1 // Initialize PCI devices (on emulators)
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "util.h" // dprintf
9 #include "pci.h" // pci_config_readl
10 #include "biosvar.h" // GET_EBDA
11 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12 #include "pci_regs.h" // PCI_COMMAND
13 #include "dev-i440fx.h"
15 #define PCI_ROM_SLOT 6
16 #define PCI_NUM_REGIONS 7
18 static void pci_bios_init_device_in_bus(int bus);
20 static struct pci_region pci_bios_io_region;
21 static struct pci_region pci_bios_mem_region;
22 static struct pci_region pci_bios_prefmem_region;
24 /* host irqs corresponding to PCI irqs A-D */
25 const u8 pci_irqs[4] = {
29 static u32 pci_bar(u16 bdf, int region_num)
31 if (region_num != PCI_ROM_SLOT) {
32 return PCI_BASE_ADDRESS_0 + region_num * 4;
35 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
36 u8 type = pci_config_readb(bdf, PCI_HEADER_TYPE);
37 type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
38 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
41 static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
45 ofs = pci_bar(bdf, region_num);
47 pci_config_writel(bdf, ofs, addr);
48 dprintf(1, "region %d: 0x%08x\n", region_num, addr);
56 static int pci_bios_allocate_region(u16 bdf, int region_num)
59 u32 ofs = pci_bar(bdf, region_num);
61 u32 old = pci_config_readl(bdf, ofs);
63 if (region_num == PCI_ROM_SLOT) {
64 mask = PCI_ROM_ADDRESS_MASK;
65 pci_config_writel(bdf, ofs, mask);
67 if (old & PCI_BASE_ADDRESS_SPACE_IO)
68 mask = PCI_BASE_ADDRESS_IO_MASK;
70 mask = PCI_BASE_ADDRESS_MEM_MASK;
71 pci_config_writel(bdf, ofs, ~0);
73 u32 val = pci_config_readl(bdf, ofs);
74 pci_config_writel(bdf, ofs, old);
76 u32 size = (~(val & mask)) + 1;
80 if (val & PCI_BASE_ADDRESS_SPACE_IO) {
81 r = &pci_bios_io_region;
84 } else if ((val & PCI_BASE_ADDRESS_MEM_PREFETCH) &&
85 /* keep behaviour on bus = 0 */
86 pci_bdf_to_bus(bdf) != 0 &&
87 /* If pci_bios_prefmem_addr == 0, keep old behaviour */
88 pci_region_addr(&pci_bios_prefmem_region) != 0) {
89 r = &pci_bios_prefmem_region;
91 msg = "decrease BUILD_PCIMEM_SIZE and recompile. size %x";
93 r = &pci_bios_mem_region;
95 msg = "increase BUILD_PCIMEM_SIZE and recompile.";
97 u32 addr = pci_region_alloc(r, size);
99 pci_set_io_region_addr(bdf, region_num, addr);
103 "%s region of (bdf 0x%x bar %d) can't be mapped. "
105 type, bdf, region_num, msg, pci_region_size(r));
109 int is_64bit = !(val & PCI_BASE_ADDRESS_SPACE_IO) &&
110 (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64;
111 if (is_64bit && size > 0) {
112 pci_config_writel(bdf, ofs + 4, 0);
117 void pci_bios_allocate_regions(u16 bdf, void *arg)
120 for (i = 0; i < PCI_NUM_REGIONS; i++) {
121 int is_64bit = pci_bios_allocate_region(bdf, i);
128 /* return the global irq number corresponding to a given device irq
129 pin. We could also use the bus number to have a more precise
131 static int pci_slot_get_pirq(u16 bdf, int irq_num)
133 int slot_addend = pci_bdf_to_dev(bdf) - 1;
134 return (irq_num + slot_addend) & 3;
137 static const struct pci_device_id pci_isa_bridge_tbl[] = {
138 /* PIIX3/PIIX4 PCI to ISA bridge */
139 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
140 piix_isa_bridge_init),
141 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
142 piix_isa_bridge_init),
147 #define PCI_IO_ALIGN 4096
148 #define PCI_IO_SHIFT 8
149 #define PCI_MEMORY_ALIGN (1UL << 20)
150 #define PCI_MEMORY_SHIFT 16
151 #define PCI_PREF_MEMORY_ALIGN (1UL << 20)
152 #define PCI_PREF_MEMORY_SHIFT 16
154 static void pci_bios_init_device_bridge(u16 bdf, void *arg)
156 pci_bios_allocate_region(bdf, 0);
157 pci_bios_allocate_region(bdf, 1);
158 pci_bios_allocate_region(bdf, PCI_ROM_SLOT);
160 u32 io_old = pci_region_addr(&pci_bios_io_region);
161 u32 mem_old = pci_region_addr(&pci_bios_mem_region);
162 u32 prefmem_old = pci_region_addr(&pci_bios_prefmem_region);
164 /* IO BASE is assumed to be 16 bit */
165 if (pci_region_align(&pci_bios_io_region, PCI_IO_ALIGN) == 0) {
166 pci_region_disable(&pci_bios_io_region);
168 if (pci_region_align(&pci_bios_mem_region, PCI_MEMORY_ALIGN) == 0) {
169 pci_region_disable(&pci_bios_mem_region);
171 if (pci_region_align(&pci_bios_prefmem_region,
172 PCI_PREF_MEMORY_ALIGN) == 0) {
173 pci_region_disable(&pci_bios_prefmem_region);
176 u32 io_base = pci_region_addr(&pci_bios_io_region);
177 u32 mem_base = pci_region_addr(&pci_bios_mem_region);
178 u32 prefmem_base = pci_region_addr(&pci_bios_prefmem_region);
180 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
182 pci_bios_init_device_in_bus(secbus);
185 u32 io_end = pci_region_align(&pci_bios_io_region, PCI_IO_ALIGN);
187 pci_region_revert(&pci_bios_io_region, io_old);
191 pci_config_writeb(bdf, PCI_IO_BASE, io_base >> PCI_IO_SHIFT);
192 pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
193 pci_config_writeb(bdf, PCI_IO_LIMIT, (io_end - 1) >> PCI_IO_SHIFT);
194 pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
196 u32 mem_end = pci_region_align(&pci_bios_mem_region, PCI_MEMORY_ALIGN);
198 pci_region_revert(&pci_bios_mem_region, mem_old);
199 mem_base = 0xffffffff;
202 pci_config_writew(bdf, PCI_MEMORY_BASE, mem_base >> PCI_MEMORY_SHIFT);
203 pci_config_writew(bdf, PCI_MEMORY_LIMIT, (mem_end -1) >> PCI_MEMORY_SHIFT);
205 u32 prefmem_end = pci_region_align(&pci_bios_prefmem_region,
206 PCI_PREF_MEMORY_ALIGN);
207 if (prefmem_end == 0) {
208 pci_region_revert(&pci_bios_prefmem_region, prefmem_old);
209 prefmem_base = 0xffffffff;
212 pci_config_writew(bdf, PCI_PREF_MEMORY_BASE,
213 prefmem_base >> PCI_PREF_MEMORY_SHIFT);
214 pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT,
215 (prefmem_end - 1) >> PCI_PREF_MEMORY_SHIFT);
216 pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, 0);
217 pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, 0);
219 dprintf(1, "PCI: br io = [0x%x, 0x%x)\n", io_base, io_end);
220 dprintf(1, "PCI: br mem = [0x%x, 0x%x)\n", mem_base, mem_end);
221 dprintf(1, "PCI: br pref = [0x%x, 0x%x)\n", prefmem_base, prefmem_end);
223 u16 cmd = pci_config_readw(bdf, PCI_COMMAND);
224 cmd &= ~PCI_COMMAND_IO;
225 if (io_end > io_base) {
226 cmd |= PCI_COMMAND_IO;
228 cmd &= ~PCI_COMMAND_MEMORY;
229 if (mem_end > mem_base || prefmem_end > prefmem_base) {
230 cmd |= PCI_COMMAND_MEMORY;
232 cmd |= PCI_COMMAND_MASTER;
233 pci_config_writew(bdf, PCI_COMMAND, cmd);
235 pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0, PCI_BRIDGE_CTL_SERR);
238 static void storage_ide_init(u16 bdf, void *arg)
240 /* IDE: we map it as in ISA mode */
241 pci_set_io_region_addr(bdf, 0, PORT_ATA1_CMD_BASE);
242 pci_set_io_region_addr(bdf, 1, PORT_ATA1_CTRL_BASE);
243 pci_set_io_region_addr(bdf, 2, PORT_ATA2_CMD_BASE);
244 pci_set_io_region_addr(bdf, 3, PORT_ATA2_CTRL_BASE);
247 static void pic_ibm_init(u16 bdf, void *arg)
249 /* PIC, IBM, MPIC & MPIC2 */
250 pci_set_io_region_addr(bdf, 0, 0x80800000 + 0x00040000);
253 static void apple_macio_init(u16 bdf, void *arg)
256 pci_set_io_region_addr(bdf, 0, 0x80800000);
259 static const struct pci_device_id pci_class_tbl[] = {
261 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
262 PCI_CLASS_STORAGE_IDE, piix_ide_init),
263 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
264 PCI_CLASS_STORAGE_IDE, piix_ide_init),
265 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
268 /* PIC, IBM, MIPC & MPIC2 */
269 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
271 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
275 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_init),
276 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_init),
279 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
280 pci_bios_init_device_bridge),
283 PCI_DEVICE(PCI_ANY_ID, PCI_ANY_ID, pci_bios_allocate_regions),
288 static const struct pci_device_id pci_device_tbl[] = {
289 /* PIIX4 Power Management device (for ACPI) */
290 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
296 static void pci_bios_init_device(u16 bdf)
298 int pin, pic_irq, vendor_id, device_id;
300 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
301 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
302 dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n"
303 , pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf), vendor_id, device_id);
304 pci_init_device(pci_class_tbl, bdf, NULL);
306 /* enable memory mappings */
307 pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
309 /* map the interrupt */
310 pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
312 pin = pci_slot_get_pirq(bdf, pin - 1);
313 pic_irq = pci_irqs[pin];
314 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pic_irq);
317 pci_init_device(pci_device_tbl, bdf, NULL);
320 static void pci_bios_init_device_in_bus(int bus)
323 foreachpci_in_bus(bdf, max, bus) {
324 pci_bios_init_device(bdf);
329 pci_bios_init_bus_rec(int bus, u8 *pci_bus)
334 dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus);
336 /* prevent accidental access to unintended devices */
337 foreachpci_in_bus(bdf, max, bus) {
338 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
339 if (class == PCI_CLASS_BRIDGE_PCI) {
340 pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255);
341 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0);
345 foreachpci_in_bus(bdf, max, bus) {
346 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
347 if (class != PCI_CLASS_BRIDGE_PCI) {
350 dprintf(1, "PCI: %s bdf = 0x%x\n", __func__, bdf);
352 u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS);
354 dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus);
355 pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus);
357 dprintf(1, "PCI: primary bus = 0x%x\n", pribus);
360 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
362 if (*pci_bus != secbus) {
363 dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n",
366 pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus);
368 dprintf(1, "PCI: secondary bus = 0x%x\n", secbus);
371 /* set to max for access to all subordinate buses.
372 later set it to accurate value */
373 u8 subbus = pci_config_readb(bdf, PCI_SUBORDINATE_BUS);
374 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255);
376 pci_bios_init_bus_rec(secbus, pci_bus);
378 if (subbus != *pci_bus) {
379 dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n",
383 dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus);
385 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus);
390 pci_bios_init_bus(void)
393 pci_bios_init_bus_rec(0 /* host bus */, &pci_bus);
400 // Already done by coreboot.
403 dprintf(3, "pci setup\n");
405 pci_region_init(&pci_bios_io_region, 0xc000, 64 * 1024 - 1);
406 pci_region_init(&pci_bios_mem_region,
407 BUILD_PCIMEM_START, BUILD_PCIMEM_END - 1);
408 pci_region_init(&pci_bios_prefmem_region,
409 BUILD_PCIPREFMEM_START, BUILD_PCIPREFMEM_END - 1);
414 foreachpci(bdf, max) {
415 pci_init_device(pci_isa_bridge_tbl, bdf, NULL);
417 pci_bios_init_device_in_bus(0 /* host bus */);