1 // Initialize PCI devices (on emulators)
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "util.h" // dprintf
9 #include "pci.h" // pci_config_readl
10 #include "biosvar.h" // GET_EBDA
11 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12 #include "pci_regs.h" // PCI_COMMAND
14 #define PCI_ROM_SLOT 6
15 #define PCI_NUM_REGIONS 7
17 static u32 pci_bios_io_addr;
18 static u32 pci_bios_mem_addr;
19 static u32 pci_bios_prefmem_addr;
20 /* host irqs corresponding to PCI irqs A-D */
21 static u8 pci_irqs[4] = {
25 static u32 pci_bar(u16 bdf, int region_num)
27 if (region_num != PCI_ROM_SLOT) {
28 return PCI_BASE_ADDRESS_0 + region_num * 4;
31 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
32 u8 type = pci_config_readb(bdf, PCI_HEADER_TYPE);
33 type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
34 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
37 static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
41 ofs = pci_bar(bdf, region_num);
43 old_addr = pci_config_readl(bdf, ofs);
45 pci_config_writel(bdf, ofs, addr);
46 dprintf(1, "region %d: 0x%08x\n", region_num, addr);
54 static int pci_bios_allocate_region(u16 bdf, int region_num)
57 u32 ofs = pci_bar(bdf, region_num);
59 u32 old = pci_config_readl(bdf, ofs);
61 if (region_num == PCI_ROM_SLOT) {
62 mask = PCI_ROM_ADDRESS_MASK;
63 pci_config_writel(bdf, ofs, mask);
65 if (old & PCI_BASE_ADDRESS_SPACE_IO)
66 mask = PCI_BASE_ADDRESS_IO_MASK;
68 mask = PCI_BASE_ADDRESS_MEM_MASK;
69 pci_config_writel(bdf, ofs, ~0);
71 u32 val = pci_config_readl(bdf, ofs);
72 pci_config_writel(bdf, ofs, old);
74 u32 size = (~(val & mask)) + 1;
76 if (val & PCI_BASE_ADDRESS_SPACE_IO) {
77 paddr = &pci_bios_io_addr;
78 if (ALIGN(*paddr, size) + size >= 64 * 1024) {
80 "io region of (bdf 0x%x bar %d) can't be mapped.\n",
84 } else if ((val & PCI_BASE_ADDRESS_MEM_PREFETCH) &&
85 /* keep behaviour on bus = 0 */
86 pci_bdf_to_bus(bdf) != 0 &&
87 /* If pci_bios_prefmem_addr == 0, keep old behaviour */
88 pci_bios_prefmem_addr != 0) {
89 paddr = &pci_bios_prefmem_addr;
90 if (ALIGN(*paddr, size) + size >= BUILD_PCIPREFMEM_END) {
92 "prefmem region of (bdf 0x%x bar %d) can't be mapped. "
93 "decrease BUILD_PCIMEM_SIZE and recompile. size %x\n",
94 bdf, region_num, BUILD_PCIPREFMEM_SIZE);
98 paddr = &pci_bios_mem_addr;
99 if (ALIGN(*paddr, size) + size >= BUILD_PCIMEM_END) {
101 "mem region of (bdf 0x%x bar %d) can't be mapped. "
102 "increase BUILD_PCIMEM_SIZE and recompile. size %x\n",
103 bdf, region_num, BUILD_PCIMEM_SIZE);
108 *paddr = ALIGN(*paddr, size);
109 pci_set_io_region_addr(bdf, region_num, *paddr);
114 int is_64bit = !(val & PCI_BASE_ADDRESS_SPACE_IO) &&
115 (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64;
118 pci_config_writel(bdf, ofs + 4, 0);
120 pci_config_writel(bdf, ofs + 4, ~0);
126 static void pci_bios_allocate_regions(u16 bdf)
129 for (i = 0; i < PCI_NUM_REGIONS; i++) {
130 int is_64bit = pci_bios_allocate_region(bdf, i);
137 /* return the global irq number corresponding to a given device irq
138 pin. We could also use the bus number to have a more precise
140 static int pci_slot_get_pirq(u16 bdf, int irq_num)
142 int slot_addend = pci_bdf_to_dev(bdf) - 1;
143 return (irq_num + slot_addend) & 3;
146 static void pci_bios_init_bridges(u16 bdf)
148 u16 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
149 u16 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
151 if (vendor_id == PCI_VENDOR_ID_INTEL
152 && (device_id == PCI_DEVICE_ID_INTEL_82371SB_0
153 || device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
157 /* PIIX3/PIIX4 PCI to ISA bridge */
161 for (i = 0; i < 4; i++) {
163 /* set to trigger level */
164 elcr[irq >> 3] |= (1 << (irq & 7));
165 /* activate irq remapping in PIIX */
166 pci_config_writeb(bdf, 0x60 + i, irq);
168 outb(elcr[0], 0x4d0);
169 outb(elcr[1], 0x4d1);
170 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n",
175 static void pci_bios_init_device(u16 bdf)
178 int pin, pic_irq, vendor_id, device_id;
180 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
181 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
182 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
183 dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n"
184 , pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf), vendor_id, device_id);
186 case PCI_CLASS_STORAGE_IDE:
187 if (vendor_id == PCI_VENDOR_ID_INTEL
188 && (device_id == PCI_DEVICE_ID_INTEL_82371SB_1
189 || device_id == PCI_DEVICE_ID_INTEL_82371AB)) {
190 /* PIIX3/PIIX4 IDE */
191 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
192 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
193 pci_bios_allocate_regions(bdf);
195 /* IDE: we map it as in ISA mode */
196 pci_set_io_region_addr(bdf, 0, PORT_ATA1_CMD_BASE);
197 pci_set_io_region_addr(bdf, 1, PORT_ATA1_CTRL_BASE);
198 pci_set_io_region_addr(bdf, 2, PORT_ATA2_CMD_BASE);
199 pci_set_io_region_addr(bdf, 3, PORT_ATA2_CTRL_BASE);
202 case PCI_CLASS_SYSTEM_PIC:
204 if (vendor_id == PCI_VENDOR_ID_IBM) {
206 if (device_id == 0x0046 || device_id == 0xFFFF) {
208 pci_set_io_region_addr(bdf, 0, 0x80800000 + 0x00040000);
213 if (vendor_id == PCI_VENDOR_ID_APPLE &&
214 (device_id == 0x0017 || device_id == 0x0022)) {
216 pci_set_io_region_addr(bdf, 0, 0x80800000);
220 /* default memory mappings */
221 pci_bios_allocate_regions(bdf);
225 /* enable memory mappings */
226 pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
228 /* map the interrupt */
229 pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
231 pin = pci_slot_get_pirq(bdf, pin - 1);
232 pic_irq = pci_irqs[pin];
233 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pic_irq);
236 if (vendor_id == PCI_VENDOR_ID_INTEL
237 && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
238 /* PIIX4 Power Management device (for ACPI) */
240 // acpi sci is hardwired to 9
241 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
243 pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
244 pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
245 pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
246 pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
254 // Already done by coreboot.
257 dprintf(3, "pci setup\n");
259 pci_bios_io_addr = 0xc000;
260 pci_bios_mem_addr = BUILD_PCIMEM_START;
261 pci_bios_prefmem_addr = BUILD_PCIPREFMEM_START;
264 foreachpci(bdf, max) {
265 pci_bios_init_bridges(bdf);
267 foreachpci(bdf, max) {
268 pci_bios_init_device(bdf);