1 // Initialize PCI devices (on emulators)
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "util.h" // dprintf
9 #include "pci.h" // pci_config_readl
10 #include "biosvar.h" // GET_EBDA
11 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12 #include "pci_regs.h" // PCI_COMMAND
14 #define PCI_ROM_SLOT 6
15 #define PCI_NUM_REGIONS 7
17 static u32 pci_bios_io_addr;
18 static u32 pci_bios_mem_addr;
19 static u32 pci_bios_prefmem_addr;
20 /* host irqs corresponding to PCI irqs A-D */
21 static u8 pci_irqs[4] = {
25 static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
29 if (region_num == PCI_ROM_SLOT) {
30 ofs = PCI_ROM_ADDRESS;
32 ofs = PCI_BASE_ADDRESS_0 + region_num * 4;
35 old_addr = pci_config_readl(bdf, ofs);
37 pci_config_writel(bdf, ofs, addr);
38 dprintf(1, "region %d: 0x%08x\n", region_num, addr);
46 static int pci_bios_allocate_region(u16 bdf, int region_num)
50 if (region_num == PCI_ROM_SLOT)
51 ofs = PCI_ROM_ADDRESS;
53 ofs = PCI_BASE_ADDRESS_0 + region_num * 4;
55 u32 old = pci_config_readl(bdf, ofs);
57 if (region_num == PCI_ROM_SLOT) {
58 mask = PCI_ROM_ADDRESS_MASK;
59 pci_config_writel(bdf, ofs, mask);
61 if (old & PCI_BASE_ADDRESS_SPACE_IO)
62 mask = PCI_BASE_ADDRESS_IO_MASK;
64 mask = PCI_BASE_ADDRESS_MEM_MASK;
65 pci_config_writel(bdf, ofs, ~0);
67 u32 val = pci_config_readl(bdf, ofs);
68 pci_config_writel(bdf, ofs, old);
70 u32 size = (~(val & mask)) + 1;
72 if (val & PCI_BASE_ADDRESS_SPACE_IO) {
73 paddr = &pci_bios_io_addr;
74 if (ALIGN(*paddr, size) + size >= 64 * 1024) {
76 "io region of (bdf 0x%x bar %d) can't be mapped.\n",
80 } else if ((val & PCI_BASE_ADDRESS_MEM_PREFETCH) &&
81 /* keep behaviour on bus = 0 */
82 pci_bdf_to_bus(bdf) != 0 &&
83 /* If pci_bios_prefmem_addr == 0, keep old behaviour */
84 pci_bios_prefmem_addr != 0) {
85 paddr = &pci_bios_prefmem_addr;
86 if (ALIGN(*paddr, size) + size >= BUILD_PCIPREFMEM_END) {
88 "prefmem region of (bdf 0x%x bar %d) can't be mapped. "
89 "decrease BUILD_PCIMEM_SIZE and recompile. size %x\n",
90 bdf, region_num, BUILD_PCIPREFMEM_SIZE);
94 paddr = &pci_bios_mem_addr;
95 if (ALIGN(*paddr, size) + size >= BUILD_PCIMEM_END) {
97 "mem region of (bdf 0x%x bar %d) can't be mapped. "
98 "increase BUILD_PCIMEM_SIZE and recompile. size %x\n",
99 bdf, region_num, BUILD_PCIMEM_SIZE);
104 *paddr = ALIGN(*paddr, size);
105 pci_set_io_region_addr(bdf, region_num, *paddr);
110 int is_64bit = !(val & PCI_BASE_ADDRESS_SPACE_IO) &&
111 (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64;
114 pci_config_writel(bdf, ofs + 4, 0);
116 pci_config_writel(bdf, ofs + 4, ~0);
122 static void pci_bios_allocate_regions(u16 bdf)
125 for (i = 0; i < PCI_NUM_REGIONS; i++) {
126 int is_64bit = pci_bios_allocate_region(bdf, i);
133 /* return the global irq number corresponding to a given device irq
134 pin. We could also use the bus number to have a more precise
136 static int pci_slot_get_pirq(u16 bdf, int irq_num)
138 int slot_addend = pci_bdf_to_dev(bdf) - 1;
139 return (irq_num + slot_addend) & 3;
142 static void pci_bios_init_bridges(u16 bdf)
144 u16 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
145 u16 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
147 if (vendor_id == PCI_VENDOR_ID_INTEL
148 && (device_id == PCI_DEVICE_ID_INTEL_82371SB_0
149 || device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
153 /* PIIX3/PIIX4 PCI to ISA bridge */
157 for (i = 0; i < 4; i++) {
159 /* set to trigger level */
160 elcr[irq >> 3] |= (1 << (irq & 7));
161 /* activate irq remapping in PIIX */
162 pci_config_writeb(bdf, 0x60 + i, irq);
164 outb(elcr[0], 0x4d0);
165 outb(elcr[1], 0x4d1);
166 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n",
171 static void pci_bios_init_device(u16 bdf)
174 int pin, pic_irq, vendor_id, device_id;
176 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
177 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
178 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
179 dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n"
180 , pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf), vendor_id, device_id);
182 case PCI_CLASS_STORAGE_IDE:
183 if (vendor_id == PCI_VENDOR_ID_INTEL
184 && (device_id == PCI_DEVICE_ID_INTEL_82371SB_1
185 || device_id == PCI_DEVICE_ID_INTEL_82371AB)) {
186 /* PIIX3/PIIX4 IDE */
187 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
188 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
189 pci_bios_allocate_regions(bdf);
191 /* IDE: we map it as in ISA mode */
192 pci_set_io_region_addr(bdf, 0, PORT_ATA1_CMD_BASE);
193 pci_set_io_region_addr(bdf, 1, PORT_ATA1_CTRL_BASE);
194 pci_set_io_region_addr(bdf, 2, PORT_ATA2_CMD_BASE);
195 pci_set_io_region_addr(bdf, 3, PORT_ATA2_CTRL_BASE);
198 case PCI_CLASS_SYSTEM_PIC:
200 if (vendor_id == PCI_VENDOR_ID_IBM) {
202 if (device_id == 0x0046 || device_id == 0xFFFF) {
204 pci_set_io_region_addr(bdf, 0, 0x80800000 + 0x00040000);
209 if (vendor_id == PCI_VENDOR_ID_APPLE &&
210 (device_id == 0x0017 || device_id == 0x0022)) {
212 pci_set_io_region_addr(bdf, 0, 0x80800000);
216 /* default memory mappings */
217 pci_bios_allocate_regions(bdf);
221 /* enable memory mappings */
222 pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
224 /* map the interrupt */
225 pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
227 pin = pci_slot_get_pirq(bdf, pin - 1);
228 pic_irq = pci_irqs[pin];
229 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pic_irq);
232 if (vendor_id == PCI_VENDOR_ID_INTEL
233 && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
234 /* PIIX4 Power Management device (for ACPI) */
236 // acpi sci is hardwired to 9
237 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
239 pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
240 pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
241 pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
242 pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
250 // Already done by coreboot.
253 dprintf(3, "pci setup\n");
255 pci_bios_io_addr = 0xc000;
256 pci_bios_mem_addr = BUILD_PCIMEM_START;
257 pci_bios_prefmem_addr = BUILD_PCIPREFMEM_START;
260 foreachpci(bdf, max) {
261 pci_bios_init_bridges(bdf);
263 foreachpci(bdf, max) {
264 pci_bios_init_device(bdf);