1 // Initialize PCI devices (on emulators)
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "util.h" // dprintf
9 #include "pci.h" // pci_config_readl
10 #include "biosvar.h" // GET_EBDA
11 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12 #include "pci_regs.h" // PCI_COMMAND
13 #include "xen.h" // usingXen
15 #define PCI_IO_INDEX_SHIFT 2
16 #define PCI_MEM_INDEX_SHIFT 12
18 #define PCI_BRIDGE_IO_MIN 0x1000
19 #define PCI_BRIDGE_MEM_MIN 0x100000
21 enum pci_region_type {
24 PCI_REGION_TYPE_PREFMEM,
25 PCI_REGION_TYPE_COUNT,
28 static const char *region_type_name[] = {
29 [ PCI_REGION_TYPE_IO ] = "io",
30 [ PCI_REGION_TYPE_MEM ] = "mem",
31 [ PCI_REGION_TYPE_PREFMEM ] = "prefmem",
34 static struct pci_bus {
36 /* pci region stats */
37 u32 count[32 - PCI_MEM_INDEX_SHIFT];
39 /* seconday bus region sizes */
41 /* pci region assignments */
42 u32 bases[32 - PCI_MEM_INDEX_SHIFT];
44 } r[PCI_REGION_TYPE_COUNT];
46 static int busses_count;
48 static int pci_size_to_index(u32 size, enum pci_region_type type)
50 int index = __fls(size);
51 int shift = (type == PCI_REGION_TYPE_IO) ?
52 PCI_IO_INDEX_SHIFT : PCI_MEM_INDEX_SHIFT;
60 static u32 pci_index_to_size(int index, enum pci_region_type type)
62 int shift = (type == PCI_REGION_TYPE_IO) ?
63 PCI_IO_INDEX_SHIFT : PCI_MEM_INDEX_SHIFT;
65 return 0x1 << (index + shift);
68 static enum pci_region_type pci_addr_to_type(u32 addr)
70 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
71 return PCI_REGION_TYPE_IO;
72 if (addr & PCI_BASE_ADDRESS_MEM_PREFETCH)
73 return PCI_REGION_TYPE_PREFMEM;
74 return PCI_REGION_TYPE_MEM;
77 static u32 pci_bar(u16 bdf, int region_num)
79 if (region_num != PCI_ROM_SLOT) {
80 return PCI_BASE_ADDRESS_0 + region_num * 4;
83 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
84 u8 type = pci_config_readb(bdf, PCI_HEADER_TYPE);
85 type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
86 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
89 static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
93 ofs = pci_bar(bdf, region_num);
95 pci_config_writel(bdf, ofs, addr);
99 /****************************************************************
101 ****************************************************************/
103 /* host irqs corresponding to PCI irqs A-D */
104 const u8 pci_irqs[4] = {
108 /* return the global irq number corresponding to a given device irq
109 pin. We could also use the bus number to have a more precise
111 static int pci_slot_get_pirq(u16 bdf, int irq_num)
113 int slot_addend = pci_bdf_to_dev(bdf) - 1;
114 return (irq_num + slot_addend) & 3;
117 /* PIIX3/PIIX4 PCI to ISA bridge */
118 static void piix_isa_bridge_init(struct pci_device *pci, void *arg)
125 for (i = 0; i < 4; i++) {
127 /* set to trigger level */
128 elcr[irq >> 3] |= (1 << (irq & 7));
129 /* activate irq remapping in PIIX */
130 pci_config_writeb(pci->bdf, 0x60 + i, irq);
132 outb(elcr[0], 0x4d0);
133 outb(elcr[1], 0x4d1);
134 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
137 static const struct pci_device_id pci_isa_bridge_tbl[] = {
138 /* PIIX3/PIIX4 PCI to ISA bridge */
139 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
140 piix_isa_bridge_init),
141 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
142 piix_isa_bridge_init),
147 static void storage_ide_init(struct pci_device *pci, void *arg)
150 /* IDE: we map it as in ISA mode */
151 pci_set_io_region_addr(bdf, 0, PORT_ATA1_CMD_BASE);
152 pci_set_io_region_addr(bdf, 1, PORT_ATA1_CTRL_BASE);
153 pci_set_io_region_addr(bdf, 2, PORT_ATA2_CMD_BASE);
154 pci_set_io_region_addr(bdf, 3, PORT_ATA2_CTRL_BASE);
157 /* PIIX3/PIIX4 IDE */
158 static void piix_ide_init(struct pci_device *pci, void *arg)
161 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
162 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
165 static void pic_ibm_init(struct pci_device *pci, void *arg)
167 /* PIC, IBM, MPIC & MPIC2 */
168 pci_set_io_region_addr(pci->bdf, 0, 0x80800000 + 0x00040000);
171 static void apple_macio_init(struct pci_device *pci, void *arg)
174 pci_set_io_region_addr(pci->bdf, 0, 0x80800000);
177 static const struct pci_device_id pci_class_tbl[] = {
179 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
180 PCI_CLASS_STORAGE_IDE, piix_ide_init),
181 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
182 PCI_CLASS_STORAGE_IDE, piix_ide_init),
183 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
186 /* PIC, IBM, MIPC & MPIC2 */
187 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
189 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
193 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_init),
194 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_init),
199 /* PIIX4 Power Management device (for ACPI) */
200 static void piix4_pm_init(struct pci_device *pci, void *arg)
203 // acpi sci is hardwired to 9
204 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
206 pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
207 pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
208 pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
209 pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
212 static const struct pci_device_id pci_device_tbl[] = {
213 /* PIIX4 Power Management device (for ACPI) */
214 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
220 static void pci_bios_init_device(struct pci_device *pci)
225 dprintf(1, "PCI: init bdf=%02x:%02x.%x id=%04x:%04x\n"
226 , pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf)
227 , pci->vendor, pci->device);
228 pci_init_device(pci_class_tbl, pci, NULL);
230 /* enable memory mappings */
231 pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
233 /* map the interrupt */
234 pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
236 pin = pci_slot_get_pirq(bdf, pin - 1);
237 pic_irq = pci_irqs[pin];
238 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pic_irq);
241 pci_init_device(pci_device_tbl, pci, NULL);
244 static void pci_bios_init_device_in_bus(int bus)
246 struct pci_device *pci;
248 u8 pci_bus = pci_bdf_to_bus(pci->bdf);
253 pci_bios_init_device(pci);
258 /****************************************************************
260 ****************************************************************/
263 pci_bios_init_bus_rec(int bus, u8 *pci_bus)
268 dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus);
270 /* prevent accidental access to unintended devices */
271 foreachbdf(bdf, bus) {
272 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
273 if (class == PCI_CLASS_BRIDGE_PCI) {
274 pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255);
275 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0);
279 foreachbdf(bdf, bus) {
280 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
281 if (class != PCI_CLASS_BRIDGE_PCI) {
284 dprintf(1, "PCI: %s bdf = 0x%x\n", __func__, bdf);
286 u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS);
288 dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus);
289 pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus);
291 dprintf(1, "PCI: primary bus = 0x%x\n", pribus);
294 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
296 if (*pci_bus != secbus) {
297 dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n",
300 pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus);
302 dprintf(1, "PCI: secondary bus = 0x%x\n", secbus);
305 /* set to max for access to all subordinate buses.
306 later set it to accurate value */
307 u8 subbus = pci_config_readb(bdf, PCI_SUBORDINATE_BUS);
308 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255);
310 pci_bios_init_bus_rec(secbus, pci_bus);
312 if (subbus != *pci_bus) {
313 dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n",
317 dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus);
319 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus);
324 pci_bios_init_bus(void)
327 pci_bios_init_bus_rec(0 /* host bus */, &pci_bus);
328 busses_count = pci_bus + 1;
332 /****************************************************************
334 ****************************************************************/
336 static u32 pci_size_roundup(u32 size)
338 int index = __fls(size-1)+1;
342 static void pci_bios_bus_get_bar(struct pci_bus *bus, int bdf, int bar,
345 u32 ofs = pci_bar(bdf, bar);
346 u32 old = pci_config_readl(bdf, ofs);
349 if (bar == PCI_ROM_SLOT) {
350 mask = PCI_ROM_ADDRESS_MASK;
351 pci_config_writel(bdf, ofs, mask);
353 if (old & PCI_BASE_ADDRESS_SPACE_IO)
354 mask = PCI_BASE_ADDRESS_IO_MASK;
356 mask = PCI_BASE_ADDRESS_MEM_MASK;
357 pci_config_writel(bdf, ofs, ~0);
359 *val = pci_config_readl(bdf, ofs);
360 pci_config_writel(bdf, ofs, old);
361 *size = (~(*val & mask)) + 1;
364 static void pci_bios_bus_reserve(struct pci_bus *bus, int type, u32 size)
368 index = pci_size_to_index(size, type);
369 size = pci_index_to_size(index, type);
370 bus->r[type].count[index]++;
371 bus->r[type].sum += size;
372 if (bus->r[type].max < size)
373 bus->r[type].max = size;
376 static void pci_bios_check_device_in_bus(int bus);
378 static void pci_bios_check_device(struct pci_bus *bus, struct pci_device *dev)
384 if (dev->class == PCI_CLASS_BRIDGE_PCI) {
385 if (dev->secondary_bus >= busses_count) {
386 /* should never trigger */
387 dprintf(1, "PCI: bus count too small (%d), skipping bus #%d\n",
388 busses_count, dev->secondary_bus);
391 struct pci_bus *s = busses + dev->secondary_bus;
392 pci_bios_check_device_in_bus(dev->secondary_bus);
393 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
394 limit = (type == PCI_REGION_TYPE_IO) ?
395 PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN;
396 s->r[type].size = s->r[type].sum;
397 if (s->r[type].size < limit)
398 s->r[type].size = limit;
399 s->r[type].size = pci_size_roundup(s->r[type].size);
400 pci_bios_bus_reserve(bus, type, s->r[type].size);
402 dprintf(1, "PCI: secondary bus %d sizes: io %x, mem %x, prefmem %x\n",
404 s->r[PCI_REGION_TYPE_IO].size,
405 s->r[PCI_REGION_TYPE_MEM].size,
406 s->r[PCI_REGION_TYPE_PREFMEM].size);
410 for (i = 0; i < PCI_NUM_REGIONS; i++) {
412 pci_bios_bus_get_bar(bus, bdf, i, &val, &size);
416 pci_bios_bus_reserve(bus, pci_addr_to_type(val), size);
417 dev->bars[i].addr = val;
418 dev->bars[i].size = size;
419 dev->bars[i].is64 = (!(val & PCI_BASE_ADDRESS_SPACE_IO) &&
420 (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64);
422 if (dev->bars[i].is64) {
428 static void pci_bios_check_device_in_bus(int bus)
430 struct pci_device *pci;
432 dprintf(1, "PCI: check devices bus %d\n", bus);
434 if (pci_bdf_to_bus(pci->bdf) != bus)
436 pci_bios_check_device(&busses[bus], pci);
440 #define ROOT_BASE(top, sum, max) ALIGN_DOWN((top)-(sum),(max) ?: 1)
442 static int pci_bios_init_root_regions(u32 start, u32 end)
444 struct pci_bus *bus = &busses[0];
446 bus->r[PCI_REGION_TYPE_IO].base = 0xc000;
448 if (bus->r[PCI_REGION_TYPE_MEM].sum < bus->r[PCI_REGION_TYPE_PREFMEM].sum) {
449 bus->r[PCI_REGION_TYPE_MEM].base =
451 bus->r[PCI_REGION_TYPE_MEM].sum,
452 bus->r[PCI_REGION_TYPE_MEM].max);
453 bus->r[PCI_REGION_TYPE_PREFMEM].base =
454 ROOT_BASE(bus->r[PCI_REGION_TYPE_MEM].base,
455 bus->r[PCI_REGION_TYPE_PREFMEM].sum,
456 bus->r[PCI_REGION_TYPE_PREFMEM].max);
457 if (bus->r[PCI_REGION_TYPE_PREFMEM].base >= start) {
461 bus->r[PCI_REGION_TYPE_PREFMEM].base =
463 bus->r[PCI_REGION_TYPE_PREFMEM].sum,
464 bus->r[PCI_REGION_TYPE_PREFMEM].max);
465 bus->r[PCI_REGION_TYPE_MEM].base =
466 ROOT_BASE(bus->r[PCI_REGION_TYPE_PREFMEM].base,
467 bus->r[PCI_REGION_TYPE_MEM].sum,
468 bus->r[PCI_REGION_TYPE_MEM].max);
469 if (bus->r[PCI_REGION_TYPE_MEM].base >= start) {
477 /****************************************************************
479 ****************************************************************/
481 static void pci_bios_init_bus_bases(struct pci_bus *bus)
483 u32 base, newbase, size;
486 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
487 dprintf(1, " type %s max %x sum %x base %x\n", region_type_name[type],
488 bus->r[type].max, bus->r[type].sum, bus->r[type].base);
489 base = bus->r[type].base;
490 for (i = ARRAY_SIZE(bus->r[type].count)-1; i >= 0; i--) {
491 size = pci_index_to_size(i, type);
492 if (!bus->r[type].count[i])
494 newbase = base + size * bus->r[type].count[i];
495 dprintf(1, " size %8x: %d bar(s), %8x -> %8x\n",
496 size, bus->r[type].count[i], base, newbase - 1);
497 bus->r[type].bases[i] = base;
503 static u32 pci_bios_bus_get_addr(struct pci_bus *bus, int type, u32 size)
507 index = pci_size_to_index(size, type);
508 addr = bus->r[type].bases[index];
509 bus->r[type].bases[index] += pci_index_to_size(index, type);
513 #define PCI_IO_SHIFT 8
514 #define PCI_MEMORY_SHIFT 16
515 #define PCI_PREF_MEMORY_SHIFT 16
517 static void pci_bios_map_device_in_bus(int bus);
519 static void pci_bios_map_device(struct pci_bus *bus, struct pci_device *dev)
524 if (dev->class == PCI_CLASS_BRIDGE_PCI) {
525 if (dev->secondary_bus >= busses_count) {
528 struct pci_bus *s = busses + dev->secondary_bus;
531 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
532 s->r[type].base = pci_bios_bus_get_addr(bus, type, s->r[type].size);
534 dprintf(1, "PCI: init bases bus %d (secondary)\n", dev->secondary_bus);
535 pci_bios_init_bus_bases(s);
537 base = s->r[PCI_REGION_TYPE_IO].base;
538 limit = base + s->r[PCI_REGION_TYPE_IO].size - 1;
539 pci_config_writeb(bdf, PCI_IO_BASE, base >> PCI_IO_SHIFT);
540 pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
541 pci_config_writeb(bdf, PCI_IO_LIMIT, limit >> PCI_IO_SHIFT);
542 pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
544 base = s->r[PCI_REGION_TYPE_MEM].base;
545 limit = base + s->r[PCI_REGION_TYPE_MEM].size - 1;
546 pci_config_writew(bdf, PCI_MEMORY_BASE, base >> PCI_MEMORY_SHIFT);
547 pci_config_writew(bdf, PCI_MEMORY_LIMIT, limit >> PCI_MEMORY_SHIFT);
549 base = s->r[PCI_REGION_TYPE_PREFMEM].base;
550 limit = base + s->r[PCI_REGION_TYPE_PREFMEM].size - 1;
551 pci_config_writew(bdf, PCI_PREF_MEMORY_BASE, base >> PCI_PREF_MEMORY_SHIFT);
552 pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT, limit >> PCI_PREF_MEMORY_SHIFT);
553 pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, 0);
554 pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, 0);
556 pci_bios_map_device_in_bus(dev->secondary_bus);
560 for (i = 0; i < PCI_NUM_REGIONS; i++) {
562 if (dev->bars[i].addr == 0) {
566 addr = pci_bios_bus_get_addr(bus, pci_addr_to_type(dev->bars[i].addr),
568 dprintf(1, " bar %d, addr %x, size %x [%s]\n",
569 i, addr, dev->bars[i].size,
570 region_type_name[pci_addr_to_type(dev->bars[i].addr)]);
571 pci_set_io_region_addr(bdf, i, addr);
573 if (dev->bars[i].is64) {
579 static void pci_bios_map_device_in_bus(int bus)
581 struct pci_device *pci;
585 if (pci_bdf_to_bus(bdf) != bus)
587 dprintf(1, "PCI: map device bdf=%02x:%02x.%x\n"
588 , pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf));
589 pci_bios_map_device(&busses[bus], pci);
594 /****************************************************************
596 ****************************************************************/
601 if (CONFIG_COREBOOT || usingXen()) {
602 // PCI setup already done by coreboot or Xen - just do probe.
607 dprintf(3, "pci setup\n");
609 u32 start = BUILD_PCIMEM_START;
610 u32 end = BUILD_PCIMEM_END;
612 dprintf(1, "=== PCI bus & bridge init ===\n");
613 if (pci_probe_host() != 0) {
618 dprintf(1, "=== PCI device probing ===\n");
621 dprintf(1, "=== PCI new allocation pass #1 ===\n");
622 busses = malloc_tmp(sizeof(*busses) * busses_count);
623 memset(busses, 0, sizeof(*busses) * busses_count);
624 pci_bios_check_device_in_bus(0 /* host bus */);
625 if (pci_bios_init_root_regions(start, end) != 0) {
626 panic("PCI: out of address space\n");
629 dprintf(1, "=== PCI new allocation pass #2 ===\n");
630 dprintf(1, "PCI: init bases bus 0 (primary)\n");
631 pci_bios_init_bus_bases(&busses[0]);
632 pci_bios_map_device_in_bus(0 /* host bus */);
634 pci_bios_init_device_in_bus(0 /* host bus */);
636 struct pci_device *pci;
638 pci_init_device(pci_isa_bridge_tbl, pci, NULL);