1 // Initialize PCI devices (on emulators)
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "util.h" // dprintf
9 #include "pci.h" // pci_config_readl
10 #include "biosvar.h" // GET_EBDA
11 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12 #include "pci_regs.h" // PCI_COMMAND
13 #include "xen.h" // usingXen
15 #define PCI_IO_INDEX_SHIFT 2
16 #define PCI_MEM_INDEX_SHIFT 12
18 #define PCI_BRIDGE_IO_MIN 0x1000
19 #define PCI_BRIDGE_MEM_MIN 0x100000
21 static struct pci_region pci_bios_io_region;
22 static struct pci_region pci_bios_mem_region;
23 static struct pci_region pci_bios_prefmem_region;
25 enum pci_region_type {
28 PCI_REGION_TYPE_PREFMEM,
29 PCI_REGION_TYPE_COUNT,
32 static const char *region_type_name[] = {
33 [ PCI_REGION_TYPE_IO ] = "io",
34 [ PCI_REGION_TYPE_MEM ] = "mem",
35 [ PCI_REGION_TYPE_PREFMEM ] = "prefmem",
38 static struct pci_bus {
40 /* pci region stats */
41 u32 count[32 - PCI_MEM_INDEX_SHIFT];
43 /* seconday bus region sizes */
45 /* pci region assignments */
46 u32 bases[32 - PCI_MEM_INDEX_SHIFT];
48 } r[PCI_REGION_TYPE_COUNT];
50 static int busses_count;
52 static void pci_bios_init_device_in_bus(int bus);
53 static void pci_bios_check_device_in_bus(int bus);
54 static void pci_bios_init_bus_bases(struct pci_bus *bus);
55 static void pci_bios_map_device_in_bus(int bus);
57 static int pci_size_to_index(u32 size, enum pci_region_type type)
59 int index = __fls(size);
60 int shift = (type == PCI_REGION_TYPE_IO) ?
61 PCI_IO_INDEX_SHIFT : PCI_MEM_INDEX_SHIFT;
69 static u32 pci_index_to_size(int index, enum pci_region_type type)
71 int shift = (type == PCI_REGION_TYPE_IO) ?
72 PCI_IO_INDEX_SHIFT : PCI_MEM_INDEX_SHIFT;
74 return 0x1 << (index + shift);
77 static enum pci_region_type pci_addr_to_type(u32 addr)
79 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
80 return PCI_REGION_TYPE_IO;
81 if (addr & PCI_BASE_ADDRESS_MEM_PREFETCH)
82 return PCI_REGION_TYPE_PREFMEM;
83 return PCI_REGION_TYPE_MEM;
86 static u32 pci_size_roundup(u32 size)
88 int index = __fls(size-1)+1;
92 /* host irqs corresponding to PCI irqs A-D */
93 const u8 pci_irqs[4] = {
97 static u32 pci_bar(u16 bdf, int region_num)
99 if (region_num != PCI_ROM_SLOT) {
100 return PCI_BASE_ADDRESS_0 + region_num * 4;
103 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
104 u8 type = pci_config_readb(bdf, PCI_HEADER_TYPE);
105 type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
106 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
109 static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
113 ofs = pci_bar(bdf, region_num);
115 pci_config_writel(bdf, ofs, addr);
116 dprintf(1, "region %d: 0x%08x\n", region_num, addr);
124 static int pci_bios_allocate_region(u16 bdf, int region_num)
128 struct pci_region *r;
129 u32 ofs = pci_bar(bdf, region_num);
131 u32 old = pci_config_readl(bdf, ofs);
133 if (region_num == PCI_ROM_SLOT) {
134 mask = PCI_ROM_ADDRESS_MASK;
135 pci_config_writel(bdf, ofs, mask);
137 if (old & PCI_BASE_ADDRESS_SPACE_IO)
138 mask = PCI_BASE_ADDRESS_IO_MASK;
140 mask = PCI_BASE_ADDRESS_MEM_MASK;
141 pci_config_writel(bdf, ofs, ~0);
143 u32 val = pci_config_readl(bdf, ofs);
144 pci_config_writel(bdf, ofs, old);
146 u32 size = (~(val & mask)) + 1;
150 if (val & PCI_BASE_ADDRESS_SPACE_IO) {
151 r = &pci_bios_io_region;
154 } else if ((val & PCI_BASE_ADDRESS_MEM_PREFETCH) &&
155 /* keep behaviour on bus = 0 */
156 pci_bdf_to_bus(bdf) != 0 &&
157 /* If pci_bios_prefmem_addr == 0, keep old behaviour */
158 pci_region_addr(&pci_bios_prefmem_region) != 0) {
159 r = &pci_bios_prefmem_region;
161 msg = "decrease BUILD_PCIMEM_SIZE and recompile. size %x";
163 r = &pci_bios_mem_region;
165 msg = "increase BUILD_PCIMEM_SIZE and recompile.";
167 u32 addr = pci_region_alloc(r, size);
169 pci_set_io_region_addr(bdf, region_num, addr);
173 "%s region of (bdf 0x%x bar %d) can't be mapped. "
175 type, bdf, region_num, msg, pci_region_size(r));
179 int is_64bit = !(val & PCI_BASE_ADDRESS_SPACE_IO) &&
180 (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64;
181 if (is_64bit && size > 0) {
182 pci_config_writel(bdf, ofs + 4, 0);
187 static void pci_bios_allocate_regions(struct pci_device *pci, void *arg)
192 for (i = 0; i < PCI_NUM_REGIONS; i++) {
193 int is_64bit = pci_bios_allocate_region(pci->bdf, i);
200 /* return the global irq number corresponding to a given device irq
201 pin. We could also use the bus number to have a more precise
203 static int pci_slot_get_pirq(u16 bdf, int irq_num)
205 int slot_addend = pci_bdf_to_dev(bdf) - 1;
206 return (irq_num + slot_addend) & 3;
209 /* PIIX3/PIIX4 PCI to ISA bridge */
210 static void piix_isa_bridge_init(struct pci_device *pci, void *arg)
217 for (i = 0; i < 4; i++) {
219 /* set to trigger level */
220 elcr[irq >> 3] |= (1 << (irq & 7));
221 /* activate irq remapping in PIIX */
222 pci_config_writeb(pci->bdf, 0x60 + i, irq);
224 outb(elcr[0], 0x4d0);
225 outb(elcr[1], 0x4d1);
226 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
229 static const struct pci_device_id pci_isa_bridge_tbl[] = {
230 /* PIIX3/PIIX4 PCI to ISA bridge */
231 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
232 piix_isa_bridge_init),
233 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
234 piix_isa_bridge_init),
239 #define PCI_IO_ALIGN 4096
240 #define PCI_IO_SHIFT 8
241 #define PCI_MEMORY_ALIGN (1UL << 20)
242 #define PCI_MEMORY_SHIFT 16
243 #define PCI_PREF_MEMORY_ALIGN (1UL << 20)
244 #define PCI_PREF_MEMORY_SHIFT 16
247 static void pci_bios_init_device_bridge(struct pci_device *pci, void *arg)
250 pci_bios_allocate_region(bdf, 0);
251 pci_bios_allocate_region(bdf, 1);
252 pci_bios_allocate_region(bdf, PCI_ROM_SLOT);
254 u32 io_old = pci_region_addr(&pci_bios_io_region);
255 u32 mem_old = pci_region_addr(&pci_bios_mem_region);
256 u32 prefmem_old = pci_region_addr(&pci_bios_prefmem_region);
258 /* IO BASE is assumed to be 16 bit */
259 if (pci_region_align(&pci_bios_io_region, PCI_IO_ALIGN) == 0) {
260 pci_region_disable(&pci_bios_io_region);
262 if (pci_region_align(&pci_bios_mem_region, PCI_MEMORY_ALIGN) == 0) {
263 pci_region_disable(&pci_bios_mem_region);
265 if (pci_region_align(&pci_bios_prefmem_region,
266 PCI_PREF_MEMORY_ALIGN) == 0) {
267 pci_region_disable(&pci_bios_prefmem_region);
270 u32 io_base = pci_region_addr(&pci_bios_io_region);
271 u32 mem_base = pci_region_addr(&pci_bios_mem_region);
272 u32 prefmem_base = pci_region_addr(&pci_bios_prefmem_region);
274 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
276 pci_bios_init_device_in_bus(secbus);
279 u32 io_end = pci_region_align(&pci_bios_io_region, PCI_IO_ALIGN);
281 pci_region_revert(&pci_bios_io_region, io_old);
285 pci_config_writeb(bdf, PCI_IO_BASE, io_base >> PCI_IO_SHIFT);
286 pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
287 pci_config_writeb(bdf, PCI_IO_LIMIT, (io_end - 1) >> PCI_IO_SHIFT);
288 pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
290 u32 mem_end = pci_region_align(&pci_bios_mem_region, PCI_MEMORY_ALIGN);
292 pci_region_revert(&pci_bios_mem_region, mem_old);
293 mem_base = 0xffffffff;
296 pci_config_writew(bdf, PCI_MEMORY_BASE, mem_base >> PCI_MEMORY_SHIFT);
297 pci_config_writew(bdf, PCI_MEMORY_LIMIT, (mem_end -1) >> PCI_MEMORY_SHIFT);
299 u32 prefmem_end = pci_region_align(&pci_bios_prefmem_region,
300 PCI_PREF_MEMORY_ALIGN);
301 if (prefmem_end == 0) {
302 pci_region_revert(&pci_bios_prefmem_region, prefmem_old);
303 prefmem_base = 0xffffffff;
306 pci_config_writew(bdf, PCI_PREF_MEMORY_BASE,
307 prefmem_base >> PCI_PREF_MEMORY_SHIFT);
308 pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT,
309 (prefmem_end - 1) >> PCI_PREF_MEMORY_SHIFT);
310 pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, 0);
311 pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, 0);
313 dprintf(1, "PCI: br io = [0x%x, 0x%x)\n", io_base, io_end);
314 dprintf(1, "PCI: br mem = [0x%x, 0x%x)\n", mem_base, mem_end);
315 dprintf(1, "PCI: br pref = [0x%x, 0x%x)\n", prefmem_base, prefmem_end);
317 u16 cmd = pci_config_readw(bdf, PCI_COMMAND);
318 cmd &= ~PCI_COMMAND_IO;
319 if (io_end > io_base) {
320 cmd |= PCI_COMMAND_IO;
322 cmd &= ~PCI_COMMAND_MEMORY;
323 if (mem_end > mem_base || prefmem_end > prefmem_base) {
324 cmd |= PCI_COMMAND_MEMORY;
326 cmd |= PCI_COMMAND_MASTER;
327 pci_config_writew(bdf, PCI_COMMAND, cmd);
329 pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0, PCI_BRIDGE_CTL_SERR);
333 static void storage_ide_init(struct pci_device *pci, void *arg)
336 /* IDE: we map it as in ISA mode */
337 pci_set_io_region_addr(bdf, 0, PORT_ATA1_CMD_BASE);
338 pci_set_io_region_addr(bdf, 1, PORT_ATA1_CTRL_BASE);
339 pci_set_io_region_addr(bdf, 2, PORT_ATA2_CMD_BASE);
340 pci_set_io_region_addr(bdf, 3, PORT_ATA2_CTRL_BASE);
343 /* PIIX3/PIIX4 IDE */
344 static void piix_ide_init(struct pci_device *pci, void *arg)
347 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
348 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
349 pci_bios_allocate_regions(pci, NULL);
352 static void pic_ibm_init(struct pci_device *pci, void *arg)
354 /* PIC, IBM, MPIC & MPIC2 */
355 pci_set_io_region_addr(pci->bdf, 0, 0x80800000 + 0x00040000);
358 static void apple_macio_init(struct pci_device *pci, void *arg)
361 pci_set_io_region_addr(pci->bdf, 0, 0x80800000);
364 static const struct pci_device_id pci_class_tbl[] = {
366 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
367 PCI_CLASS_STORAGE_IDE, piix_ide_init),
368 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
369 PCI_CLASS_STORAGE_IDE, piix_ide_init),
370 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
373 /* PIC, IBM, MIPC & MPIC2 */
374 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
376 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
380 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_init),
381 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_init),
385 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
386 pci_bios_init_device_bridge),
390 PCI_DEVICE(PCI_ANY_ID, PCI_ANY_ID, pci_bios_allocate_regions),
395 /* PIIX4 Power Management device (for ACPI) */
396 static void piix4_pm_init(struct pci_device *pci, void *arg)
399 // acpi sci is hardwired to 9
400 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
402 pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
403 pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
404 pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
405 pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
408 static const struct pci_device_id pci_device_tbl[] = {
409 /* PIIX4 Power Management device (for ACPI) */
410 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
416 static void pci_bios_init_device(struct pci_device *pci)
421 dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n"
422 , pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf)
423 , pci->vendor, pci->device);
424 pci_init_device(pci_class_tbl, pci, NULL);
426 /* enable memory mappings */
427 pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
429 /* map the interrupt */
430 pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
432 pin = pci_slot_get_pirq(bdf, pin - 1);
433 pic_irq = pci_irqs[pin];
434 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pic_irq);
437 pci_init_device(pci_device_tbl, pci, NULL);
440 static void pci_bios_init_device_in_bus(int bus)
442 struct pci_device *pci;
444 u8 pci_bus = pci_bdf_to_bus(pci->bdf);
449 pci_bios_init_device(pci);
454 pci_bios_init_bus_rec(int bus, u8 *pci_bus)
459 dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus);
461 /* prevent accidental access to unintended devices */
462 foreachbdf(bdf, bus) {
463 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
464 if (class == PCI_CLASS_BRIDGE_PCI) {
465 pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255);
466 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0);
470 foreachbdf(bdf, bus) {
471 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
472 if (class != PCI_CLASS_BRIDGE_PCI) {
475 dprintf(1, "PCI: %s bdf = 0x%x\n", __func__, bdf);
477 u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS);
479 dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus);
480 pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus);
482 dprintf(1, "PCI: primary bus = 0x%x\n", pribus);
485 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
487 if (*pci_bus != secbus) {
488 dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n",
491 pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus);
493 dprintf(1, "PCI: secondary bus = 0x%x\n", secbus);
496 /* set to max for access to all subordinate buses.
497 later set it to accurate value */
498 u8 subbus = pci_config_readb(bdf, PCI_SUBORDINATE_BUS);
499 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255);
501 pci_bios_init_bus_rec(secbus, pci_bus);
503 if (subbus != *pci_bus) {
504 dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n",
508 dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus);
510 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus);
515 pci_bios_init_bus(void)
518 pci_bios_init_bus_rec(0 /* host bus */, &pci_bus);
519 busses_count = pci_bus + 1;
522 static void pci_bios_bus_get_bar(struct pci_bus *bus, int bdf, int bar,
525 u32 ofs = pci_bar(bdf, bar);
526 u32 old = pci_config_readl(bdf, ofs);
529 if (bar == PCI_ROM_SLOT) {
530 mask = PCI_ROM_ADDRESS_MASK;
531 pci_config_writel(bdf, ofs, mask);
533 if (old & PCI_BASE_ADDRESS_SPACE_IO)
534 mask = PCI_BASE_ADDRESS_IO_MASK;
536 mask = PCI_BASE_ADDRESS_MEM_MASK;
537 pci_config_writel(bdf, ofs, ~0);
539 *val = pci_config_readl(bdf, ofs);
540 pci_config_writel(bdf, ofs, old);
541 *size = (~(*val & mask)) + 1;
544 static void pci_bios_bus_reserve(struct pci_bus *bus, int type, u32 size)
548 index = pci_size_to_index(size, type);
549 size = pci_index_to_size(index, type);
550 bus->r[type].count[index]++;
551 bus->r[type].sum += size;
552 if (bus->r[type].max < size)
553 bus->r[type].max = size;
556 static u32 pci_bios_bus_get_addr(struct pci_bus *bus, int type, u32 size)
560 index = pci_size_to_index(size, type);
561 addr = bus->r[type].bases[index];
562 bus->r[type].bases[index] += pci_index_to_size(index, type);
566 static void pci_bios_check_device(struct pci_bus *bus, struct pci_device *dev)
572 if (dev->class == PCI_CLASS_BRIDGE_PCI) {
573 if (dev->secondary_bus >= busses_count) {
574 /* should never trigger */
575 dprintf(1, "PCI: bus count too small (%d), skipping bus #%d\n",
576 busses_count, dev->secondary_bus);
579 struct pci_bus *s = busses + dev->secondary_bus;
580 pci_bios_check_device_in_bus(dev->secondary_bus);
581 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
582 limit = (type == PCI_REGION_TYPE_IO) ?
583 PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN;
584 s->r[type].size = s->r[type].sum;
585 if (s->r[type].size < limit)
586 s->r[type].size = limit;
587 s->r[type].size = pci_size_roundup(s->r[type].size);
588 pci_bios_bus_reserve(bus, type, s->r[type].size);
590 dprintf(1, "PCI: secondary bus %d sizes: io %x, mem %x, prefmem %x\n",
592 s->r[PCI_REGION_TYPE_IO].size,
593 s->r[PCI_REGION_TYPE_MEM].size,
594 s->r[PCI_REGION_TYPE_PREFMEM].size);
598 for (i = 0; i < PCI_NUM_REGIONS; i++) {
600 pci_bios_bus_get_bar(bus, bdf, i, &val, &size);
604 pci_bios_bus_reserve(bus, pci_addr_to_type(val), size);
605 dev->bars[i].addr = val;
606 dev->bars[i].size = size;
607 dev->bars[i].is64 = (!(val & PCI_BASE_ADDRESS_SPACE_IO) &&
608 (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64);
610 if (dev->bars[i].is64) {
616 static void pci_bios_map_device(struct pci_bus *bus, struct pci_device *dev)
621 if (dev->class == PCI_CLASS_BRIDGE_PCI) {
622 if (dev->secondary_bus >= busses_count) {
625 struct pci_bus *s = busses + dev->secondary_bus;
628 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
629 s->r[type].base = pci_bios_bus_get_addr(bus, type, s->r[type].size);
631 dprintf(1, "PCI: init bases bus %d (secondary)\n", dev->secondary_bus);
632 pci_bios_init_bus_bases(s);
634 base = s->r[PCI_REGION_TYPE_IO].base;
635 limit = base + s->r[PCI_REGION_TYPE_IO].size - 1;
636 pci_config_writeb(bdf, PCI_IO_BASE, base >> PCI_IO_SHIFT);
637 pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
638 pci_config_writeb(bdf, PCI_IO_LIMIT, limit >> PCI_IO_SHIFT);
639 pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
641 base = s->r[PCI_REGION_TYPE_MEM].base;
642 limit = base + s->r[PCI_REGION_TYPE_MEM].size - 1;
643 pci_config_writew(bdf, PCI_MEMORY_BASE, base >> PCI_MEMORY_SHIFT);
644 pci_config_writew(bdf, PCI_MEMORY_LIMIT, limit >> PCI_MEMORY_SHIFT);
646 base = s->r[PCI_REGION_TYPE_PREFMEM].base;
647 limit = base + s->r[PCI_REGION_TYPE_PREFMEM].size - 1;
648 pci_config_writew(bdf, PCI_PREF_MEMORY_BASE, base >> PCI_PREF_MEMORY_SHIFT);
649 pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT, limit >> PCI_PREF_MEMORY_SHIFT);
650 pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, 0);
651 pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, 0);
653 pci_bios_map_device_in_bus(dev->secondary_bus);
657 for (i = 0; i < PCI_NUM_REGIONS; i++) {
659 if (dev->bars[i].addr == 0) {
663 addr = pci_bios_bus_get_addr(bus, pci_addr_to_type(dev->bars[i].addr),
665 dprintf(1, " bar %d, addr %x, size %x [%s]\n",
666 i, addr, dev->bars[i].size,
667 dev->bars[i].addr & PCI_BASE_ADDRESS_SPACE_IO ? "io" : "mem");
668 pci_set_io_region_addr(bdf, i, addr);
670 if (dev->bars[i].is64) {
676 static void pci_bios_check_device_in_bus(int bus)
678 struct pci_device *pci;
680 dprintf(1, "PCI: check devices bus %d\n", bus);
682 if (pci_bdf_to_bus(pci->bdf) != bus)
684 pci_bios_check_device(&busses[bus], pci);
688 static void pci_bios_map_device_in_bus(int bus)
690 struct pci_device *pci;
693 if (pci_bdf_to_bus(pci->bdf) != bus)
695 dprintf(1, "PCI: map device bus %d, bfd 0x%x\n", bus, pci->bdf);
696 pci_bios_map_device(&busses[bus], pci);
700 static void pci_bios_init_bus_bases(struct pci_bus *bus)
702 u32 base, newbase, size;
705 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
706 dprintf(1, " type %s max %x sum %x base %x\n", region_type_name[type],
707 bus->r[type].max, bus->r[type].sum, bus->r[type].base);
708 base = bus->r[type].base;
709 for (i = ARRAY_SIZE(bus->r[type].count)-1; i >= 0; i--) {
710 size = pci_index_to_size(i, type);
711 if (!bus->r[type].count[i])
713 newbase = base + size * bus->r[type].count[i];
714 dprintf(1, " size %8x: %d bar(s), %8x -> %8x\n",
715 size, bus->r[type].count[i], base, newbase - 1);
716 bus->r[type].bases[i] = base;
722 #define ROOT_BASE(top, sum, align) ALIGN_DOWN((top)-(sum),(align))
724 static int pci_bios_init_root_regions(u32 start, u32 end)
726 struct pci_bus *bus = &busses[0];
728 bus->r[PCI_REGION_TYPE_IO].base = 0xc000;
730 if (bus->r[PCI_REGION_TYPE_MEM].sum < bus->r[PCI_REGION_TYPE_PREFMEM].sum) {
731 bus->r[PCI_REGION_TYPE_MEM].base =
733 bus->r[PCI_REGION_TYPE_MEM].sum,
734 bus->r[PCI_REGION_TYPE_MEM].max);
735 bus->r[PCI_REGION_TYPE_PREFMEM].base =
736 ROOT_BASE(bus->r[PCI_REGION_TYPE_MEM].base,
737 bus->r[PCI_REGION_TYPE_PREFMEM].sum,
738 bus->r[PCI_REGION_TYPE_PREFMEM].max);
739 if (bus->r[PCI_REGION_TYPE_PREFMEM].base >= start) {
743 bus->r[PCI_REGION_TYPE_PREFMEM].base =
745 bus->r[PCI_REGION_TYPE_PREFMEM].sum,
746 bus->r[PCI_REGION_TYPE_PREFMEM].max);
747 bus->r[PCI_REGION_TYPE_MEM].base =
748 ROOT_BASE(bus->r[PCI_REGION_TYPE_PREFMEM].base,
749 bus->r[PCI_REGION_TYPE_MEM].sum,
750 bus->r[PCI_REGION_TYPE_MEM].max);
751 if (bus->r[PCI_REGION_TYPE_MEM].base >= start) {
761 if (CONFIG_COREBOOT || usingXen()) {
762 // PCI setup already done by coreboot or Xen - just do probe.
767 dprintf(3, "pci setup\n");
769 u32 start = BUILD_PCIMEM_START;
770 u32 end = BUILD_IOAPIC_ADDR;
772 pci_region_init(&pci_bios_io_region, 0xc000, 64 * 1024 - 1);
773 pci_region_init(&pci_bios_mem_region,
774 BUILD_PCIMEM_START, BUILD_PCIMEM_END - 1);
775 pci_region_init(&pci_bios_prefmem_region,
776 BUILD_PCIPREFMEM_START, BUILD_PCIPREFMEM_END - 1);
778 dprintf(1, "=== PCI bus & bridge init ===\n");
781 dprintf(1, "=== PCI device probing ===\n");
784 dprintf(1, "=== PCI new allocation pass #1 ===\n");
785 busses = malloc_tmp(sizeof(*busses) * busses_count);
786 memset(busses, 0, sizeof(*busses) * busses_count);
787 pci_bios_check_device_in_bus(0 /* host bus */);
788 if (pci_bios_init_root_regions(start, end) != 0) {
789 panic("PCI: out of address space\n");
792 dprintf(1, "=== PCI new allocation pass #2 ===\n");
793 dprintf(1, "PCI: init bases bus 0 (primary)\n");
794 pci_bios_init_bus_bases(&busses[0]);
795 pci_bios_map_device_in_bus(0 /* host bus */);
798 dprintf(1, "=== PCI old allocation pass ===\n");
799 struct pci_device *pci;
801 pci_init_device(pci_isa_bridge_tbl, pci, NULL);
805 pci_bios_init_device_in_bus(0 /* host bus */);