1 // Initialize PCI devices (on emulators)
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "util.h" // dprintf
9 #include "pci.h" // pci_config_readl
10 #include "biosvar.h" // GET_EBDA
11 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12 #include "pci_regs.h" // PCI_COMMAND
13 #include "xen.h" // usingXen
15 #define PCI_IO_INDEX_SHIFT 2
16 #define PCI_MEM_INDEX_SHIFT 12
18 #define PCI_BRIDGE_IO_MIN 0x1000
19 #define PCI_BRIDGE_MEM_MIN 0x100000
21 static struct pci_region pci_bios_io_region;
22 static struct pci_region pci_bios_mem_region;
23 static struct pci_region pci_bios_prefmem_region;
25 enum pci_region_type {
28 PCI_REGION_TYPE_PREFMEM,
29 PCI_REGION_TYPE_COUNT,
32 static const char *region_type_name[] = {
33 [ PCI_REGION_TYPE_IO ] = "io",
34 [ PCI_REGION_TYPE_MEM ] = "mem",
35 [ PCI_REGION_TYPE_PREFMEM ] = "prefmem",
38 static struct pci_bus {
40 /* pci region stats */
41 u32 count[32 - PCI_MEM_INDEX_SHIFT];
43 /* seconday bus region sizes */
45 /* pci region assignments */
46 u32 bases[32 - PCI_MEM_INDEX_SHIFT];
48 } r[PCI_REGION_TYPE_COUNT];
50 static int busses_count;
52 static void pci_bios_init_device_in_bus(int bus);
53 static void pci_bios_check_device_in_bus(int bus);
54 static void pci_bios_init_bus_bases(struct pci_bus *bus);
55 static void pci_bios_map_device_in_bus(int bus);
57 static int pci_size_to_index(u32 size, enum pci_region_type type)
59 int index = __fls(size);
60 int shift = (type == PCI_REGION_TYPE_IO) ?
61 PCI_IO_INDEX_SHIFT : PCI_MEM_INDEX_SHIFT;
69 static u32 pci_index_to_size(int index, enum pci_region_type type)
71 int shift = (type == PCI_REGION_TYPE_IO) ?
72 PCI_IO_INDEX_SHIFT : PCI_MEM_INDEX_SHIFT;
74 return 0x1 << (index + shift);
77 static enum pci_region_type pci_addr_to_type(u32 addr)
79 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
80 return PCI_REGION_TYPE_IO;
81 if (addr & PCI_BASE_ADDRESS_MEM_PREFETCH)
82 return PCI_REGION_TYPE_PREFMEM;
83 return PCI_REGION_TYPE_MEM;
86 static u32 pci_size_roundup(u32 size)
88 int index = __fls(size-1)+1;
92 /* host irqs corresponding to PCI irqs A-D */
93 const u8 pci_irqs[4] = {
97 static u32 pci_bar(u16 bdf, int region_num)
99 if (region_num != PCI_ROM_SLOT) {
100 return PCI_BASE_ADDRESS_0 + region_num * 4;
103 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
104 u8 type = pci_config_readb(bdf, PCI_HEADER_TYPE);
105 type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
106 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
109 static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
113 ofs = pci_bar(bdf, region_num);
115 pci_config_writel(bdf, ofs, addr);
116 dprintf(1, "region %d: 0x%08x\n", region_num, addr);
124 static int pci_bios_allocate_region(u16 bdf, int region_num)
126 struct pci_region *r;
127 u32 ofs = pci_bar(bdf, region_num);
129 u32 old = pci_config_readl(bdf, ofs);
131 if (region_num == PCI_ROM_SLOT) {
132 mask = PCI_ROM_ADDRESS_MASK;
133 pci_config_writel(bdf, ofs, mask);
135 if (old & PCI_BASE_ADDRESS_SPACE_IO)
136 mask = PCI_BASE_ADDRESS_IO_MASK;
138 mask = PCI_BASE_ADDRESS_MEM_MASK;
139 pci_config_writel(bdf, ofs, ~0);
141 u32 val = pci_config_readl(bdf, ofs);
142 pci_config_writel(bdf, ofs, old);
144 u32 size = (~(val & mask)) + 1;
148 if (val & PCI_BASE_ADDRESS_SPACE_IO) {
149 r = &pci_bios_io_region;
152 } else if ((val & PCI_BASE_ADDRESS_MEM_PREFETCH) &&
153 /* keep behaviour on bus = 0 */
154 pci_bdf_to_bus(bdf) != 0 &&
155 /* If pci_bios_prefmem_addr == 0, keep old behaviour */
156 pci_region_addr(&pci_bios_prefmem_region) != 0) {
157 r = &pci_bios_prefmem_region;
159 msg = "decrease BUILD_PCIMEM_SIZE and recompile. size %x";
161 r = &pci_bios_mem_region;
163 msg = "increase BUILD_PCIMEM_SIZE and recompile.";
165 u32 addr = pci_region_alloc(r, size);
167 pci_set_io_region_addr(bdf, region_num, addr);
171 "%s region of (bdf 0x%x bar %d) can't be mapped. "
173 type, bdf, region_num, msg, pci_region_size(r));
177 int is_64bit = !(val & PCI_BASE_ADDRESS_SPACE_IO) &&
178 (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64;
179 if (is_64bit && size > 0) {
180 pci_config_writel(bdf, ofs + 4, 0);
185 static void pci_bios_allocate_regions(struct pci_device *pci, void *arg)
188 for (i = 0; i < PCI_NUM_REGIONS; i++) {
189 int is_64bit = pci_bios_allocate_region(pci->bdf, i);
196 /* return the global irq number corresponding to a given device irq
197 pin. We could also use the bus number to have a more precise
199 static int pci_slot_get_pirq(u16 bdf, int irq_num)
201 int slot_addend = pci_bdf_to_dev(bdf) - 1;
202 return (irq_num + slot_addend) & 3;
205 /* PIIX3/PIIX4 PCI to ISA bridge */
206 static void piix_isa_bridge_init(struct pci_device *pci, void *arg)
213 for (i = 0; i < 4; i++) {
215 /* set to trigger level */
216 elcr[irq >> 3] |= (1 << (irq & 7));
217 /* activate irq remapping in PIIX */
218 pci_config_writeb(pci->bdf, 0x60 + i, irq);
220 outb(elcr[0], 0x4d0);
221 outb(elcr[1], 0x4d1);
222 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
225 static const struct pci_device_id pci_isa_bridge_tbl[] = {
226 /* PIIX3/PIIX4 PCI to ISA bridge */
227 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
228 piix_isa_bridge_init),
229 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
230 piix_isa_bridge_init),
235 #define PCI_IO_ALIGN 4096
236 #define PCI_IO_SHIFT 8
237 #define PCI_MEMORY_ALIGN (1UL << 20)
238 #define PCI_MEMORY_SHIFT 16
239 #define PCI_PREF_MEMORY_ALIGN (1UL << 20)
240 #define PCI_PREF_MEMORY_SHIFT 16
242 static void pci_bios_init_device_bridge(struct pci_device *pci, void *arg)
245 pci_bios_allocate_region(bdf, 0);
246 pci_bios_allocate_region(bdf, 1);
247 pci_bios_allocate_region(bdf, PCI_ROM_SLOT);
249 u32 io_old = pci_region_addr(&pci_bios_io_region);
250 u32 mem_old = pci_region_addr(&pci_bios_mem_region);
251 u32 prefmem_old = pci_region_addr(&pci_bios_prefmem_region);
253 /* IO BASE is assumed to be 16 bit */
254 if (pci_region_align(&pci_bios_io_region, PCI_IO_ALIGN) == 0) {
255 pci_region_disable(&pci_bios_io_region);
257 if (pci_region_align(&pci_bios_mem_region, PCI_MEMORY_ALIGN) == 0) {
258 pci_region_disable(&pci_bios_mem_region);
260 if (pci_region_align(&pci_bios_prefmem_region,
261 PCI_PREF_MEMORY_ALIGN) == 0) {
262 pci_region_disable(&pci_bios_prefmem_region);
265 u32 io_base = pci_region_addr(&pci_bios_io_region);
266 u32 mem_base = pci_region_addr(&pci_bios_mem_region);
267 u32 prefmem_base = pci_region_addr(&pci_bios_prefmem_region);
269 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
271 pci_bios_init_device_in_bus(secbus);
274 u32 io_end = pci_region_align(&pci_bios_io_region, PCI_IO_ALIGN);
276 pci_region_revert(&pci_bios_io_region, io_old);
280 pci_config_writeb(bdf, PCI_IO_BASE, io_base >> PCI_IO_SHIFT);
281 pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
282 pci_config_writeb(bdf, PCI_IO_LIMIT, (io_end - 1) >> PCI_IO_SHIFT);
283 pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
285 u32 mem_end = pci_region_align(&pci_bios_mem_region, PCI_MEMORY_ALIGN);
287 pci_region_revert(&pci_bios_mem_region, mem_old);
288 mem_base = 0xffffffff;
291 pci_config_writew(bdf, PCI_MEMORY_BASE, mem_base >> PCI_MEMORY_SHIFT);
292 pci_config_writew(bdf, PCI_MEMORY_LIMIT, (mem_end -1) >> PCI_MEMORY_SHIFT);
294 u32 prefmem_end = pci_region_align(&pci_bios_prefmem_region,
295 PCI_PREF_MEMORY_ALIGN);
296 if (prefmem_end == 0) {
297 pci_region_revert(&pci_bios_prefmem_region, prefmem_old);
298 prefmem_base = 0xffffffff;
301 pci_config_writew(bdf, PCI_PREF_MEMORY_BASE,
302 prefmem_base >> PCI_PREF_MEMORY_SHIFT);
303 pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT,
304 (prefmem_end - 1) >> PCI_PREF_MEMORY_SHIFT);
305 pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, 0);
306 pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, 0);
308 dprintf(1, "PCI: br io = [0x%x, 0x%x)\n", io_base, io_end);
309 dprintf(1, "PCI: br mem = [0x%x, 0x%x)\n", mem_base, mem_end);
310 dprintf(1, "PCI: br pref = [0x%x, 0x%x)\n", prefmem_base, prefmem_end);
312 u16 cmd = pci_config_readw(bdf, PCI_COMMAND);
313 cmd &= ~PCI_COMMAND_IO;
314 if (io_end > io_base) {
315 cmd |= PCI_COMMAND_IO;
317 cmd &= ~PCI_COMMAND_MEMORY;
318 if (mem_end > mem_base || prefmem_end > prefmem_base) {
319 cmd |= PCI_COMMAND_MEMORY;
321 cmd |= PCI_COMMAND_MASTER;
322 pci_config_writew(bdf, PCI_COMMAND, cmd);
324 pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0, PCI_BRIDGE_CTL_SERR);
327 static void storage_ide_init(struct pci_device *pci, void *arg)
330 /* IDE: we map it as in ISA mode */
331 pci_set_io_region_addr(bdf, 0, PORT_ATA1_CMD_BASE);
332 pci_set_io_region_addr(bdf, 1, PORT_ATA1_CTRL_BASE);
333 pci_set_io_region_addr(bdf, 2, PORT_ATA2_CMD_BASE);
334 pci_set_io_region_addr(bdf, 3, PORT_ATA2_CTRL_BASE);
337 /* PIIX3/PIIX4 IDE */
338 static void piix_ide_init(struct pci_device *pci, void *arg)
341 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
342 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
343 pci_bios_allocate_regions(pci, NULL);
346 static void pic_ibm_init(struct pci_device *pci, void *arg)
348 /* PIC, IBM, MPIC & MPIC2 */
349 pci_set_io_region_addr(pci->bdf, 0, 0x80800000 + 0x00040000);
352 static void apple_macio_init(struct pci_device *pci, void *arg)
355 pci_set_io_region_addr(pci->bdf, 0, 0x80800000);
358 static const struct pci_device_id pci_class_tbl[] = {
360 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
361 PCI_CLASS_STORAGE_IDE, piix_ide_init),
362 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
363 PCI_CLASS_STORAGE_IDE, piix_ide_init),
364 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
367 /* PIC, IBM, MIPC & MPIC2 */
368 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
370 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
374 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_init),
375 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_init),
378 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
379 pci_bios_init_device_bridge),
382 PCI_DEVICE(PCI_ANY_ID, PCI_ANY_ID, pci_bios_allocate_regions),
387 /* PIIX4 Power Management device (for ACPI) */
388 static void piix4_pm_init(struct pci_device *pci, void *arg)
391 // acpi sci is hardwired to 9
392 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
394 pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
395 pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
396 pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
397 pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
400 static const struct pci_device_id pci_device_tbl[] = {
401 /* PIIX4 Power Management device (for ACPI) */
402 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
408 static void pci_bios_init_device(struct pci_device *pci)
413 dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n"
414 , pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf)
415 , pci->vendor, pci->device);
416 pci_init_device(pci_class_tbl, pci, NULL);
418 /* enable memory mappings */
419 pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
421 /* map the interrupt */
422 pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
424 pin = pci_slot_get_pirq(bdf, pin - 1);
425 pic_irq = pci_irqs[pin];
426 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pic_irq);
429 pci_init_device(pci_device_tbl, pci, NULL);
432 static void pci_bios_init_device_in_bus(int bus)
434 struct pci_device *pci;
436 u8 pci_bus = pci_bdf_to_bus(pci->bdf);
441 pci_bios_init_device(pci);
446 pci_bios_init_bus_rec(int bus, u8 *pci_bus)
451 dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus);
453 /* prevent accidental access to unintended devices */
454 foreachbdf(bdf, bus) {
455 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
456 if (class == PCI_CLASS_BRIDGE_PCI) {
457 pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255);
458 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0);
462 foreachbdf(bdf, bus) {
463 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
464 if (class != PCI_CLASS_BRIDGE_PCI) {
467 dprintf(1, "PCI: %s bdf = 0x%x\n", __func__, bdf);
469 u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS);
471 dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus);
472 pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus);
474 dprintf(1, "PCI: primary bus = 0x%x\n", pribus);
477 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
479 if (*pci_bus != secbus) {
480 dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n",
483 pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus);
485 dprintf(1, "PCI: secondary bus = 0x%x\n", secbus);
488 /* set to max for access to all subordinate buses.
489 later set it to accurate value */
490 u8 subbus = pci_config_readb(bdf, PCI_SUBORDINATE_BUS);
491 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255);
493 pci_bios_init_bus_rec(secbus, pci_bus);
495 if (subbus != *pci_bus) {
496 dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n",
500 dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus);
502 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus);
507 pci_bios_init_bus(void)
510 pci_bios_init_bus_rec(0 /* host bus */, &pci_bus);
511 busses_count = pci_bus + 1;
514 static void pci_bios_bus_get_bar(struct pci_bus *bus, int bdf, int bar,
517 u32 ofs = pci_bar(bdf, bar);
518 u32 old = pci_config_readl(bdf, ofs);
521 if (bar == PCI_ROM_SLOT) {
522 mask = PCI_ROM_ADDRESS_MASK;
523 pci_config_writel(bdf, ofs, mask);
525 if (old & PCI_BASE_ADDRESS_SPACE_IO)
526 mask = PCI_BASE_ADDRESS_IO_MASK;
528 mask = PCI_BASE_ADDRESS_MEM_MASK;
529 pci_config_writel(bdf, ofs, ~0);
531 *val = pci_config_readl(bdf, ofs);
532 pci_config_writel(bdf, ofs, old);
533 *size = (~(*val & mask)) + 1;
536 static void pci_bios_bus_reserve(struct pci_bus *bus, int type, u32 size)
540 index = pci_size_to_index(size, type);
541 size = pci_index_to_size(index, type);
542 bus->r[type].count[index]++;
543 bus->r[type].sum += size;
544 if (bus->r[type].max < size)
545 bus->r[type].max = size;
548 static u32 pci_bios_bus_get_addr(struct pci_bus *bus, int type, u32 size)
552 index = pci_size_to_index(size, type);
553 addr = bus->r[type].bases[index];
554 bus->r[type].bases[index] += pci_index_to_size(index, type);
558 static void pci_bios_check_device(struct pci_bus *bus, struct pci_device *dev)
564 if (dev->class == PCI_CLASS_BRIDGE_PCI) {
565 if (dev->secondary_bus >= busses_count) {
566 /* should never trigger */
567 dprintf(1, "PCI: bus count too small (%d), skipping bus #%d\n",
568 busses_count, dev->secondary_bus);
571 struct pci_bus *s = busses + dev->secondary_bus;
572 pci_bios_check_device_in_bus(dev->secondary_bus);
573 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
574 limit = (type == PCI_REGION_TYPE_IO) ?
575 PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN;
576 s->r[type].size = s->r[type].sum;
577 if (s->r[type].size < limit)
578 s->r[type].size = limit;
579 s->r[type].size = pci_size_roundup(s->r[type].size);
580 pci_bios_bus_reserve(bus, type, s->r[type].size);
582 dprintf(1, "PCI: secondary bus %d sizes: io %x, mem %x, prefmem %x\n",
584 s->r[PCI_REGION_TYPE_IO].size,
585 s->r[PCI_REGION_TYPE_MEM].size,
586 s->r[PCI_REGION_TYPE_PREFMEM].size);
590 for (i = 0; i < PCI_NUM_REGIONS; i++) {
592 pci_bios_bus_get_bar(bus, bdf, i, &val, &size);
596 pci_bios_bus_reserve(bus, pci_addr_to_type(val), size);
597 dev->bars[i].addr = val;
598 dev->bars[i].size = size;
599 dev->bars[i].is64 = (!(val & PCI_BASE_ADDRESS_SPACE_IO) &&
600 (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64);
602 if (dev->bars[i].is64) {
608 static void pci_bios_map_device(struct pci_bus *bus, struct pci_device *dev)
612 if (dev->class == PCI_CLASS_BRIDGE_PCI) {
613 if (dev->secondary_bus >= busses_count) {
616 struct pci_bus *s = busses + dev->secondary_bus;
618 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
619 s->r[type].base = pci_bios_bus_get_addr(bus, type, s->r[type].size);
621 dprintf(1, "PCI: init bases bus %d (secondary)\n", dev->secondary_bus);
622 pci_bios_init_bus_bases(s);
623 /* TODO: commit assignments */
625 pci_bios_map_device_in_bus(dev->secondary_bus);
629 for (i = 0; i < PCI_NUM_REGIONS; i++) {
631 if (dev->bars[i].addr == 0) {
635 addr = pci_bios_bus_get_addr(bus, pci_addr_to_type(dev->bars[i].addr),
637 dprintf(1, " bar %d, addr %x, size %x [%s]\n",
638 i, addr, dev->bars[i].size,
639 dev->bars[i].addr & PCI_BASE_ADDRESS_SPACE_IO ? "io" : "mem");
640 /* TODO: commit assignments */
642 if (dev->bars[i].is64) {
648 static void pci_bios_check_device_in_bus(int bus)
650 struct pci_device *pci;
652 dprintf(1, "PCI: check devices bus %d\n", bus);
654 if (pci_bdf_to_bus(pci->bdf) != bus)
656 pci_bios_check_device(&busses[bus], pci);
660 static void pci_bios_map_device_in_bus(int bus)
662 struct pci_device *pci;
665 if (pci_bdf_to_bus(pci->bdf) != bus)
667 dprintf(1, "PCI: map device bus %d, bfd 0x%x\n", bus, pci->bdf);
668 pci_bios_map_device(&busses[bus], pci);
672 static void pci_bios_init_bus_bases(struct pci_bus *bus)
674 u32 base, newbase, size;
677 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
678 dprintf(1, " type %s max %x sum %x base %x\n", region_type_name[type],
679 bus->r[type].max, bus->r[type].sum, bus->r[type].base);
680 base = bus->r[type].base;
681 for (i = ARRAY_SIZE(bus->r[type].count)-1; i >= 0; i--) {
682 size = pci_index_to_size(i, type);
683 if (!bus->r[type].count[i])
685 newbase = base + size * bus->r[type].count[i];
686 dprintf(1, " size %8x: %d bar(s), %8x -> %8x\n",
687 size, bus->r[type].count[i], base, newbase - 1);
688 bus->r[type].bases[i] = base;
694 #define ROOT_BASE(top, sum, align) ALIGN_DOWN((top)-(sum),(align))
696 static int pci_bios_init_root_regions(u32 start, u32 end)
698 struct pci_bus *bus = &busses[0];
700 bus->r[PCI_REGION_TYPE_IO].base = 0xc000;
702 if (bus->r[PCI_REGION_TYPE_MEM].sum < bus->r[PCI_REGION_TYPE_PREFMEM].sum) {
703 bus->r[PCI_REGION_TYPE_MEM].base =
705 bus->r[PCI_REGION_TYPE_MEM].sum,
706 bus->r[PCI_REGION_TYPE_MEM].max);
707 bus->r[PCI_REGION_TYPE_PREFMEM].base =
708 ROOT_BASE(bus->r[PCI_REGION_TYPE_MEM].base,
709 bus->r[PCI_REGION_TYPE_PREFMEM].sum,
710 bus->r[PCI_REGION_TYPE_PREFMEM].max);
711 if (bus->r[PCI_REGION_TYPE_PREFMEM].base >= start) {
715 bus->r[PCI_REGION_TYPE_PREFMEM].base =
717 bus->r[PCI_REGION_TYPE_PREFMEM].sum,
718 bus->r[PCI_REGION_TYPE_PREFMEM].max);
719 bus->r[PCI_REGION_TYPE_MEM].base =
720 ROOT_BASE(bus->r[PCI_REGION_TYPE_PREFMEM].base,
721 bus->r[PCI_REGION_TYPE_MEM].sum,
722 bus->r[PCI_REGION_TYPE_MEM].max);
723 if (bus->r[PCI_REGION_TYPE_MEM].base >= start) {
733 if (CONFIG_COREBOOT || usingXen()) {
734 // PCI setup already done by coreboot or Xen - just do probe.
739 dprintf(3, "pci setup\n");
741 u32 start = BUILD_PCIMEM_START;
742 u32 end = BUILD_IOAPIC_ADDR;
744 pci_region_init(&pci_bios_io_region, 0xc000, 64 * 1024 - 1);
745 pci_region_init(&pci_bios_mem_region,
746 BUILD_PCIMEM_START, BUILD_PCIMEM_END - 1);
747 pci_region_init(&pci_bios_prefmem_region,
748 BUILD_PCIPREFMEM_START, BUILD_PCIPREFMEM_END - 1);
750 dprintf(1, "=== PCI bus & bridge init ===\n");
753 dprintf(1, "=== PCI device probing ===\n");
756 dprintf(1, "=== PCI new allocation pass #1 ===\n");
757 busses = malloc_tmp(sizeof(*busses) * busses_count);
758 memset(busses, 0, sizeof(*busses) * busses_count);
759 pci_bios_check_device_in_bus(0 /* host bus */);
760 if (pci_bios_init_root_regions(start, end) != 0) {
761 dprintf(1, "PCI: out of address space\n");
762 /* Hmm, what do now? */
765 dprintf(1, "=== PCI new allocation pass #2 ===\n");
766 dprintf(1, "PCI: init bases bus 0 (primary)\n");
767 pci_bios_init_bus_bases(&busses[0]);
768 pci_bios_map_device_in_bus(0 /* host bus */);
770 dprintf(1, "=== PCI old allocation pass ===\n");
771 struct pci_device *pci;
773 pci_init_device(pci_isa_bridge_tbl, pci, NULL);
775 pci_bios_init_device_in_bus(0 /* host bus */);