1 // Initialize PCI devices (on emulators)
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "util.h" // dprintf
9 #include "pci.h" // pci_config_readl
10 #include "biosvar.h" // GET_EBDA
11 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12 #include "pci_regs.h" // PCI_COMMAND
14 #define PCI_ROM_SLOT 6
15 #define PCI_NUM_REGIONS 7
17 static u32 pci_bios_io_addr;
18 static u32 pci_bios_mem_addr;
19 static u32 pci_bios_bigmem_addr;
20 /* host irqs corresponding to PCI irqs A-D */
21 static u8 pci_irqs[4] = {
29 static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
34 if (region_num == PCI_ROM_SLOT) {
35 ofs = PCI_ROM_ADDRESS;
37 ofs = PCI_BASE_ADDRESS_0 + region_num * 4;
40 old_addr = pci_config_readl(bdf, ofs);
42 pci_config_writel(bdf, ofs, addr);
43 dprintf(1, "region %d: 0x%08x\n", region_num, addr);
45 /* enable memory mappings */
46 cmd = pci_config_readw(bdf, PCI_COMMAND);
47 if (region_num == PCI_ROM_SLOT)
48 cmd |= PCI_COMMAND_MEMORY;
49 else if (old_addr & PCI_BASE_ADDRESS_SPACE_IO)
50 cmd |= PCI_COMMAND_IO;
52 cmd |= PCI_COMMAND_MEMORY;
53 pci_config_writew(bdf, PCI_COMMAND, cmd);
56 /* return the global irq number corresponding to a given device irq
57 pin. We could also use the bus number to have a more precise
59 static int pci_slot_get_pirq(u16 bdf, int irq_num)
61 int slot_addend = pci_bdf_to_dev(bdf) - 1;
62 return (irq_num + slot_addend) & 3;
65 static void pci_bios_init_bridges(u16 bdf)
67 u16 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
68 u16 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
70 if (vendor_id == PCI_VENDOR_ID_INTEL
71 && (device_id == PCI_DEVICE_ID_INTEL_82371SB_0
72 || device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
76 /* PIIX3/PIIX4 PCI to ISA bridge */
80 for(i = 0; i < 4; i++) {
82 /* set to trigger level */
83 elcr[irq >> 3] |= (1 << (irq & 7));
84 /* activate irq remapping in PIIX */
85 pci_config_writeb(bdf, 0x60 + i, irq);
89 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n",
94 static void pci_bios_init_device(u16 bdf)
98 int i, pin, pic_irq, vendor_id, device_id;
100 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
101 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
102 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
103 dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n"
104 , pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf), vendor_id, device_id);
106 case PCI_CLASS_STORAGE_IDE:
107 if (vendor_id == PCI_VENDOR_ID_INTEL
108 && (device_id == PCI_DEVICE_ID_INTEL_82371SB_1
109 || device_id == PCI_DEVICE_ID_INTEL_82371AB)) {
110 /* PIIX3/PIIX4 IDE */
111 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
112 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
115 /* IDE: we map it as in ISA mode */
116 pci_set_io_region_addr(bdf, 0, 0x1f0);
117 pci_set_io_region_addr(bdf, 1, 0x3f4);
118 pci_set_io_region_addr(bdf, 2, 0x170);
119 pci_set_io_region_addr(bdf, 3, 0x374);
122 case PCI_CLASS_DISPLAY_VGA:
123 if (vendor_id != 0x1234)
125 /* VGA: map frame buffer to default Bochs VBE address */
126 pci_set_io_region_addr(bdf, 0, 0xE0000000);
128 case PCI_CLASS_SYSTEM_PIC:
130 if (vendor_id == PCI_VENDOR_ID_IBM) {
132 if (device_id == 0x0046 || device_id == 0xFFFF) {
134 pci_set_io_region_addr(bdf, 0, 0x80800000 + 0x00040000);
139 if (vendor_id == PCI_VENDOR_ID_APPLE &&
140 (device_id == 0x0017 || device_id == 0x0022)) {
142 pci_set_io_region_addr(bdf, 0, 0x80800000);
147 /* default memory mappings */
148 for (i = 0; i < PCI_NUM_REGIONS; i++) {
152 if (i == PCI_ROM_SLOT)
153 ofs = PCI_ROM_ADDRESS;
155 ofs = PCI_BASE_ADDRESS_0 + i * 4;
156 pci_config_writel(bdf, ofs, 0xffffffff);
157 val = pci_config_readl(bdf, ofs);
159 size = (~(val & ~0xf)) + 1;
160 if (val & PCI_BASE_ADDRESS_SPACE_IO)
161 paddr = &pci_bios_io_addr;
162 else if (size >= 0x04000000)
163 paddr = &pci_bios_bigmem_addr;
165 paddr = &pci_bios_mem_addr;
166 *paddr = ALIGN(*paddr, size);
167 pci_set_io_region_addr(bdf, i, *paddr);
174 /* map the interrupt */
175 pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
177 pin = pci_slot_get_pirq(bdf, pin - 1);
178 pic_irq = pci_irqs[pin];
179 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pic_irq);
182 if (vendor_id == PCI_VENDOR_ID_INTEL
183 && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
184 /* PIIX4 Power Management device (for ACPI) */
187 // acpi sci is hardwired to 9
188 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
190 pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
191 pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
192 pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
193 pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
201 // Already done by coreboot.
204 pci_bios_io_addr = 0xc000;
205 pci_bios_mem_addr = 0xf0000000;
206 pci_bios_bigmem_addr = RamSize;
207 if (pci_bios_bigmem_addr < 0x90000000)
208 pci_bios_bigmem_addr = 0x90000000;
211 foreachpci(bdf, max) {
212 pci_bios_init_bridges(bdf);
214 foreachpci(bdf, max) {
215 pci_bios_init_device(bdf);