1 // Initialize PCI devices (on emulators)
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "util.h" // dprintf
9 #include "pci.h" // pci_config_readl
10 #include "biosvar.h" // GET_EBDA
11 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12 #include "pci_regs.h" // PCI_COMMAND
13 #include "xen.h" // usingXen
15 #define PCI_IO_INDEX_SHIFT 2
16 #define PCI_MEM_INDEX_SHIFT 12
18 #define PCI_BRIDGE_IO_MIN 0x1000
19 #define PCI_BRIDGE_MEM_MIN 0x100000
21 enum pci_region_type {
24 PCI_REGION_TYPE_PREFMEM,
25 PCI_REGION_TYPE_COUNT,
28 static const char *region_type_name[] = {
29 [ PCI_REGION_TYPE_IO ] = "io",
30 [ PCI_REGION_TYPE_MEM ] = "mem",
31 [ PCI_REGION_TYPE_PREFMEM ] = "prefmem",
34 static struct pci_bus {
36 /* pci region stats */
37 u32 count[32 - PCI_MEM_INDEX_SHIFT];
39 /* seconday bus region sizes */
41 /* pci region assignments */
42 u32 bases[32 - PCI_MEM_INDEX_SHIFT];
44 } r[PCI_REGION_TYPE_COUNT];
47 static int pci_size_to_index(u32 size, enum pci_region_type type)
49 int index = __fls(size);
50 int shift = (type == PCI_REGION_TYPE_IO) ?
51 PCI_IO_INDEX_SHIFT : PCI_MEM_INDEX_SHIFT;
59 static u32 pci_index_to_size(int index, enum pci_region_type type)
61 int shift = (type == PCI_REGION_TYPE_IO) ?
62 PCI_IO_INDEX_SHIFT : PCI_MEM_INDEX_SHIFT;
64 return 0x1 << (index + shift);
67 static enum pci_region_type pci_addr_to_type(u32 addr)
69 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
70 return PCI_REGION_TYPE_IO;
71 if (addr & PCI_BASE_ADDRESS_MEM_PREFETCH)
72 return PCI_REGION_TYPE_PREFMEM;
73 return PCI_REGION_TYPE_MEM;
76 static u32 pci_bar(struct pci_device *pci, int region_num)
78 if (region_num != PCI_ROM_SLOT) {
79 return PCI_BASE_ADDRESS_0 + region_num * 4;
82 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
83 u8 type = pci->header_type & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
84 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
88 pci_set_io_region_addr(struct pci_device *pci, int region_num, u32 addr)
90 pci_config_writel(pci->bdf, pci_bar(pci, region_num), addr);
94 /****************************************************************
96 ****************************************************************/
98 /* host irqs corresponding to PCI irqs A-D */
99 const u8 pci_irqs[4] = {
103 // Return the global irq number corresponding to a host bus device irq pin.
104 static int pci_slot_get_irq(u16 bdf, int pin)
106 int slot_addend = pci_bdf_to_dev(bdf) - 1;
107 return pci_irqs[(pin - 1 + slot_addend) & 3];
110 /* PIIX3/PIIX4 PCI to ISA bridge */
111 static void piix_isa_bridge_init(struct pci_device *pci, void *arg)
118 for (i = 0; i < 4; i++) {
120 /* set to trigger level */
121 elcr[irq >> 3] |= (1 << (irq & 7));
122 /* activate irq remapping in PIIX */
123 pci_config_writeb(pci->bdf, 0x60 + i, irq);
125 outb(elcr[0], 0x4d0);
126 outb(elcr[1], 0x4d1);
127 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
130 static const struct pci_device_id pci_isa_bridge_tbl[] = {
131 /* PIIX3/PIIX4 PCI to ISA bridge */
132 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
133 piix_isa_bridge_init),
134 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
135 piix_isa_bridge_init),
140 static void storage_ide_init(struct pci_device *pci, void *arg)
142 /* IDE: we map it as in ISA mode */
143 pci_set_io_region_addr(pci, 0, PORT_ATA1_CMD_BASE);
144 pci_set_io_region_addr(pci, 1, PORT_ATA1_CTRL_BASE);
145 pci_set_io_region_addr(pci, 2, PORT_ATA2_CMD_BASE);
146 pci_set_io_region_addr(pci, 3, PORT_ATA2_CTRL_BASE);
149 /* PIIX3/PIIX4 IDE */
150 static void piix_ide_init(struct pci_device *pci, void *arg)
153 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
154 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
157 static void pic_ibm_init(struct pci_device *pci, void *arg)
159 /* PIC, IBM, MPIC & MPIC2 */
160 pci_set_io_region_addr(pci, 0, 0x80800000 + 0x00040000);
163 static void apple_macio_init(struct pci_device *pci, void *arg)
166 pci_set_io_region_addr(pci, 0, 0x80800000);
169 static const struct pci_device_id pci_class_tbl[] = {
171 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
172 PCI_CLASS_STORAGE_IDE, piix_ide_init),
173 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
174 PCI_CLASS_STORAGE_IDE, piix_ide_init),
175 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
178 /* PIC, IBM, MIPC & MPIC2 */
179 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
181 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
185 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_init),
186 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_init),
191 /* PIIX4 Power Management device (for ACPI) */
192 static void piix4_pm_init(struct pci_device *pci, void *arg)
195 // acpi sci is hardwired to 9
196 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
198 pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
199 pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
200 pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
201 pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
204 static const struct pci_device_id pci_device_tbl[] = {
205 /* PIIX4 Power Management device (for ACPI) */
206 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
212 static void pci_bios_init_device(struct pci_device *pci)
215 dprintf(1, "PCI: init bdf=%02x:%02x.%x id=%04x:%04x\n"
216 , pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf)
217 , pci->vendor, pci->device);
219 pci_init_device(pci_class_tbl, pci, NULL);
221 /* enable memory mappings */
222 pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
224 /* map the interrupt */
225 int pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
227 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pci_slot_get_irq(bdf, pin));
229 pci_init_device(pci_device_tbl, pci, NULL);
232 static void pci_bios_init_device_in_bus(int bus)
234 struct pci_device *pci;
236 u8 pci_bus = pci_bdf_to_bus(pci->bdf);
241 pci_bios_init_device(pci);
246 /****************************************************************
248 ****************************************************************/
251 pci_bios_init_bus_rec(int bus, u8 *pci_bus)
256 dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus);
258 /* prevent accidental access to unintended devices */
259 foreachbdf(bdf, bus) {
260 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
261 if (class == PCI_CLASS_BRIDGE_PCI) {
262 pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255);
263 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0);
267 foreachbdf(bdf, bus) {
268 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
269 if (class != PCI_CLASS_BRIDGE_PCI) {
272 dprintf(1, "PCI: %s bdf = 0x%x\n", __func__, bdf);
274 u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS);
276 dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus);
277 pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus);
279 dprintf(1, "PCI: primary bus = 0x%x\n", pribus);
282 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
284 if (*pci_bus != secbus) {
285 dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n",
288 pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus);
290 dprintf(1, "PCI: secondary bus = 0x%x\n", secbus);
293 /* set to max for access to all subordinate buses.
294 later set it to accurate value */
295 u8 subbus = pci_config_readb(bdf, PCI_SUBORDINATE_BUS);
296 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255);
298 pci_bios_init_bus_rec(secbus, pci_bus);
300 if (subbus != *pci_bus) {
301 dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n",
305 dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus);
307 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus);
312 pci_bios_init_bus(void)
315 pci_bios_init_bus_rec(0 /* host bus */, &pci_bus);
319 /****************************************************************
321 ****************************************************************/
323 static u32 pci_size_roundup(u32 size)
325 int index = __fls(size-1)+1;
330 pci_bios_get_bar(struct pci_device *pci, int bar, u32 *val, u32 *size)
332 u32 ofs = pci_bar(pci, bar);
334 u32 old = pci_config_readl(bdf, ofs);
337 if (bar == PCI_ROM_SLOT) {
338 mask = PCI_ROM_ADDRESS_MASK;
339 pci_config_writel(bdf, ofs, mask);
341 if (old & PCI_BASE_ADDRESS_SPACE_IO)
342 mask = PCI_BASE_ADDRESS_IO_MASK;
344 mask = PCI_BASE_ADDRESS_MEM_MASK;
345 pci_config_writel(bdf, ofs, ~0);
347 *val = pci_config_readl(bdf, ofs);
348 pci_config_writel(bdf, ofs, old);
349 *size = (~(*val & mask)) + 1;
352 static void pci_bios_bus_reserve(struct pci_bus *bus, int type, u32 size)
356 index = pci_size_to_index(size, type);
357 size = pci_index_to_size(index, type);
358 bus->r[type].count[index]++;
359 bus->r[type].sum += size;
360 if (bus->r[type].max < size)
361 bus->r[type].max = size;
364 static void pci_bios_check_device_in_bus(int bus);
366 static void pci_bios_check_device(struct pci_bus *bus, struct pci_device *dev)
368 if (dev->class == PCI_CLASS_BRIDGE_PCI) {
369 struct pci_bus *s = busses + dev->secondary_bus;
370 pci_bios_check_device_in_bus(dev->secondary_bus);
372 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
373 u32 limit = (type == PCI_REGION_TYPE_IO) ?
374 PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN;
375 s->r[type].size = s->r[type].sum;
376 if (s->r[type].size < limit)
377 s->r[type].size = limit;
378 s->r[type].size = pci_size_roundup(s->r[type].size);
379 pci_bios_bus_reserve(bus, type, s->r[type].size);
381 dprintf(1, "PCI: secondary bus %d sizes: io %x, mem %x, prefmem %x\n",
383 s->r[PCI_REGION_TYPE_IO].size,
384 s->r[PCI_REGION_TYPE_MEM].size,
385 s->r[PCI_REGION_TYPE_PREFMEM].size);
390 for (i = 0; i < PCI_NUM_REGIONS; i++) {
392 pci_bios_get_bar(dev, i, &val, &size);
396 pci_bios_bus_reserve(bus, pci_addr_to_type(val), size);
397 dev->bars[i].addr = val;
398 dev->bars[i].size = size;
399 dev->bars[i].is64 = (!(val & PCI_BASE_ADDRESS_SPACE_IO) &&
400 (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64);
402 if (dev->bars[i].is64) {
408 static void pci_bios_check_device_in_bus(int bus)
410 struct pci_device *pci;
412 dprintf(1, "PCI: check devices bus %d\n", bus);
414 if (pci_bdf_to_bus(pci->bdf) != bus)
416 pci_bios_check_device(&busses[bus], pci);
420 #define ROOT_BASE(top, sum, max) ALIGN_DOWN((top)-(sum),(max) ?: 1)
422 static int pci_bios_init_root_regions(u32 start, u32 end)
424 struct pci_bus *bus = &busses[0];
426 bus->r[PCI_REGION_TYPE_IO].base = 0xc000;
428 if (bus->r[PCI_REGION_TYPE_MEM].sum < bus->r[PCI_REGION_TYPE_PREFMEM].sum) {
429 bus->r[PCI_REGION_TYPE_MEM].base =
431 bus->r[PCI_REGION_TYPE_MEM].sum,
432 bus->r[PCI_REGION_TYPE_MEM].max);
433 bus->r[PCI_REGION_TYPE_PREFMEM].base =
434 ROOT_BASE(bus->r[PCI_REGION_TYPE_MEM].base,
435 bus->r[PCI_REGION_TYPE_PREFMEM].sum,
436 bus->r[PCI_REGION_TYPE_PREFMEM].max);
437 if (bus->r[PCI_REGION_TYPE_PREFMEM].base >= start) {
441 bus->r[PCI_REGION_TYPE_PREFMEM].base =
443 bus->r[PCI_REGION_TYPE_PREFMEM].sum,
444 bus->r[PCI_REGION_TYPE_PREFMEM].max);
445 bus->r[PCI_REGION_TYPE_MEM].base =
446 ROOT_BASE(bus->r[PCI_REGION_TYPE_PREFMEM].base,
447 bus->r[PCI_REGION_TYPE_MEM].sum,
448 bus->r[PCI_REGION_TYPE_MEM].max);
449 if (bus->r[PCI_REGION_TYPE_MEM].base >= start) {
457 /****************************************************************
459 ****************************************************************/
461 static void pci_bios_init_bus_bases(struct pci_bus *bus)
463 u32 base, newbase, size;
466 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
467 dprintf(1, " type %s max %x sum %x base %x\n", region_type_name[type],
468 bus->r[type].max, bus->r[type].sum, bus->r[type].base);
469 base = bus->r[type].base;
470 for (i = ARRAY_SIZE(bus->r[type].count)-1; i >= 0; i--) {
471 size = pci_index_to_size(i, type);
472 if (!bus->r[type].count[i])
474 newbase = base + size * bus->r[type].count[i];
475 dprintf(1, " size %8x: %d bar(s), %8x -> %8x\n",
476 size, bus->r[type].count[i], base, newbase - 1);
477 bus->r[type].bases[i] = base;
483 static u32 pci_bios_bus_get_addr(struct pci_bus *bus, int type, u32 size)
487 index = pci_size_to_index(size, type);
488 addr = bus->r[type].bases[index];
489 bus->r[type].bases[index] += pci_index_to_size(index, type);
493 #define PCI_IO_SHIFT 8
494 #define PCI_MEMORY_SHIFT 16
495 #define PCI_PREF_MEMORY_SHIFT 16
497 static void pci_bios_map_device_in_bus(int bus);
499 static void pci_bios_map_device(struct pci_bus *bus, struct pci_device *dev)
501 if (dev->class == PCI_CLASS_BRIDGE_PCI) {
502 struct pci_bus *s = busses + dev->secondary_bus;
506 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
507 s->r[type].base = pci_bios_bus_get_addr(bus, type, s->r[type].size);
509 dprintf(1, "PCI: init bases bus %d (secondary)\n", dev->secondary_bus);
510 pci_bios_init_bus_bases(s);
512 base = s->r[PCI_REGION_TYPE_IO].base;
513 limit = base + s->r[PCI_REGION_TYPE_IO].size - 1;
515 pci_config_writeb(bdf, PCI_IO_BASE, base >> PCI_IO_SHIFT);
516 pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
517 pci_config_writeb(bdf, PCI_IO_LIMIT, limit >> PCI_IO_SHIFT);
518 pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
520 base = s->r[PCI_REGION_TYPE_MEM].base;
521 limit = base + s->r[PCI_REGION_TYPE_MEM].size - 1;
522 pci_config_writew(bdf, PCI_MEMORY_BASE, base >> PCI_MEMORY_SHIFT);
523 pci_config_writew(bdf, PCI_MEMORY_LIMIT, limit >> PCI_MEMORY_SHIFT);
525 base = s->r[PCI_REGION_TYPE_PREFMEM].base;
526 limit = base + s->r[PCI_REGION_TYPE_PREFMEM].size - 1;
527 pci_config_writew(bdf, PCI_PREF_MEMORY_BASE, base >> PCI_PREF_MEMORY_SHIFT);
528 pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT, limit >> PCI_PREF_MEMORY_SHIFT);
529 pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, 0);
530 pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, 0);
532 pci_bios_map_device_in_bus(dev->secondary_bus);
537 for (i = 0; i < PCI_NUM_REGIONS; i++) {
539 if (dev->bars[i].addr == 0) {
543 addr = pci_bios_bus_get_addr(bus, pci_addr_to_type(dev->bars[i].addr),
545 dprintf(1, " bar %d, addr %x, size %x [%s]\n",
546 i, addr, dev->bars[i].size,
547 region_type_name[pci_addr_to_type(dev->bars[i].addr)]);
548 pci_set_io_region_addr(dev, i, addr);
550 if (dev->bars[i].is64) {
556 static void pci_bios_map_device_in_bus(int bus)
558 struct pci_device *pci;
562 if (pci_bdf_to_bus(bdf) != bus)
564 dprintf(1, "PCI: map device bdf=%02x:%02x.%x\n"
565 , pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf));
566 pci_bios_map_device(&busses[bus], pci);
571 /****************************************************************
573 ****************************************************************/
578 if (CONFIG_COREBOOT || usingXen()) {
579 // PCI setup already done by coreboot or Xen - just do probe.
584 dprintf(3, "pci setup\n");
586 u32 start = BUILD_PCIMEM_START;
587 u32 end = BUILD_PCIMEM_END;
589 dprintf(1, "=== PCI bus & bridge init ===\n");
590 if (pci_probe_host() != 0) {
595 dprintf(1, "=== PCI device probing ===\n");
598 dprintf(1, "=== PCI new allocation pass #1 ===\n");
599 busses = malloc_tmp(sizeof(*busses) * (MaxPCIBus + 1));
604 memset(busses, 0, sizeof(*busses) * (MaxPCIBus + 1));
605 pci_bios_check_device_in_bus(0 /* host bus */);
606 if (pci_bios_init_root_regions(start, end) != 0) {
607 panic("PCI: out of address space\n");
610 dprintf(1, "=== PCI new allocation pass #2 ===\n");
611 dprintf(1, "PCI: init bases bus 0 (primary)\n");
612 pci_bios_init_bus_bases(&busses[0]);
613 pci_bios_map_device_in_bus(0 /* host bus */);
615 pci_bios_init_device_in_bus(0 /* host bus */);
617 struct pci_device *pci;
619 pci_init_device(pci_isa_bridge_tbl, pci, NULL);