4 // Configuration definitions.
6 //#define CONFIG_APPNAME "QEMU"
7 //#define CONFIG_CPUNAME8 "QEMUCPU "
8 //#define CONFIG_APPNAME6 "QEMU "
9 //#define CONFIG_APPNAME4 "QEMU"
10 #define CONFIG_APPNAME "Bochs"
11 #define CONFIG_CPUNAME8 "BOCHSCPU"
12 #define CONFIG_APPNAME6 "BOCHS "
13 #define CONFIG_APPNAME4 "BXPC"
15 // Configure for use with KVM.
17 // Configure as a coreboot payload.
18 #define CONFIG_COREBOOT 0
20 // Control how verbose debug output is.
21 #define CONFIG_DEBUG_LEVEL 1
23 // Send debugging information to serial port
24 #define CONFIG_DEBUG_SERIAL 0
26 // Support for int13 floppy drive access
27 #define CONFIG_FLOPPY_SUPPORT 1
28 // Support for IDE disk code
30 // Use 32bit PIO accesses on ATA (minor optimization on PCI transfers)
31 #define CONFIG_ATA_PIO32 0
32 // Support for booting from a CD
33 #define CONFIG_CDROM_BOOT 1
34 // Support for emulating a boot CD as a floppy/harddrive
35 #define CONFIG_CDROM_EMU 1
36 // Support int 1a/b1 PCI BIOS calls
37 #define CONFIG_PCIBIOS 1
38 // Support int 15/53 APM BIOS calls
39 #define CONFIG_APMBIOS 1
40 // Support PnP BIOS entry point.
41 #define CONFIG_PNPBIOS 1
42 // Support int 19/18 system bootup support
44 // Support an interactive boot menu at end of post.
45 #define CONFIG_BOOTMENU 1
46 // Amount of time (in ms) to wait at menu before selecting normal boot.
47 #define CONFIG_BOOTMENU_WAIT 2500
48 // Support int 14 serial port calls
49 #define CONFIG_SERIAL 1
50 // Support int 17 parallel port calls
52 // Support int 16 keyboard calls
53 #define CONFIG_KEYBOARD 1
54 // Support calling int155f on each keyboard event
55 #define CONFIG_KBD_CALL_INT15_4F 1
56 // Disable A20 on 16bit boot
57 #define CONFIG_DISABLE_A20 0
58 // Support for int15c2 mouse calls
59 #define CONFIG_PS2_MOUSE 1
60 // If the target machine has multiple independent root buses, the
61 // extra buses may be specified here.
62 #define CONFIG_PCI_ROOT1 0x00
63 #define CONFIG_PCI_ROOT2 0x00
64 // Support searching coreboot flash format.
65 #define CONFIG_COREBOOT_FLASH 0
66 // Support the lzma decompression algorighm.
68 // Support finding and running option roms during post.
69 #define CONFIG_OPTIONROMS 1
70 // Set if option roms are already copied to 0xc0000-0xf0000
71 #define CONFIG_OPTIONROMS_DEPLOYED 1
72 // When option roms are not pre-deployed, SeaBIOS can copy an optionrom
73 // from flash for up to 2 devices.
74 #define OPTIONROM_VENDEV_1 0x00000000
75 #define OPTIONROM_MEM_1 0x00000000
76 #define OPTIONROM_VENDEV_2 0x00000000
77 #define OPTIONROM_MEM_2 0x00000000
79 // Support generation of a PIR table in 0xf000 segment (for emulators)
80 #define CONFIG_PIRTABLE 1
81 // Support generation of MPTable (for emulators)
82 #define CONFIG_MPTABLE 1
83 // Support generation of SM BIOS tables (for emulators)
84 #define CONFIG_SMBIOS 1
85 // Support finding a UUID (for smbios) via "magic" outl sequence.
86 #define CONFIG_UUID_BACKDOOR 1
87 // Support generation of ACPI tables (for emulators)
89 // Support bios callbacks specific to via vgabios.
90 #define CONFIG_VGAHOOKS 0
91 // Support S3 resume handler.
92 #define CONFIG_S3_RESUME 1
93 // Run the vga rom during S3 resume.
94 #define CONFIG_S3_RESUME_VGA_INIT 0
95 // define it if the (emulated) hardware supports SMM mode
96 #define CONFIG_USE_SMM 1
97 // Maximum number of map entries in the e820 map
98 #define CONFIG_MAX_E820 32
99 // Space to reserve in f-segment for run-time built bios tables.
100 #define CONFIG_MAX_BIOSTABLE 2048
101 // Space to reserve in high-memory for tables
102 #define CONFIG_MAX_HIGHTABLE (64*1024)
104 #define CONFIG_MAX_ATA_INTERFACES 4
105 #define CONFIG_MAX_ATA_DEVICES (CONFIG_MAX_ATA_INTERFACES*2)
107 #define CONFIG_MODEL_ID 0xFC
108 #define CONFIG_SUBMODEL_ID 0x00
109 #define CONFIG_BIOS_REVISION 0x01
111 // Various memory addresses used by the code.
112 #define BUILD_STACK_ADDR 0x7c00
113 #define BUILD_S3RESUME_STACK_ADDR 0x1000
114 #define BUILD_AP_BOOT_ADDR 0x10000
115 #define BUILD_ROM_START 0xc0000
116 #define BUILD_BIOS_ADDR 0xf0000
117 #define BUILD_BIOS_SIZE 0x10000
118 // 32KB for shadow ram copying (works around emulator deficiencies)
119 #define BUILD_BIOS_TMP_ADDR 0x30000
121 #define BUILD_APIC_ADDR 0xfee00000
122 #define BUILD_IOAPIC_ADDR 0xfec00000
124 #define BUILD_SMM_INIT_ADDR 0x38000
125 #define BUILD_SMM_ADDR 0xa8000
126 #define BUILD_SMM_SIZE 0x8000
128 // Important real-mode segments
129 #define SEG_IVT 0x0000
130 #define SEG_BDA 0x0040
131 #define SEG_BIOS 0xf000
133 // Segment definitions in protected mode (see rombios32_gdt in misc.c)
134 #define SEG32_MODE32_CS (1 << 3)
135 #define SEG32_MODE32_DS (2 << 3)
136 #define SEG32_MODE16_CS (3 << 3)
137 #define SEG32_MODE16_DS (4 << 3)
138 #define SEG32_MODE16BIG_CS (5 << 3)
139 #define SEG32_MODE16BIG_DS (6 << 3)
141 // Debugging levels. If non-zero and CONFIG_DEBUG_LEVEL is greater
142 // than the specified value, then the corresponding irq handler will
143 // report every enter event.
144 #define DEBUG_ISR_02 1
145 #define DEBUG_HDL_05 1
146 #define DEBUG_ISR_08 20
147 #define DEBUG_ISR_09 9
148 #define DEBUG_ISR_0e 9
149 #define DEBUG_HDL_10 20
150 #define DEBUG_HDL_11 1
151 #define DEBUG_HDL_12 1
152 #define DEBUG_HDL_13 10
153 #define DEBUG_HDL_14 1
154 #define DEBUG_HDL_15 9
155 #define DEBUG_HDL_16 9
156 #define DEBUG_HDL_17 1
157 #define DEBUG_HDL_18 1
158 #define DEBUG_HDL_19 1
159 #define DEBUG_HDL_1a 9
160 #define DEBUG_HDL_40 1
161 #define DEBUG_ISR_70 9
162 #define DEBUG_ISR_74 9
163 #define DEBUG_ISR_75 1
164 #define DEBUG_ISR_76 10
165 #define DEBUG_ISR_hwpic1 5
166 #define DEBUG_ISR_hwpic2 5
167 #define DEBUG_HDL_pnp 1