4 #include "../out/autoconf.h"
6 // Configuration definitions.
8 //#define CONFIG_APPNAME "QEMU"
9 //#define CONFIG_CPUNAME8 "QEMUCPU "
10 //#define CONFIG_APPNAME6 "QEMU "
11 //#define CONFIG_APPNAME4 "QEMU"
12 #define CONFIG_APPNAME "Bochs"
13 #define CONFIG_CPUNAME8 "BOCHSCPU"
14 #define CONFIG_APPNAME6 "BOCHS "
15 #define CONFIG_APPNAME4 "BXPC"
17 // Screen writes are also sent to debug ports.
18 #define CONFIG_SCREEN_AND_DEBUG 1
20 // Support running hardware initialization in parallel
21 #define CONFIG_THREADS 1
22 // Allow hardware init to run in parallel with optionrom execution
23 #define CONFIG_THREAD_OPTIONROMS 0
24 // Support relocating the one time initialization code to high memory
25 #define CONFIG_RELOCATE_INIT 1
26 // Support int13 disk/floppy drive functions
27 #define CONFIG_DRIVES 1
28 // Support floppy drive access
29 #define CONFIG_FLOPPY 1
30 // Support USB devices
32 // Support USB UHCI controllers
33 #define CONFIG_USB_UHCI 1
34 // Support USB OHCI controllers
35 #define CONFIG_USB_OHCI 1
36 // Support USB EHCI controllers
37 #define CONFIG_USB_EHCI 1
39 #define CONFIG_USB_MSC 1
41 #define CONFIG_USB_HUB 1
42 // Support USB keyboards
43 #define CONFIG_USB_KEYBOARD 1
45 #define CONFIG_USB_MOUSE 1
46 // Support PS2 ports (keyboard and mouse)
47 #define CONFIG_PS2PORT 1
48 // Support for IDE disk code
50 // Detect and try to use ATA bus mastering DMA controllers.
51 #define CONFIG_ATA_DMA 0
52 // Use 32bit PIO accesses on ATA (minor optimization on PCI transfers)
53 #define CONFIG_ATA_PIO32 0
54 // Support for AHCI disk code
56 // Support for booting from a CD
57 #define CONFIG_CDROM_BOOT 1
58 // Support for emulating a boot CD as a floppy/harddrive
59 #define CONFIG_CDROM_EMU 1
60 // Support int 1a/b1 PCI BIOS calls
61 #define CONFIG_PCIBIOS 1
62 // Support int 15/53 APM BIOS calls
63 #define CONFIG_APMBIOS 1
64 // Support PnP BIOS entry point.
65 #define CONFIG_PNPBIOS 1
66 // Support Post Memory Manager (PMM) entry point.
68 // Support int 19/18 system bootup support
70 // Support an interactive boot menu at end of post.
71 #define CONFIG_BOOTMENU 1
72 // Amount of time (in ms) to wait at menu before selecting normal boot.
73 #define CONFIG_BOOTMENU_WAIT 2500
74 // Support int 14 serial port calls
75 #define CONFIG_SERIAL 1
76 // Support int 17 parallel port calls
78 // Support int 16 keyboard calls
79 #define CONFIG_KEYBOARD 1
80 // Support calling int155f on each keyboard event
81 #define CONFIG_KBD_CALL_INT15_4F 1
82 // Disable A20 on 16bit boot
83 #define CONFIG_DISABLE_A20 0
84 // Support for int15c2 mouse calls
85 #define CONFIG_MOUSE 1
86 // If the target machine has multiple independent root buses, the
87 // extra buses may be specified here.
88 #define CONFIG_PCI_ROOT1 0x00
89 #define CONFIG_PCI_ROOT2 0x00
90 // Support searching coreboot flash format.
91 #define CONFIG_COREBOOT_FLASH 1
92 // Support floppy images in the coreboot flash.
93 #define CONFIG_FLASH_FLOPPY 1
94 // Support the lzma decompression algorighm.
96 // Support finding and running option roms during post.
97 #define CONFIG_OPTIONROMS 1
98 // Set if option roms are already copied to 0xc0000-0xf0000
99 #define CONFIG_OPTIONROMS_DEPLOYED 0
100 // When option roms are not pre-deployed, SeaBIOS can copy an optionrom
101 // from flash for up to 2 devices.
102 #define OPTIONROM_VENDEV_1 0x00000000
103 #define OPTIONROM_MEM_1 0x00000000
104 #define OPTIONROM_VENDEV_2 0x00000000
105 #define OPTIONROM_MEM_2 0x00000000
107 // Support generation of a PIR table in 0xf000 segment (for emulators)
108 #define CONFIG_PIRTABLE 1
109 // Support generation of MPTable (for emulators)
110 #define CONFIG_MPTABLE 1
111 // Support generation of SM BIOS tables (for emulators)
112 #define CONFIG_SMBIOS 1
113 // Support finding a UUID (for smbios) via "magic" outl sequence.
114 #define CONFIG_UUID_BACKDOOR 1
115 // Support generation of ACPI tables (for emulators)
116 #define CONFIG_ACPI 1
117 // Support S3 resume handler.
118 #define CONFIG_S3_RESUME 1
119 // Run the vga rom during S3 resume.
120 #define CONFIG_S3_RESUME_VGA_INIT 0
121 // Support boot splash
122 #define CONFIG_BOOTSPLASH 1
123 // define it if the (emulated) hardware supports SMM mode
124 #define CONFIG_USE_SMM 1
125 // Maximum number of map entries in the e820 map
126 #define CONFIG_MAX_E820 32
127 // Space to reserve in f-segment for dynamic allocations
128 #define CONFIG_MAX_BIOSTABLE 2048
129 // Space to reserve in high-memory for tables
130 #define CONFIG_MAX_HIGHTABLE (64*1024)
131 // Largest supported externaly facing drive id
132 #define CONFIG_MAX_EXTDRIVE 16
134 #define CONFIG_MODEL_ID 0xFC
135 #define CONFIG_SUBMODEL_ID 0x00
136 #define CONFIG_BIOS_REVISION 0x01
138 // Support boot from virtio storage
139 #define CONFIG_VIRTIO_BLK 1
141 // Various memory addresses used by the code.
142 #define BUILD_STACK_ADDR 0x7000
143 #define BUILD_S3RESUME_STACK_ADDR 0x1000
144 #define BUILD_AP_BOOT_ADDR 0x10000
145 #define BUILD_EBDA_MINIMUM 0x90000
146 #define BUILD_LOWRAM_END 0xa0000
147 #define BUILD_ROM_START 0xc0000
148 #define BUILD_BIOS_ADDR 0xf0000
149 #define BUILD_BIOS_SIZE 0x10000
150 // 32KB for shadow ram copying (works around emulator deficiencies)
151 #define BUILD_BIOS_TMP_ADDR 0x30000
152 #define BUILD_MAX_HIGHMEM 0xe0000000
154 // Support old pci mem assignment behaviour
155 //#define CONFIG_OLD_PCIMEM_ASSIGNMENT 1
156 #if CONFIG_OLD_PCIMEM_ASSIGNMENT
157 #define BUILD_PCIMEM_START 0xf0000000
158 #define BUILD_PCIMEM_SIZE (BUILD_PCIMEM_END - BUILD_PCIMEM_START)
159 #define BUILD_PCIMEM_END 0xfec00000 /* IOAPIC is mapped at */
160 #define BUILD_PCIPREFMEM_START 0
161 #define BUILD_PCIPREFMEM_SIZE 0
162 #define BUILD_PCIPREFMEM_END 0
164 #define BUILD_PCIMEM_START 0xf0000000
165 #define BUILD_PCIMEM_SIZE 0x08000000 /* half- of pci window */
166 #define BUILD_PCIMEM_END (BUILD_PCIMEM_START + BUILD_PCIMEM_SIZE)
167 #define BUILD_PCIPREFMEM_START BUILD_PCIMEM_END
168 #define BUILD_PCIPREFMEM_SIZE (BUILD_PCIPREFMEM_END - BUILD_PCIPREFMEM_START)
169 #define BUILD_PCIPREFMEM_END 0xfec00000 /* IOAPIC is mapped at */
172 #define BUILD_APIC_ADDR 0xfee00000
173 #define BUILD_IOAPIC_ADDR 0xfec00000
175 #define BUILD_SMM_INIT_ADDR 0x38000
176 #define BUILD_SMM_ADDR 0xa8000
177 #define BUILD_SMM_SIZE 0x8000
179 // Important real-mode segments
180 #define SEG_IVT 0x0000
181 #define SEG_BDA 0x0040
182 #define SEG_BIOS 0xf000
184 // Segment definitions in protected mode (see rombios32_gdt in misc.c)
185 #define SEG32_MODE32_CS (1 << 3)
186 #define SEG32_MODE32_DS (2 << 3)
187 #define SEG32_MODE16_CS (3 << 3)
188 #define SEG32_MODE16_DS (4 << 3)
189 #define SEG32_MODE16BIG_CS (5 << 3)
190 #define SEG32_MODE16BIG_DS (6 << 3)
192 // Debugging levels. If non-zero and CONFIG_DEBUG_LEVEL is greater
193 // than the specified value, then the corresponding irq handler will
194 // report every enter event.
195 #define DEBUG_ISR_02 1
196 #define DEBUG_HDL_05 1
197 #define DEBUG_ISR_08 20
198 #define DEBUG_ISR_09 9
199 #define DEBUG_ISR_0e 9
200 #define DEBUG_HDL_10 20
201 #define DEBUG_HDL_11 2
202 #define DEBUG_HDL_12 2
203 #define DEBUG_HDL_13 10
204 #define DEBUG_HDL_14 2
205 #define DEBUG_HDL_15 9
206 #define DEBUG_HDL_16 9
207 #define DEBUG_HDL_17 2
208 #define DEBUG_HDL_18 1
209 #define DEBUG_HDL_19 1
210 #define DEBUG_HDL_1a 9
211 #define DEBUG_HDL_40 1
212 #define DEBUG_ISR_70 9
213 #define DEBUG_ISR_74 9
214 #define DEBUG_ISR_75 1
215 #define DEBUG_ISR_76 10
216 #define DEBUG_ISR_hwpic1 5
217 #define DEBUG_ISR_hwpic2 5
218 #define DEBUG_HDL_pnp 1
219 #define DEBUG_HDL_pmm 1
220 #define DEBUG_HDL_pcibios32 9
221 #define DEBUG_HDL_apm 9
223 #define DEBUG_unimplemented 2
224 #define DEBUG_invalid 3
225 #define DEBUG_thread 2