1 // 16bit code to handle system clocks.
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2002 MandrakeSoft S.A.
6 // This file may be distributed under the terms of the GNU GPLv3 license.
8 #include "biosvar.h" // struct bregs
9 #include "util.h" // debug_enter
10 #include "disk.h" // floppy_tick
11 #include "cmos.h" // inb_cmos
13 #define DEBUGF1(fmt, args...) bprintf(0, fmt , ##args)
14 #define DEBUGF(fmt, args...)
19 outb_cmos(0x26, CMOS_STATUS_A);
20 outb_cmos(0x02, CMOS_STATUS_B);
21 inb_cmos(CMOS_STATUS_C);
22 inb_cmos(CMOS_STATUS_D);
28 // This function checks to see if the update-in-progress bit
29 // is set in CMOS Status Register A. If not, it returns 0.
30 // If it is set, it tries to wait until there is a transition
31 // to 0, and will return 0 if such a transition occurs. A 1
32 // is returned only after timing out. The maximum period
33 // that this bit should be set is constrained to 244useconds.
34 // The count I use below guarantees coverage or more than
35 // this time, with any reasonable IPS setting.
38 while (--count != 0) {
39 if ( (inb_cmos(CMOS_STATUS_A) & 0x80) == 0 )
42 return 1; // update-in-progress never transitioned to 0
45 // get current clock count
47 handle_1a00(struct bregs *regs)
49 u32 ticks = GET_BDA(timer_counter);
50 regs->cx = ticks >> 16;
52 regs->al = GET_BDA(timer_rollover);
53 SET_BDA(timer_rollover, 0); // reset flag
57 // Set Current Clock Count
59 handle_1a01(struct bregs *regs)
61 u32 ticks = (regs->cx << 16) | regs->dx;
62 SET_BDA(timer_counter, ticks);
63 SET_BDA(timer_rollover, 0); // reset flag
70 handle_1a02(struct bregs *regs)
77 regs->dh = inb_cmos(CMOS_RTC_SECONDS);
78 regs->cl = inb_cmos(CMOS_RTC_MINUTES);
79 regs->ch = inb_cmos(CMOS_RTC_HOURS);
80 regs->dl = inb_cmos(CMOS_STATUS_B) & 0x01;
88 handle_1a03(struct bregs *regs)
90 // Using a debugger, I notice the following masking/setting
91 // of bits in Status Register B, by setting Reg B to
92 // a few values and getting its value after INT 1A was called.
95 // before 1111 1101 0111 1101 0000 0000
96 // after 0110 0010 0110 0010 0000 0010
98 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
99 // My assumption: RegB = ((RegB & 01100000b) | 00000010b)
100 if (rtc_updating()) {
102 // fall through as if an update were not in progress
104 outb_cmos(regs->dh, CMOS_RTC_SECONDS);
105 outb_cmos(regs->cl, CMOS_RTC_MINUTES);
106 outb_cmos(regs->ch, CMOS_RTC_HOURS);
107 // Set Daylight Savings time enabled bit to requested value
108 u8 val8 = (inb_cmos(CMOS_STATUS_B) & 0x60) | 0x02 | (regs->dl & 0x01);
109 outb_cmos(val8, CMOS_STATUS_B);
111 regs->al = val8; // val last written to Reg B
117 handle_1a04(struct bregs *regs)
120 if (rtc_updating()) {
124 regs->cl = inb_cmos(CMOS_RTC_YEAR);
125 regs->dh = inb_cmos(CMOS_RTC_MONTH);
126 regs->dl = inb_cmos(CMOS_RTC_DAY_MONTH);
127 regs->ch = inb_cmos(CMOS_CENTURY);
134 handle_1a05(struct bregs *regs)
136 // Using a debugger, I notice the following masking/setting
137 // of bits in Status Register B, by setting Reg B to
138 // a few values and getting its value after INT 1A was called.
140 // try#1 try#2 try#3 try#4
141 // before 1111 1101 0111 1101 0000 0010 0000 0000
142 // after 0110 1101 0111 1101 0000 0010 0000 0000
144 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
145 // My assumption: RegB = (RegB & 01111111b)
146 if (rtc_updating()) {
151 outb_cmos(regs->cl, CMOS_RTC_YEAR);
152 outb_cmos(regs->dh, CMOS_RTC_MONTH);
153 outb_cmos(regs->dl, CMOS_RTC_DAY_MONTH);
154 outb_cmos(regs->ch, CMOS_CENTURY);
155 u8 val8 = inb_cmos(CMOS_STATUS_B) & 0x7f; // clear halt-clock bit
156 outb_cmos(val8, CMOS_STATUS_B);
158 regs->al = val8; // AL = val last written to Reg B
162 // Set Alarm Time in CMOS
164 handle_1a06(struct bregs *regs)
166 // Using a debugger, I notice the following masking/setting
167 // of bits in Status Register B, by setting Reg B to
168 // a few values and getting its value after INT 1A was called.
171 // before 1101 1111 0101 1111 0000 0000
172 // after 0110 1111 0111 1111 0010 0000
174 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
175 // My assumption: RegB = ((RegB & 01111111b) | 00100000b)
176 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
179 // Alarm interrupt enabled already
183 if (rtc_updating()) {
185 // fall through as if an update were not in progress
187 outb_cmos(regs->dh, CMOS_RTC_SECONDS_ALARM);
188 outb_cmos(regs->cl, CMOS_RTC_MINUTES_ALARM);
189 outb_cmos(regs->ch, CMOS_RTC_HOURS_ALARM);
190 outb(inb(PORT_PIC2_DATA) & ~PIC2_IRQ8, PORT_PIC2_DATA); // enable IRQ 8
191 // enable Status Reg B alarm bit, clear halt clock bit
192 outb_cmos((val8 & 0x7f) | 0x20, CMOS_STATUS_B);
198 handle_1a07(struct bregs *regs)
200 // Using a debugger, I notice the following masking/setting
201 // of bits in Status Register B, by setting Reg B to
202 // a few values and getting its value after INT 1A was called.
204 // try#1 try#2 try#3 try#4
205 // before 1111 1101 0111 1101 0010 0000 0010 0010
206 // after 0100 0101 0101 0101 0000 0000 0000 0010
208 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
209 // My assumption: RegB = (RegB & 01010111b)
210 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
211 // clear clock-halt bit, disable alarm bit
212 outb_cmos(val8 & 0x57, CMOS_STATUS_B); // disable alarm bit
214 regs->al = val8; // val last written to Reg B
219 handle_1ab1(struct bregs *regs)
221 // XXX - pcibios stuff
227 handle_1aXX(struct bregs *regs)
232 // INT 1Ah Time-of-day Service Entry Point
234 handle_1a(struct bregs *regs)
238 case 0x00: handle_1a00(regs); break;
239 case 0x01: handle_1a01(regs); break;
240 case 0x02: handle_1a02(regs); break;
241 case 0x03: handle_1a03(regs); break;
242 case 0x04: handle_1a04(regs); break;
243 case 0x05: handle_1a05(regs); break;
244 case 0x06: handle_1a06(regs); break;
245 case 0x07: handle_1a07(regs); break;
246 case 0xb1: handle_1ab1(regs); break;
247 default: handle_1aXX(regs); break;
258 // INT 08h System Timer ISR Entry Point
267 u32 counter = GET_BDA(timer_counter);
269 // compare to one days worth of timer ticks at 18.2 hz
270 if (counter >= 0x001800B0) {
271 // there has been a midnight rollover at this point
273 SET_BDA(timer_rollover, GET_BDA(timer_rollover) + 1);
276 SET_BDA(timer_counter, counter);
278 // chain to user timer tick INT #0x1c
280 memset(&br, 0, sizeof(br));
281 call16_int(0x1c, &br);
288 // Set Interval requested.
290 handle_158300(struct bregs *regs)
292 if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING) {
293 // Interval already set.
294 DEBUGF("int15: Func 83h, failed, already waiting.\n" );
295 set_code_fail(regs, RET_EUNSUPPORTED);
297 // Interval not already set.
298 SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
299 u32 v = (regs->es << 16) | regs->bx;
300 SET_BDA(ptr_user_wait_complete_flag, v);
301 v = (regs->dx << 16) | regs->cx;
302 SET_BDA(user_wait_timeout, v);
304 // Unmask IRQ8 so INT70 will get through.
305 u8 irqDisable = inb(PORT_PIC2_DATA);
306 outb(irqDisable & ~PIC2_IRQ8, PORT_PIC2_DATA);
307 // Turn on the Periodic Interrupt timer
308 u8 bRegister = inb_cmos(CMOS_STATUS_B);
309 outb_cmos(CMOS_STATUS_B, bRegister | CSB_EN_ALARM_IRQ);
311 set_success(regs); // XXX - no set ah?
314 // Clear interval requested
316 handle_158301(struct bregs *regs)
318 SET_BDA(rtc_wait_flag, 0); // Clear status byte
319 // Turn off the Periodic Interrupt timer
320 u8 bRegister = inb_cmos(CMOS_STATUS_B);
321 outb_cmos(CMOS_STATUS_B, bRegister & ~CSB_EN_ALARM_IRQ);
322 set_success(regs); // XXX - no set ah?
326 handle_1583XX(struct bregs *regs)
328 set_code_fail(regs, RET_EUNSUPPORTED);
333 handle_1583(struct bregs *regs)
336 case 0x00: handle_158300(regs); break;
337 case 0x01: handle_158301(regs); break;
338 default: handle_1583XX(regs); break;
342 // int70h: IRQ8 - CMOS RTC
348 // Check which modes are enabled and have occurred.
349 u8 registerB = inb_cmos(CMOS_STATUS_B);
350 u8 registerC = inb_cmos(CMOS_STATUS_C);
352 if (!(registerB & 0x60))
354 if (registerC & 0x20) {
355 // Handle Alarm Interrupt.
357 memset(&br, 0, sizeof(br));
358 call16_int(0x4a, &br);
360 if (!(registerC & 0x40))
363 // Handle Periodic Interrupt.
365 if (!GET_BDA(rtc_wait_flag))
368 // Wait Interval (Int 15, AH=83) active.
369 u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds.
372 u32 segoff = GET_BDA(ptr_user_wait_complete_flag);
373 u16 segment = segoff >> 16;
374 u16 offset = segoff & 0xffff;
375 // Turn off status byte.
376 SET_BDA(rtc_wait_flag, 0);
377 // Clear the Periodic Interrupt.
378 outb_cmos(registerB & 0x37, CMOS_STATUS_B);
379 // Write to specified flag byte.
380 u8 oldval = GET_FARVAR(segment, *(u8*)(offset+0));
381 SET_FARVAR(segment, *(u8*)(offset+0), oldval | 0x80);
385 SET_BDA(user_wait_timeout, time);