1 // 16bit code to handle system clocks.
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2002 MandrakeSoft S.A.
6 // This file may be distributed under the terms of the GNU GPLv3 license.
8 #include "biosvar.h" // struct bregs
9 #include "util.h" // debug_enter
10 #include "disk.h" // floppy_tick
11 #include "cmos.h" // inb_cmos
13 #define DEBUGF1(fmt, args...) bprintf(0, fmt , ##args)
14 #define DEBUGF(fmt, args...)
19 // timer0: binary count, 16bit count, mode 2
20 outb(0x34, PORT_PIT_MODE);
21 // maximum count of 0000H = 18.2Hz
22 outb(0x0, PORT_PIT_COUNTER0);
23 outb(0x0, PORT_PIT_COUNTER0);
29 return (val & 0xf) + ((val >> 4) * 10);
37 u32 seconds = bcd2bin(inb_cmos(CMOS_RTC_SECONDS));
38 u32 ticks = (seconds * 18206507) / 1000000;
39 u32 minutes = bcd2bin(inb_cmos(CMOS_RTC_MINUTES));
40 ticks += (minutes * 10923904) / 10000;
41 u32 hours = bcd2bin(inb_cmos(CMOS_RTC_HOURS));
42 ticks += (hours * 65543427) / 1000;
43 SET_BDA(timer_counter, ticks);
44 SET_BDA(timer_rollover, 0);
50 outb_cmos(0x26, CMOS_STATUS_A);
51 outb_cmos(0x02, CMOS_STATUS_B);
52 inb_cmos(CMOS_STATUS_C);
53 inb_cmos(CMOS_STATUS_D);
59 // This function checks to see if the update-in-progress bit
60 // is set in CMOS Status Register A. If not, it returns 0.
61 // If it is set, it tries to wait until there is a transition
62 // to 0, and will return 0 if such a transition occurs. A 1
63 // is returned only after timing out. The maximum period
64 // that this bit should be set is constrained to 244useconds.
65 // The count I use below guarantees coverage or more than
66 // this time, with any reasonable IPS setting.
69 while (--count != 0) {
70 if ( (inb_cmos(CMOS_STATUS_A) & 0x80) == 0 )
73 return 1; // update-in-progress never transitioned to 0
76 // get current clock count
78 handle_1a00(struct bregs *regs)
80 u32 ticks = GET_BDA(timer_counter);
81 regs->cx = ticks >> 16;
83 regs->al = GET_BDA(timer_rollover);
84 SET_BDA(timer_rollover, 0); // reset flag
88 // Set Current Clock Count
90 handle_1a01(struct bregs *regs)
92 u32 ticks = (regs->cx << 16) | regs->dx;
93 SET_BDA(timer_counter, ticks);
94 SET_BDA(timer_rollover, 0); // reset flag
101 handle_1a02(struct bregs *regs)
103 if (rtc_updating()) {
108 regs->dh = inb_cmos(CMOS_RTC_SECONDS);
109 regs->cl = inb_cmos(CMOS_RTC_MINUTES);
110 regs->ch = inb_cmos(CMOS_RTC_HOURS);
111 regs->dl = inb_cmos(CMOS_STATUS_B) & 0x01;
119 handle_1a03(struct bregs *regs)
121 // Using a debugger, I notice the following masking/setting
122 // of bits in Status Register B, by setting Reg B to
123 // a few values and getting its value after INT 1A was called.
126 // before 1111 1101 0111 1101 0000 0000
127 // after 0110 0010 0110 0010 0000 0010
129 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
130 // My assumption: RegB = ((RegB & 01100000b) | 00000010b)
131 if (rtc_updating()) {
133 // fall through as if an update were not in progress
135 outb_cmos(regs->dh, CMOS_RTC_SECONDS);
136 outb_cmos(regs->cl, CMOS_RTC_MINUTES);
137 outb_cmos(regs->ch, CMOS_RTC_HOURS);
138 // Set Daylight Savings time enabled bit to requested value
139 u8 val8 = (inb_cmos(CMOS_STATUS_B) & 0x60) | 0x02 | (regs->dl & 0x01);
140 outb_cmos(val8, CMOS_STATUS_B);
142 regs->al = val8; // val last written to Reg B
148 handle_1a04(struct bregs *regs)
151 if (rtc_updating()) {
155 regs->cl = inb_cmos(CMOS_RTC_YEAR);
156 regs->dh = inb_cmos(CMOS_RTC_MONTH);
157 regs->dl = inb_cmos(CMOS_RTC_DAY_MONTH);
158 regs->ch = inb_cmos(CMOS_CENTURY);
165 handle_1a05(struct bregs *regs)
167 // Using a debugger, I notice the following masking/setting
168 // of bits in Status Register B, by setting Reg B to
169 // a few values and getting its value after INT 1A was called.
171 // try#1 try#2 try#3 try#4
172 // before 1111 1101 0111 1101 0000 0010 0000 0000
173 // after 0110 1101 0111 1101 0000 0010 0000 0000
175 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
176 // My assumption: RegB = (RegB & 01111111b)
177 if (rtc_updating()) {
182 outb_cmos(regs->cl, CMOS_RTC_YEAR);
183 outb_cmos(regs->dh, CMOS_RTC_MONTH);
184 outb_cmos(regs->dl, CMOS_RTC_DAY_MONTH);
185 outb_cmos(regs->ch, CMOS_CENTURY);
186 u8 val8 = inb_cmos(CMOS_STATUS_B) & 0x7f; // clear halt-clock bit
187 outb_cmos(val8, CMOS_STATUS_B);
189 regs->al = val8; // AL = val last written to Reg B
193 // Set Alarm Time in CMOS
195 handle_1a06(struct bregs *regs)
197 // Using a debugger, I notice the following masking/setting
198 // of bits in Status Register B, by setting Reg B to
199 // a few values and getting its value after INT 1A was called.
202 // before 1101 1111 0101 1111 0000 0000
203 // after 0110 1111 0111 1111 0010 0000
205 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
206 // My assumption: RegB = ((RegB & 01111111b) | 00100000b)
207 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
210 // Alarm interrupt enabled already
214 if (rtc_updating()) {
216 // fall through as if an update were not in progress
218 outb_cmos(regs->dh, CMOS_RTC_SECONDS_ALARM);
219 outb_cmos(regs->cl, CMOS_RTC_MINUTES_ALARM);
220 outb_cmos(regs->ch, CMOS_RTC_HOURS_ALARM);
221 outb(inb(PORT_PIC2_DATA) & ~PIC2_IRQ8, PORT_PIC2_DATA); // enable IRQ 8
222 // enable Status Reg B alarm bit, clear halt clock bit
223 outb_cmos((val8 & 0x7f) | 0x20, CMOS_STATUS_B);
229 handle_1a07(struct bregs *regs)
231 // Using a debugger, I notice the following masking/setting
232 // of bits in Status Register B, by setting Reg B to
233 // a few values and getting its value after INT 1A was called.
235 // try#1 try#2 try#3 try#4
236 // before 1111 1101 0111 1101 0010 0000 0010 0010
237 // after 0100 0101 0101 0101 0000 0000 0000 0010
239 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
240 // My assumption: RegB = (RegB & 01010111b)
241 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
242 // clear clock-halt bit, disable alarm bit
243 outb_cmos(val8 & 0x57, CMOS_STATUS_B); // disable alarm bit
245 regs->al = val8; // val last written to Reg B
251 handle_1aXX(struct bregs *regs)
256 // INT 1Ah Time-of-day Service Entry Point
258 handle_1a(struct bregs *regs)
262 case 0x00: handle_1a00(regs); break;
263 case 0x01: handle_1a01(regs); break;
264 case 0x02: handle_1a02(regs); break;
265 case 0x03: handle_1a03(regs); break;
266 case 0x04: handle_1a04(regs); break;
267 case 0x05: handle_1a05(regs); break;
268 case 0x06: handle_1a06(regs); break;
269 case 0x07: handle_1a07(regs); break;
270 case 0xb1: handle_1ab1(regs); break;
271 default: handle_1aXX(regs); break;
282 // INT 08h System Timer ISR Entry Point
291 u32 counter = GET_BDA(timer_counter);
293 // compare to one days worth of timer ticks at 18.2 hz
294 if (counter >= 0x001800B0) {
295 // there has been a midnight rollover at this point
297 SET_BDA(timer_rollover, GET_BDA(timer_rollover) + 1);
300 SET_BDA(timer_counter, counter);
302 // chain to user timer tick INT #0x1c
304 memset(&br, 0, sizeof(br));
305 call16_int(0x1c, &br);
312 // Set Interval requested.
314 handle_158300(struct bregs *regs)
316 if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING) {
317 // Interval already set.
318 DEBUGF("int15: Func 83h, failed, already waiting.\n" );
319 set_code_fail(regs, RET_EUNSUPPORTED);
321 // Interval not already set.
322 SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
323 u32 v = (regs->es << 16) | regs->bx;
324 SET_BDA(ptr_user_wait_complete_flag, v);
325 v = (regs->dx << 16) | regs->cx;
326 SET_BDA(user_wait_timeout, v);
328 // Unmask IRQ8 so INT70 will get through.
329 u8 irqDisable = inb(PORT_PIC2_DATA);
330 outb(irqDisable & ~PIC2_IRQ8, PORT_PIC2_DATA);
331 // Turn on the Periodic Interrupt timer
332 u8 bRegister = inb_cmos(CMOS_STATUS_B);
333 outb_cmos(CMOS_STATUS_B, bRegister | CSB_EN_ALARM_IRQ);
335 set_success(regs); // XXX - no set ah?
338 // Clear interval requested
340 handle_158301(struct bregs *regs)
342 SET_BDA(rtc_wait_flag, 0); // Clear status byte
343 // Turn off the Periodic Interrupt timer
344 u8 bRegister = inb_cmos(CMOS_STATUS_B);
345 outb_cmos(CMOS_STATUS_B, bRegister & ~CSB_EN_ALARM_IRQ);
346 set_success(regs); // XXX - no set ah?
350 handle_1583XX(struct bregs *regs)
352 set_code_fail(regs, RET_EUNSUPPORTED);
357 handle_1583(struct bregs *regs)
360 case 0x00: handle_158300(regs); break;
361 case 0x01: handle_158301(regs); break;
362 default: handle_1583XX(regs); break;
366 // int70h: IRQ8 - CMOS RTC
372 // Check which modes are enabled and have occurred.
373 u8 registerB = inb_cmos(CMOS_STATUS_B);
374 u8 registerC = inb_cmos(CMOS_STATUS_C);
376 if (!(registerB & 0x60))
378 if (registerC & 0x20) {
379 // Handle Alarm Interrupt.
381 memset(&br, 0, sizeof(br));
382 call16_int(0x4a, &br);
385 if (!(registerC & 0x40))
388 // Handle Periodic Interrupt.
390 if (!GET_BDA(rtc_wait_flag))
393 // Wait Interval (Int 15, AH=83) active.
394 u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds.
397 u32 segoff = GET_BDA(ptr_user_wait_complete_flag);
398 u16 segment = segoff >> 16;
399 u16 offset = segoff & 0xffff;
400 // Turn off status byte.
401 SET_BDA(rtc_wait_flag, 0);
402 // Clear the Periodic Interrupt.
403 outb_cmos(registerB & 0x37, CMOS_STATUS_B);
404 // Write to specified flag byte.
405 u8 oldval = GET_FARVAR(segment, *(u8*)(offset+0));
406 SET_FARVAR(segment, *(u8*)(offset+0), oldval | 0x80);
410 SET_BDA(user_wait_timeout, time);