1 // 16bit code to handle system clocks.
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2002 MandrakeSoft S.A.
6 // This file may be distributed under the terms of the GNU GPLv3 license.
8 #include "biosvar.h" // SET_BDA
9 #include "util.h" // debug_enter
10 #include "disk.h" // floppy_tick
11 #include "cmos.h" // inb_cmos
12 #include "pic.h" // eoi_pic1
13 #include "bregs.h" // struct bregs
16 #define RTC_A_UIP 0x80
17 #define RTC_B_SET 0x80
18 #define RTC_B_PIE 0x40
19 #define RTC_B_AIE 0x20
20 #define RTC_B_UIE 0x10
23 /****************************************************************
25 ****************************************************************/
30 // timer0: binary count, 16bit count, mode 2
31 outb(0x34, PORT_PIT_MODE);
32 // maximum count of 0000H = 18.2Hz
33 outb(0x0, PORT_PIT_COUNTER0);
34 outb(0x0, PORT_PIT_COUNTER0);
40 return (val & 0xf) + ((val >> 4) * 10);
46 dprintf(3, "init timer\n");
49 u32 seconds = bcd2bin(inb_cmos(CMOS_RTC_SECONDS));
50 u32 ticks = (seconds * 18206507) / 1000000;
51 u32 minutes = bcd2bin(inb_cmos(CMOS_RTC_MINUTES));
52 ticks += (minutes * 10923904) / 10000;
53 u32 hours = bcd2bin(inb_cmos(CMOS_RTC_HOURS));
54 ticks += (hours * 65543427) / 1000;
55 SET_BDA(timer_counter, ticks);
56 SET_BDA(timer_rollover, 0);
58 enable_hwirq(0, entry_08);
59 enable_hwirq(8, entry_70);
65 outb_cmos(0x26, CMOS_STATUS_A);
66 outb_cmos(0x02, CMOS_STATUS_B);
67 inb_cmos(CMOS_STATUS_C);
68 inb_cmos(CMOS_STATUS_D);
72 /****************************************************************
73 * Standard clock functions
74 ****************************************************************/
79 // This function checks to see if the update-in-progress bit
80 // is set in CMOS Status Register A. If not, it returns 0.
81 // If it is set, it tries to wait until there is a transition
82 // to 0, and will return 0 if such a transition occurs. A 1
83 // is returned only after timing out. The maximum period
84 // that this bit should be set is constrained to 244useconds.
85 // The count I use below guarantees coverage or more than
86 // this time, with any reasonable IPS setting.
89 while (--count != 0) {
90 if ( (inb_cmos(CMOS_STATUS_A) & 0x80) == 0 )
93 return 1; // update-in-progress never transitioned to 0
96 // get current clock count
98 handle_1a00(struct bregs *regs)
100 u32 ticks = GET_BDA(timer_counter);
101 regs->cx = ticks >> 16;
103 regs->al = GET_BDA(timer_rollover);
104 SET_BDA(timer_rollover, 0); // reset flag
108 // Set Current Clock Count
110 handle_1a01(struct bregs *regs)
112 u32 ticks = (regs->cx << 16) | regs->dx;
113 SET_BDA(timer_counter, ticks);
114 SET_BDA(timer_rollover, 0); // reset flag
121 handle_1a02(struct bregs *regs)
123 if (rtc_updating()) {
128 regs->dh = inb_cmos(CMOS_RTC_SECONDS);
129 regs->cl = inb_cmos(CMOS_RTC_MINUTES);
130 regs->ch = inb_cmos(CMOS_RTC_HOURS);
131 regs->dl = inb_cmos(CMOS_STATUS_B) & 0x01;
139 handle_1a03(struct bregs *regs)
141 // Using a debugger, I notice the following masking/setting
142 // of bits in Status Register B, by setting Reg B to
143 // a few values and getting its value after INT 1A was called.
146 // before 1111 1101 0111 1101 0000 0000
147 // after 0110 0010 0110 0010 0000 0010
149 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
150 // My assumption: RegB = ((RegB & 01100000b) | 00000010b)
151 if (rtc_updating()) {
153 // fall through as if an update were not in progress
155 outb_cmos(regs->dh, CMOS_RTC_SECONDS);
156 outb_cmos(regs->cl, CMOS_RTC_MINUTES);
157 outb_cmos(regs->ch, CMOS_RTC_HOURS);
158 // Set Daylight Savings time enabled bit to requested value
159 u8 val8 = (inb_cmos(CMOS_STATUS_B) & 0x60) | 0x02 | (regs->dl & 0x01);
160 outb_cmos(val8, CMOS_STATUS_B);
162 regs->al = val8; // val last written to Reg B
168 handle_1a04(struct bregs *regs)
171 if (rtc_updating()) {
175 regs->cl = inb_cmos(CMOS_RTC_YEAR);
176 regs->dh = inb_cmos(CMOS_RTC_MONTH);
177 regs->dl = inb_cmos(CMOS_RTC_DAY_MONTH);
178 regs->ch = inb_cmos(CMOS_CENTURY);
185 handle_1a05(struct bregs *regs)
187 // Using a debugger, I notice the following masking/setting
188 // of bits in Status Register B, by setting Reg B to
189 // a few values and getting its value after INT 1A was called.
191 // try#1 try#2 try#3 try#4
192 // before 1111 1101 0111 1101 0000 0010 0000 0000
193 // after 0110 1101 0111 1101 0000 0010 0000 0000
195 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
196 // My assumption: RegB = (RegB & 01111111b)
197 if (rtc_updating()) {
202 outb_cmos(regs->cl, CMOS_RTC_YEAR);
203 outb_cmos(regs->dh, CMOS_RTC_MONTH);
204 outb_cmos(regs->dl, CMOS_RTC_DAY_MONTH);
205 outb_cmos(regs->ch, CMOS_CENTURY);
206 // clear halt-clock bit
207 u8 val8 = inb_cmos(CMOS_STATUS_B) & ~RTC_B_SET;
208 outb_cmos(val8, CMOS_STATUS_B);
210 regs->al = val8; // AL = val last written to Reg B
214 // Set Alarm Time in CMOS
216 handle_1a06(struct bregs *regs)
218 // Using a debugger, I notice the following masking/setting
219 // of bits in Status Register B, by setting Reg B to
220 // a few values and getting its value after INT 1A was called.
223 // before 1101 1111 0101 1111 0000 0000
224 // after 0110 1111 0111 1111 0010 0000
226 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
227 // My assumption: RegB = ((RegB & 01111111b) | 00100000b)
228 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
231 // Alarm interrupt enabled already
235 if (rtc_updating()) {
237 // fall through as if an update were not in progress
239 outb_cmos(regs->dh, CMOS_RTC_SECONDS_ALARM);
240 outb_cmos(regs->cl, CMOS_RTC_MINUTES_ALARM);
241 outb_cmos(regs->ch, CMOS_RTC_HOURS_ALARM);
242 // enable Status Reg B alarm bit, clear halt clock bit
243 outb_cmos((val8 & ~RTC_B_SET) | RTC_B_AIE, CMOS_STATUS_B);
249 handle_1a07(struct bregs *regs)
251 // Using a debugger, I notice the following masking/setting
252 // of bits in Status Register B, by setting Reg B to
253 // a few values and getting its value after INT 1A was called.
255 // try#1 try#2 try#3 try#4
256 // before 1111 1101 0111 1101 0010 0000 0010 0010
257 // after 0100 0101 0101 0101 0000 0000 0000 0010
259 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
260 // My assumption: RegB = (RegB & 01010111b)
261 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
262 // clear clock-halt bit, disable alarm bit
263 outb_cmos(val8 & ~(RTC_B_SET|RTC_B_AIE), CMOS_STATUS_B);
265 regs->al = val8; // val last written to Reg B
271 handle_1aXX(struct bregs *regs)
276 // INT 1Ah Time-of-day Service Entry Point
278 handle_1a(struct bregs *regs)
280 debug_enter(regs, DEBUG_HDL_1a);
282 case 0x00: handle_1a00(regs); break;
283 case 0x01: handle_1a01(regs); break;
284 case 0x02: handle_1a02(regs); break;
285 case 0x03: handle_1a03(regs); break;
286 case 0x04: handle_1a04(regs); break;
287 case 0x05: handle_1a05(regs); break;
288 case 0x06: handle_1a06(regs); break;
289 case 0x07: handle_1a07(regs); break;
290 case 0xb1: handle_1ab1(regs); break;
291 default: handle_1aXX(regs); break;
299 debug_isr(DEBUG_ISR_1c);
302 // INT 08h System Timer ISR Entry Point
306 debug_isr(DEBUG_ISR_08);
311 u32 counter = GET_BDA(timer_counter);
313 // compare to one days worth of timer ticks at 18.2 hz
314 if (counter >= 0x001800B0) {
315 // there has been a midnight rollover at this point
317 SET_BDA(timer_rollover, GET_BDA(timer_rollover) + 1);
320 SET_BDA(timer_counter, counter);
322 // chain to user timer tick INT #0x1c
324 memset(&br, 0, sizeof(br));
325 call16_int(0x1c, &br);
333 /****************************************************************
335 ****************************************************************/
338 set_usertimer(u32 usecs, u16 seg, u16 offset)
340 if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING)
343 // Interval not already set.
344 SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
345 SET_BDA(ptr_user_wait_complete_flag, (seg << 16) | offset);
346 SET_BDA(user_wait_timeout, usecs);
348 // Turn on the Periodic Interrupt timer
349 u8 bRegister = inb_cmos(CMOS_STATUS_B);
350 outb_cmos(bRegister | RTC_B_PIE, CMOS_STATUS_B);
358 // Turn off status byte.
359 SET_BDA(rtc_wait_flag, 0);
360 // Clear the Periodic Interrupt.
361 u8 bRegister = inb_cmos(CMOS_STATUS_B);
362 outb_cmos(bRegister & ~RTC_B_PIE, CMOS_STATUS_B);
365 // Sleep for n microseconds.
370 // In 16bit mode, use the rtc to wait for the specified time.
372 int ret = set_usertimer(count, GET_SEG(SS), (u32)&statusflag);
381 // In 32bit mode, we need to call into 16bit mode to sleep.
383 memset(&br, 0, sizeof(br));
387 call16_int(0x15, &br);
394 #define RET_ECLOCKINUSE 0x83
396 // Wait for CX:DX microseconds
398 handle_1586(struct bregs *regs)
400 int ret = usleep((regs->cx << 16) | regs->dx);
402 set_code_fail(regs, RET_ECLOCKINUSE);
407 // Set Interval requested.
409 handle_158300(struct bregs *regs)
411 int ret = set_usertimer((regs->cx << 16) | regs->dx, regs->es, regs->bx);
413 // Interval already set.
414 set_code_fail(regs, RET_EUNSUPPORTED);
419 // Clear interval requested
421 handle_158301(struct bregs *regs)
428 handle_1583XX(struct bregs *regs)
430 set_code_fail(regs, RET_EUNSUPPORTED);
435 handle_1583(struct bregs *regs)
438 case 0x00: handle_158300(regs); break;
439 case 0x01: handle_158301(regs); break;
440 default: handle_1583XX(regs); break;
444 // int70h: IRQ8 - CMOS RTC
448 debug_isr(DEBUG_ISR_70);
450 // Check which modes are enabled and have occurred.
451 u8 registerB = inb_cmos(CMOS_STATUS_B);
452 u8 registerC = inb_cmos(CMOS_STATUS_C);
454 if (!(registerB & (RTC_B_PIE|RTC_B_AIE)))
456 if (registerC & 0x20) {
457 // Handle Alarm Interrupt.
459 memset(&br, 0, sizeof(br));
460 call16_int(0x4a, &br);
463 if (!(registerC & 0x40))
466 // Handle Periodic Interrupt.
468 if (!GET_BDA(rtc_wait_flag))
471 // Wait Interval (Int 15, AH=83) active.
472 u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds.
474 // Done waiting - write to specified flag byte.
475 u32 segoff = GET_BDA(ptr_user_wait_complete_flag);
476 u16 segment = segoff >> 16;
477 u16 offset = segoff & 0xffff;
478 u8 oldval = GET_FARVAR(segment, *(u8*)(offset+0));
479 SET_FARVAR(segment, *(u8*)(offset+0), oldval | 0x80);
485 SET_BDA(user_wait_timeout, time);