1 // 16bit code to handle system clocks.
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2002 MandrakeSoft S.A.
6 // This file may be distributed under the terms of the GNU GPLv3 license.
8 #include "biosvar.h" // struct bregs
9 #include "util.h" // debug_enter
10 #include "disk.h" // floppy_tick
11 #include "cmos.h" // inb_cmos
16 outb_cmos(0x26, CMOS_STATUS_A);
17 outb_cmos(0x02, CMOS_STATUS_B);
18 inb_cmos(CMOS_STATUS_C);
19 inb_cmos(CMOS_STATUS_D);
25 // This function checks to see if the update-in-progress bit
26 // is set in CMOS Status Register A. If not, it returns 0.
27 // If it is set, it tries to wait until there is a transition
28 // to 0, and will return 0 if such a transition occurs. A 1
29 // is returned only after timing out. The maximum period
30 // that this bit should be set is constrained to 244useconds.
31 // The count I use below guarantees coverage or more than
32 // this time, with any reasonable IPS setting.
35 while (--count != 0) {
36 if ( (inb_cmos(CMOS_STATUS_A) & 0x80) == 0 )
39 return 1; // update-in-progress never transitioned to 0
42 // get current clock count
44 handle_1a00(struct bregs *regs)
46 u32 ticks = GET_BDA(timer_counter);
47 regs->cx = ticks >> 16;
49 regs->al = GET_BDA(timer_rollover);
50 SET_BDA(timer_rollover, 0); // reset flag
54 // Set Current Clock Count
56 handle_1a01(struct bregs *regs)
58 u32 ticks = (regs->cx << 16) | regs->dx;
59 SET_BDA(timer_counter, ticks);
60 SET_BDA(timer_rollover, 0); // reset flag
67 handle_1a02(struct bregs *regs)
74 regs->dh = inb_cmos(CMOS_RTC_SECONDS);
75 regs->cl = inb_cmos(CMOS_RTC_MINUTES);
76 regs->ch = inb_cmos(CMOS_RTC_HOURS);
77 regs->dl = inb_cmos(CMOS_STATUS_B) & 0x01;
85 handle_1a03(struct bregs *regs)
87 // Using a debugger, I notice the following masking/setting
88 // of bits in Status Register B, by setting Reg B to
89 // a few values and getting its value after INT 1A was called.
92 // before 1111 1101 0111 1101 0000 0000
93 // after 0110 0010 0110 0010 0000 0010
95 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
96 // My assumption: RegB = ((RegB & 01100000b) | 00000010b)
99 // fall through as if an update were not in progress
101 outb_cmos(regs->dh, CMOS_RTC_SECONDS);
102 outb_cmos(regs->cl, CMOS_RTC_MINUTES);
103 outb_cmos(regs->ch, CMOS_RTC_HOURS);
104 // Set Daylight Savings time enabled bit to requested value
105 u8 val8 = (inb_cmos(CMOS_STATUS_B) & 0x60) | 0x02 | (regs->dl & 0x01);
106 outb_cmos(val8, CMOS_STATUS_B);
108 regs->al = val8; // val last written to Reg B
114 handle_1a04(struct bregs *regs)
117 if (rtc_updating()) {
121 regs->cl = inb_cmos(CMOS_RTC_YEAR);
122 regs->dh = inb_cmos(CMOS_RTC_MONTH);
123 regs->dl = inb_cmos(CMOS_RTC_DAY_MONTH);
124 regs->ch = inb_cmos(CMOS_CENTURY);
131 handle_1a05(struct bregs *regs)
133 // Using a debugger, I notice the following masking/setting
134 // of bits in Status Register B, by setting Reg B to
135 // a few values and getting its value after INT 1A was called.
137 // try#1 try#2 try#3 try#4
138 // before 1111 1101 0111 1101 0000 0010 0000 0000
139 // after 0110 1101 0111 1101 0000 0010 0000 0000
141 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
142 // My assumption: RegB = (RegB & 01111111b)
143 if (rtc_updating()) {
148 outb_cmos(regs->cl, CMOS_RTC_YEAR);
149 outb_cmos(regs->dh, CMOS_RTC_MONTH);
150 outb_cmos(regs->dl, CMOS_RTC_DAY_MONTH);
151 outb_cmos(regs->ch, CMOS_CENTURY);
152 u8 val8 = inb_cmos(CMOS_STATUS_B) & 0x7f; // clear halt-clock bit
153 outb_cmos(val8, CMOS_STATUS_B);
155 regs->al = val8; // AL = val last written to Reg B
159 // Set Alarm Time in CMOS
161 handle_1a06(struct bregs *regs)
163 // Using a debugger, I notice the following masking/setting
164 // of bits in Status Register B, by setting Reg B to
165 // a few values and getting its value after INT 1A was called.
168 // before 1101 1111 0101 1111 0000 0000
169 // after 0110 1111 0111 1111 0010 0000
171 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
172 // My assumption: RegB = ((RegB & 01111111b) | 00100000b)
173 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
176 // Alarm interrupt enabled already
180 if (rtc_updating()) {
182 // fall through as if an update were not in progress
184 outb_cmos(regs->dh, CMOS_RTC_SECONDS_ALARM);
185 outb_cmos(regs->cl, CMOS_RTC_MINUTES_ALARM);
186 outb_cmos(regs->ch, CMOS_RTC_HOURS_ALARM);
187 outb(inb(PORT_PIC2_DATA) & ~PIC2_IRQ8, PORT_PIC2_DATA); // enable IRQ 8
188 // enable Status Reg B alarm bit, clear halt clock bit
189 outb_cmos((val8 & 0x7f) | 0x20, CMOS_STATUS_B);
195 handle_1a07(struct bregs *regs)
197 // Using a debugger, I notice the following masking/setting
198 // of bits in Status Register B, by setting Reg B to
199 // a few values and getting its value after INT 1A was called.
201 // try#1 try#2 try#3 try#4
202 // before 1111 1101 0111 1101 0010 0000 0010 0010
203 // after 0100 0101 0101 0101 0000 0000 0000 0010
205 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
206 // My assumption: RegB = (RegB & 01010111b)
207 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
208 // clear clock-halt bit, disable alarm bit
209 outb_cmos(val8 & 0x57, CMOS_STATUS_B); // disable alarm bit
211 regs->al = val8; // val last written to Reg B
216 handle_1ab1(struct bregs *regs)
218 // XXX - pcibios stuff
224 handle_1aXX(struct bregs *regs)
229 // INT 1Ah Time-of-day Service Entry Point
231 handle_1a(struct bregs *regs)
235 case 0x00: handle_1a00(regs); break;
236 case 0x01: handle_1a01(regs); break;
237 case 0x02: handle_1a02(regs); break;
238 case 0x03: handle_1a03(regs); break;
239 case 0x04: handle_1a04(regs); break;
240 case 0x05: handle_1a05(regs); break;
241 case 0x06: handle_1a06(regs); break;
242 case 0x07: handle_1a07(regs); break;
243 case 0xb1: handle_1ab1(regs); break;
244 default: handle_1aXX(regs); break;
251 handle_1c(struct bregs *regs)
256 // INT 08h System Timer ISR Entry Point
258 handle_08(struct bregs *regs)
260 // debug_enter(regs);
264 u32 counter = GET_BDA(timer_counter);
266 // compare to one days worth of timer ticks at 18.2 hz
267 if (counter >= 0x001800B0) {
268 // there has been a midnight rollover at this point
270 SET_BDA(timer_rollover, GET_BDA(timer_rollover) + 1);
273 SET_BDA(timer_counter, counter);
275 // chain to user timer tick INT #0x1c
277 memset(&br, 0, sizeof(br));
278 call16_int(0x1c, &br);
283 // Set Interval requested.
285 handle_158300(struct bregs *regs)
287 if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING) {
288 // Interval already set.
289 DEBUGF("int15: Func 83h, failed, already waiting.\n" );
290 handle_ret(regs, RET_EUNSUPPORTED);
292 // Interval not already set.
293 SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
294 u32 v = (regs->es << 16) | regs->bx;
295 SET_BDA(ptr_user_wait_complete_flag, v);
296 v = (regs->dx << 16) | regs->cx;
297 SET_BDA(user_wait_timeout, v);
299 // Unmask IRQ8 so INT70 will get through.
300 u8 irqDisable = inb(PORT_PIC2_DATA);
301 outb(irqDisable & ~PIC2_IRQ8, PORT_PIC2_DATA);
302 // Turn on the Periodic Interrupt timer
303 u8 bRegister = inb_cmos(CMOS_STATUS_B);
304 outb_cmos(CMOS_STATUS_B, bRegister | CSB_EN_ALARM_IRQ);
306 set_cf(regs, 0); // XXX - no set ah?
309 // Clear interval requested
311 handle_158301(struct bregs *regs)
313 SET_BDA(rtc_wait_flag, 0); // Clear status byte
314 // Turn off the Periodic Interrupt timer
315 u8 bRegister = inb_cmos(CMOS_STATUS_B);
316 outb_cmos(CMOS_STATUS_B, bRegister & ~CSB_EN_ALARM_IRQ);
317 set_cf(regs, 0); // XXX - no set ah?
321 handle_1583XX(struct bregs *regs)
324 handle_ret(regs, RET_EUNSUPPORTED);
328 handle_1583(struct bregs *regs)
331 case 0x00: handle_158300(regs); break;
332 case 0x01: handle_158301(regs); break;
333 default: handle_1583XX(regs); break;
337 // int70h: IRQ8 - CMOS RTC
339 handle_70(struct bregs *regs)
343 // Check which modes are enabled and have occurred.
344 u8 registerB = inb_cmos(CMOS_STATUS_B);
345 u8 registerC = inb_cmos(CMOS_STATUS_C);
347 if (!(registerB & 0x60))
349 if (registerC & 0x20) {
350 // Handle Alarm Interrupt.
352 memset(&br, 0, sizeof(br));
353 call16_int(0x4a, &br);
355 if (!(registerC & 0x40))
358 // Handle Periodic Interrupt.
360 if (!GET_BDA(rtc_wait_flag))
363 // Wait Interval (Int 15, AH=83) active.
364 u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds.
367 u32 segoff = GET_BDA(ptr_user_wait_complete_flag);
368 u16 segment = segoff >> 16;
369 u16 offset = segoff & 0xffff;
370 // Turn off status byte.
371 SET_BDA(rtc_wait_flag, 0);
372 // Clear the Periodic Interrupt.
373 outb_cmos(registerB & 0x37, CMOS_STATUS_B);
374 // Write to specified flag byte.
375 u8 oldval = GET_FARVAR(segment, *(u8*)(offset+0));
376 SET_FARVAR(segment, *(u8*)(offset+0), oldval | 0x80);
380 SET_BDA(user_wait_timeout, time);