1 // 16bit code to handle system clocks.
3 // Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2002 MandrakeSoft S.A.
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "biosvar.h" // SET_BDA
9 #include "util.h" // debug_enter
10 #include "disk.h" // floppy_tick
11 #include "cmos.h" // inb_cmos
12 #include "pic.h" // eoi_pic1
13 #include "bregs.h" // struct bregs
14 #include "biosvar.h" // GET_GLOBAL
15 #include "usb-hid.h" // usb_check_event
18 #define RTC_A_UIP 0x80
20 #define RTC_B_SET 0x80
21 #define RTC_B_PIE 0x40
22 #define RTC_B_AIE 0x20
23 #define RTC_B_UIE 0x10
24 #define RTC_B_BIN 0x04
25 #define RTC_B_24HR 0x02
26 #define RTC_B_DSE 0x01
29 // Bits for PORT_PS2_CTRLB
30 #define PPCB_T2GATE (1<<0)
31 #define PPCB_SPKR (1<<1)
32 #define PPCB_T2OUT (1<<5)
34 // Bits for PORT_PIT_MODE
35 #define PM_SEL_TIMER0 (0<<6)
36 #define PM_SEL_TIMER1 (1<<6)
37 #define PM_SEL_TIMER2 (2<<6)
38 #define PM_SEL_READBACK (3<<6)
39 #define PM_ACCESS_LATCH (0<<4)
40 #define PM_ACCESS_LOBYTE (1<<4)
41 #define PM_ACCESS_HIBYTE (2<<4)
42 #define PM_ACCESS_WORD (3<<4)
43 #define PM_MODE0 (0<<1)
44 #define PM_MODE1 (1<<1)
45 #define PM_MODE2 (2<<1)
46 #define PM_MODE3 (3<<1)
47 #define PM_MODE4 (4<<1)
48 #define PM_MODE5 (5<<1)
49 #define PM_CNT_BINARY (0<<0)
50 #define PM_CNT_BCD (1<<0)
51 #define PM_READ_COUNTER0 (1<<1)
52 #define PM_READ_COUNTER1 (1<<2)
53 #define PM_READ_COUNTER2 (1<<3)
54 #define PM_READ_STATUSVALUE (0<<4)
55 #define PM_READ_VALUE (1<<4)
56 #define PM_READ_STATUS (2<<4)
59 /****************************************************************
61 ****************************************************************/
63 #define CALIBRATE_COUNT 0x800 // Approx 1.7ms
65 u32 cpu_khz VAR16VISIBLE;
66 u8 no_tsc VAR16VISIBLE;
71 u32 eax, ebx, ecx, edx, cpuid_features = 0;
72 cpuid(0, &eax, &ebx, &ecx, &edx);
74 cpuid(1, &eax, &ebx, &ecx, &cpuid_features);
76 if (!(cpuid_features & CPUID_TSC)) {
77 SET_GLOBAL(no_tsc, 1);
78 SET_GLOBAL(cpu_khz, PIT_TICK_RATE / 1000);
79 dprintf(3, "386/486 class CPU. Using TSC emulation\n");
85 u8 orig = inb(PORT_PS2_CTRLB);
86 outb((orig & ~PPCB_SPKR) | PPCB_T2GATE, PORT_PS2_CTRLB);
87 /* binary, mode 0, LSB/MSB, Ch 2 */
88 outb(PM_SEL_TIMER2|PM_ACCESS_WORD|PM_MODE0|PM_CNT_BINARY, PORT_PIT_MODE);
90 outb(CALIBRATE_COUNT & 0xFF, PORT_PIT_COUNTER2);
92 outb(CALIBRATE_COUNT >> 8, PORT_PIT_COUNTER2);
94 u64 start = rdtscll();
95 while ((inb(PORT_PS2_CTRLB) & PPCB_T2OUT) == 0)
99 // Restore PORT_PS2_CTRLB
100 outb(orig, PORT_PS2_CTRLB);
102 // Store calibrated cpu khz.
103 u64 diff = end - start;
104 dprintf(6, "tsc calibrate start=%u end=%u diff=%u\n"
105 , (u32)start, (u32)end, (u32)diff);
106 u32 hz = diff * PIT_TICK_RATE / CALIBRATE_COUNT;
107 SET_GLOBAL(cpu_khz, hz / 1000);
109 u32 hz = 800 * 1000000;
110 SET_GLOBAL(cpu_khz, hz / 1000);
113 dprintf(1, "CPU Mhz=%u\n", hz / 1000000);
120 u16 ebda_seg = get_ebda_seg();
122 /* read timer 0 current count */
123 ret = GET_EBDA2(ebda_seg, tsc_8254);
124 /* readback mode has slightly shifted registers, works on all 8254, readback PIT0 latch */
125 outb(PM_SEL_READBACK | PM_READ_VALUE | PM_READ_COUNTER0, PORT_PIT_MODE);
126 cnt = (inb(PORT_PIT_COUNTER0) | (inb(PORT_PIT_COUNTER0) << 8));
127 d = GET_EBDA2(ebda_seg, last_tsc_8254) - cnt;
128 /* Determine the ticks count from last invocation of this function */
129 ret += (d > 0) ? d : (PIT_TICK_INTERVAL + d);
130 SET_EBDA2(ebda_seg, last_tsc_8254, cnt);
131 SET_EBDA2(ebda_seg, tsc_8254, ret);
138 if (unlikely(GET_GLOBAL(no_tsc)))
139 return emulate_tsc();
146 return (s64)(get_tsc() - end) > 0;
152 u64 start = get_tsc();
153 u64 end = start + diff;
154 while (!check_tsc(end))
161 u64 start = get_tsc();
162 u64 end = start + diff;
163 while (!check_tsc(end))
167 void ndelay(u32 count) {
168 tscdelay(count * GET_GLOBAL(cpu_khz) / 1000000);
170 void udelay(u32 count) {
171 tscdelay(count * GET_GLOBAL(cpu_khz) / 1000);
173 void mdelay(u32 count) {
174 tscdelay(count * GET_GLOBAL(cpu_khz));
177 void nsleep(u32 count) {
178 tscsleep(count * GET_GLOBAL(cpu_khz) / 1000000);
180 void usleep(u32 count) {
181 tscsleep(count * GET_GLOBAL(cpu_khz) / 1000);
183 void msleep(u32 count) {
184 tscsleep(count * GET_GLOBAL(cpu_khz));
187 // Return the TSC value that is 'msecs' time in the future.
189 calc_future_tsc(u32 msecs)
191 u32 khz = GET_GLOBAL(cpu_khz);
192 return get_tsc() + ((u64)khz * msecs);
195 calc_future_tsc_usec(u32 usecs)
197 u32 khz = GET_GLOBAL(cpu_khz);
198 return get_tsc() + ((u64)(khz/1000) * usecs);
202 /****************************************************************
204 ****************************************************************/
209 // This function checks to see if the update-in-progress bit
210 // is set in CMOS Status Register A. If not, it returns 0.
211 // If it is set, it tries to wait until there is a transition
212 // to 0, and will return 0 if such a transition occurs. A -1
213 // is returned only after timing out. The maximum period
214 // that this bit should be set is constrained to (1984+244)
215 // useconds, but we wait for longer just to be sure.
217 if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
219 u64 end = calc_future_tsc(15);
221 if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
224 // update-in-progress never transitioned to 0
233 // timer0: binary count, 16bit count, mode 2
234 outb(PM_SEL_TIMER0|PM_ACCESS_WORD|PM_MODE2|PM_CNT_BINARY, PORT_PIT_MODE);
235 // maximum count of 0000H = 18.2Hz
236 outb(0x0, PORT_PIT_COUNTER0);
237 outb(0x0, PORT_PIT_COUNTER0);
243 outb_cmos(0x26, CMOS_STATUS_A); // 32,768Khz src, 976.5625us updates
244 u8 regB = inb_cmos(CMOS_STATUS_B);
245 outb_cmos((regB & RTC_B_DSE) | RTC_B_24HR, CMOS_STATUS_B);
246 inb_cmos(CMOS_STATUS_C);
247 inb_cmos(CMOS_STATUS_D);
253 return (val & 0xf) + ((val >> 4) * 10);
259 dprintf(3, "init timer\n");
263 dprintf(3, "init timer: 01\n");
265 dprintf(3, "init timer: 02\n");
268 dprintf(3, "init timer: 03\n");
270 dprintf(3, "init timer: 04\n");
271 u32 seconds = bcd2bin(inb_cmos(CMOS_RTC_SECONDS));
272 dprintf(3, "init timer: 05\n");
273 u32 minutes = bcd2bin(inb_cmos(CMOS_RTC_MINUTES));
274 dprintf(3, "init timer: 06\n");
275 u32 hours = bcd2bin(inb_cmos(CMOS_RTC_HOURS));
276 dprintf(3, "init timer: 07\n");
277 u32 ticks = (hours * 60 + minutes) * 60 + seconds;
278 dprintf(3, "init timer: 08\n");
279 ticks = ((u64)ticks * PIT_TICK_RATE) / PIT_TICK_INTERVAL;
280 dprintf(3, "init timer: 09\n");
281 SET_BDA(timer_counter, ticks);
282 dprintf(3, "init timer: 10\n");
284 enable_hwirq(0, FUNC16(entry_08));
285 dprintf(3, "init timer: 11\n");
286 enable_hwirq(8, FUNC16(entry_70));
287 dprintf(3, "init timer: 12\n");
291 /****************************************************************
292 * Standard clock functions
293 ****************************************************************/
295 #define TICKS_PER_DAY (u32)((u64)60*60*24*PIT_TICK_RATE / PIT_TICK_INTERVAL)
297 // Calculate the timer value at 'count' number of full timer ticks in
300 calc_future_timer_ticks(u32 count)
302 return (GET_BDA(timer_counter) + count + 1) % TICKS_PER_DAY;
305 // Return the timer value that is 'msecs' time in the future.
307 calc_future_timer(u32 msecs)
310 return GET_BDA(timer_counter);
311 u32 kticks = DIV_ROUND_UP((u64)msecs * PIT_TICK_RATE, PIT_TICK_INTERVAL);
312 u32 ticks = DIV_ROUND_UP(kticks, 1000);
313 return calc_future_timer_ticks(ticks);
316 // Check if the given timer value has passed.
320 return (((GET_BDA(timer_counter) + TICKS_PER_DAY - end) % TICKS_PER_DAY)
321 < (TICKS_PER_DAY/2));
324 // get current clock count
326 handle_1a00(struct bregs *regs)
329 u32 ticks = GET_BDA(timer_counter);
330 regs->cx = ticks >> 16;
332 regs->al = GET_BDA(timer_rollover);
333 SET_BDA(timer_rollover, 0); // reset flag
337 // Set Current Clock Count
339 handle_1a01(struct bregs *regs)
341 u32 ticks = (regs->cx << 16) | regs->dx;
342 SET_BDA(timer_counter, ticks);
343 SET_BDA(timer_rollover, 0); // reset flag
344 // XXX - should use set_code_success()?
351 handle_1a02(struct bregs *regs)
353 if (rtc_updating()) {
358 regs->dh = inb_cmos(CMOS_RTC_SECONDS);
359 regs->cl = inb_cmos(CMOS_RTC_MINUTES);
360 regs->ch = inb_cmos(CMOS_RTC_HOURS);
361 regs->dl = inb_cmos(CMOS_STATUS_B) & RTC_B_DSE;
369 handle_1a03(struct bregs *regs)
371 // Using a debugger, I notice the following masking/setting
372 // of bits in Status Register B, by setting Reg B to
373 // a few values and getting its value after INT 1A was called.
376 // before 1111 1101 0111 1101 0000 0000
377 // after 0110 0010 0110 0010 0000 0010
379 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
380 // My assumption: RegB = ((RegB & 01100000b) | 00000010b)
381 if (rtc_updating()) {
383 // fall through as if an update were not in progress
385 outb_cmos(regs->dh, CMOS_RTC_SECONDS);
386 outb_cmos(regs->cl, CMOS_RTC_MINUTES);
387 outb_cmos(regs->ch, CMOS_RTC_HOURS);
388 // Set Daylight Savings time enabled bit to requested value
389 u8 val8 = ((inb_cmos(CMOS_STATUS_B) & (RTC_B_PIE|RTC_B_AIE))
390 | RTC_B_24HR | (regs->dl & RTC_B_DSE));
391 outb_cmos(val8, CMOS_STATUS_B);
393 regs->al = val8; // val last written to Reg B
399 handle_1a04(struct bregs *regs)
402 if (rtc_updating()) {
406 regs->cl = inb_cmos(CMOS_RTC_YEAR);
407 regs->dh = inb_cmos(CMOS_RTC_MONTH);
408 regs->dl = inb_cmos(CMOS_RTC_DAY_MONTH);
409 if (CONFIG_COREBOOT) {
415 regs->ch = inb_cmos(CMOS_CENTURY);
423 handle_1a05(struct bregs *regs)
425 // Using a debugger, I notice the following masking/setting
426 // of bits in Status Register B, by setting Reg B to
427 // a few values and getting its value after INT 1A was called.
429 // try#1 try#2 try#3 try#4
430 // before 1111 1101 0111 1101 0000 0010 0000 0000
431 // after 0110 1101 0111 1101 0000 0010 0000 0000
433 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
434 // My assumption: RegB = (RegB & 01111111b)
435 if (rtc_updating()) {
440 outb_cmos(regs->cl, CMOS_RTC_YEAR);
441 outb_cmos(regs->dh, CMOS_RTC_MONTH);
442 outb_cmos(regs->dl, CMOS_RTC_DAY_MONTH);
443 if (!CONFIG_COREBOOT)
444 outb_cmos(regs->ch, CMOS_CENTURY);
445 // clear halt-clock bit
446 u8 val8 = inb_cmos(CMOS_STATUS_B) & ~RTC_B_SET;
447 outb_cmos(val8, CMOS_STATUS_B);
449 regs->al = val8; // AL = val last written to Reg B
453 // Set Alarm Time in CMOS
455 handle_1a06(struct bregs *regs)
457 // Using a debugger, I notice the following masking/setting
458 // of bits in Status Register B, by setting Reg B to
459 // a few values and getting its value after INT 1A was called.
462 // before 1101 1111 0101 1111 0000 0000
463 // after 0110 1111 0111 1111 0010 0000
465 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
466 // My assumption: RegB = ((RegB & 01111111b) | 00100000b)
467 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
469 if (val8 & RTC_B_AIE) {
470 // Alarm interrupt enabled already
474 if (rtc_updating()) {
476 // fall through as if an update were not in progress
478 outb_cmos(regs->dh, CMOS_RTC_SECONDS_ALARM);
479 outb_cmos(regs->cl, CMOS_RTC_MINUTES_ALARM);
480 outb_cmos(regs->ch, CMOS_RTC_HOURS_ALARM);
481 // enable Status Reg B alarm bit, clear halt clock bit
482 outb_cmos((val8 & ~RTC_B_SET) | RTC_B_AIE, CMOS_STATUS_B);
488 handle_1a07(struct bregs *regs)
490 // Using a debugger, I notice the following masking/setting
491 // of bits in Status Register B, by setting Reg B to
492 // a few values and getting its value after INT 1A was called.
494 // try#1 try#2 try#3 try#4
495 // before 1111 1101 0111 1101 0010 0000 0010 0010
496 // after 0100 0101 0101 0101 0000 0000 0000 0010
498 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
499 // My assumption: RegB = (RegB & 01010111b)
500 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
501 // clear clock-halt bit, disable alarm bit
502 outb_cmos(val8 & ~(RTC_B_SET|RTC_B_AIE), CMOS_STATUS_B);
504 regs->al = val8; // val last written to Reg B
510 handle_1aXX(struct bregs *regs)
512 set_unimplemented(regs);
515 // INT 1Ah Time-of-day Service Entry Point
517 handle_1a(struct bregs *regs)
519 debug_enter(regs, DEBUG_HDL_1a);
521 case 0x00: handle_1a00(regs); break;
522 case 0x01: handle_1a01(regs); break;
523 case 0x02: handle_1a02(regs); break;
524 case 0x03: handle_1a03(regs); break;
525 case 0x04: handle_1a04(regs); break;
526 case 0x05: handle_1a05(regs); break;
527 case 0x06: handle_1a06(regs); break;
528 case 0x07: handle_1a07(regs); break;
529 case 0xb1: handle_1ab1(regs); break;
530 default: handle_1aXX(regs); break;
534 // INT 08h System Timer ISR Entry Point
538 debug_isr(DEBUG_ISR_08);
542 u32 counter = GET_BDA(timer_counter);
544 // compare to one days worth of timer ticks at 18.2 hz
545 if (counter >= TICKS_PER_DAY) {
546 // there has been a midnight rollover at this point
548 SET_BDA(timer_rollover, GET_BDA(timer_rollover) + 1);
551 SET_BDA(timer_counter, counter);
555 // chain to user timer tick INT #0x1c
557 call16_simpint(0x1c, &eax, &flags);
563 /****************************************************************
565 ****************************************************************/
570 u16 ebda_seg = get_ebda_seg();
571 int count = GET_EBDA2(ebda_seg, RTCusers);
572 SET_EBDA2(ebda_seg, RTCusers, count+1);
575 // Turn on the Periodic Interrupt timer
576 u8 bRegister = inb_cmos(CMOS_STATUS_B);
577 outb_cmos(bRegister | RTC_B_PIE, CMOS_STATUS_B);
583 u16 ebda_seg = get_ebda_seg();
584 int count = GET_EBDA2(ebda_seg, RTCusers);
585 SET_EBDA2(ebda_seg, RTCusers, count-1);
588 // Clear the Periodic Interrupt.
589 u8 bRegister = inb_cmos(CMOS_STATUS_B);
590 outb_cmos(bRegister & ~RTC_B_PIE, CMOS_STATUS_B);
594 set_usertimer(u32 usecs, u16 seg, u16 offset)
596 if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING)
599 // Interval not already set.
600 SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
601 SET_BDA(user_wait_complete_flag, SEGOFF(seg, offset));
602 SET_BDA(user_wait_timeout, usecs);
608 clear_usertimer(void)
610 if (!(GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING))
612 // Turn off status byte.
613 SET_BDA(rtc_wait_flag, 0);
617 #define RET_ECLOCKINUSE 0x83
619 // Wait for CX:DX microseconds
621 handle_1586(struct bregs *regs)
623 // Use the rtc to wait for the specified time.
625 u32 count = (regs->cx << 16) | regs->dx;
626 int ret = set_usertimer(count, GET_SEG(SS), (u32)&statusflag);
628 set_code_invalid(regs, RET_ECLOCKINUSE);
636 // Set Interval requested.
638 handle_158300(struct bregs *regs)
640 int ret = set_usertimer((regs->cx << 16) | regs->dx, regs->es, regs->bx);
642 // Interval already set.
643 set_code_invalid(regs, RET_EUNSUPPORTED);
648 // Clear interval requested
650 handle_158301(struct bregs *regs)
657 handle_1583XX(struct bregs *regs)
659 set_code_unimplemented(regs, RET_EUNSUPPORTED);
664 handle_1583(struct bregs *regs)
667 case 0x00: handle_158300(regs); break;
668 case 0x01: handle_158301(regs); break;
669 default: handle_1583XX(regs); break;
673 #define USEC_PER_RTC DIV_ROUND_CLOSEST(1000000, 1024)
675 // int70h: IRQ8 - CMOS RTC
679 debug_isr(DEBUG_ISR_70);
681 // Check which modes are enabled and have occurred.
682 u8 registerB = inb_cmos(CMOS_STATUS_B);
683 u8 registerC = inb_cmos(CMOS_STATUS_C);
685 if (!(registerB & (RTC_B_PIE|RTC_B_AIE)))
687 if (registerC & RTC_B_AIE) {
688 // Handle Alarm Interrupt.
690 call16_simpint(0x4a, &eax, &flags);
692 if (!(registerC & RTC_B_PIE))
695 // Handle Periodic Interrupt.
699 if (!GET_BDA(rtc_wait_flag))
702 // Wait Interval (Int 15, AH=83) active.
703 u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds.
704 if (time < USEC_PER_RTC) {
705 // Done waiting - write to specified flag byte.
706 struct segoff_s segoff = GET_BDA(user_wait_complete_flag);
707 u16 ptr_seg = segoff.seg;
708 u8 *ptr_far = (u8*)(segoff.offset+0);
709 u8 oldval = GET_FARVAR(ptr_seg, *ptr_far);
710 SET_FARVAR(ptr_seg, *ptr_far, oldval | 0x80);
715 time -= USEC_PER_RTC;
716 SET_BDA(user_wait_timeout, time);