1 // 16bit code to handle system clocks.
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2002 MandrakeSoft S.A.
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "biosvar.h" // SET_BDA
9 #include "util.h" // debug_enter
10 #include "disk.h" // floppy_tick
11 #include "cmos.h" // inb_cmos
12 #include "pic.h" // eoi_pic1
13 #include "bregs.h" // struct bregs
14 #include "biosvar.h" // GET_GLOBAL
17 #define RTC_A_UIP 0x80
18 #define RTC_B_SET 0x80
19 #define RTC_B_PIE 0x40
20 #define RTC_B_AIE 0x20
21 #define RTC_B_UIE 0x10
23 // Bits for PORT_PS2_CTRLB
24 #define PPCB_T2GATE (1<<0)
25 #define PPCB_SPKR (1<<1)
26 #define PPCB_T2OUT (1<<5)
28 // Bits for PORT_PIT_MODE
29 #define PM_SEL_TIMER0 (0<<6)
30 #define PM_SEL_TIMER1 (1<<6)
31 #define PM_SEL_TIMER2 (2<<6)
32 #define PM_SEL_READBACK (3<<6)
33 #define PM_ACCESS_LATCH (0<<4)
34 #define PM_ACCESS_LOBYTE (1<<4)
35 #define PM_ACCESS_HIBYTE (2<<4)
36 #define PM_ACCESS_WORD (3<<4)
37 #define PM_MODE0 (0<<1)
38 #define PM_MODE1 (1<<1)
39 #define PM_MODE2 (2<<1)
40 #define PM_MODE3 (3<<1)
41 #define PM_MODE4 (4<<1)
42 #define PM_MODE5 (5<<1)
43 #define PM_CNT_BINARY (0<<0)
44 #define PM_CNT_BCD (1<<0)
47 /****************************************************************
49 ****************************************************************/
51 #define PIT_TICK_RATE 1193182 // Underlying HZ of PIT
52 #define CALIBRATE_COUNT 0x800 // Approx 1.7ms
60 u8 orig = inb(PORT_PS2_CTRLB);
61 outb((orig & ~PPCB_SPKR) | PPCB_T2GATE, PORT_PS2_CTRLB);
62 /* binary, mode 0, LSB/MSB, Ch 2 */
63 outb(PM_SEL_TIMER2|PM_ACCESS_WORD|PM_MODE0|PM_CNT_BINARY, PORT_PIT_MODE);
65 outb(CALIBRATE_COUNT & 0xFF, PORT_PIT_COUNTER2);
67 outb(CALIBRATE_COUNT >> 8, PORT_PIT_COUNTER2);
69 u64 start = rdtscll();
70 while ((inb(PORT_PS2_CTRLB) & PPCB_T2OUT) == 0)
74 // Restore PORT_PS2_CTRLB
75 outb(orig, PORT_PS2_CTRLB);
77 // Store calibrated cpu khz.
78 u64 diff = end - start;
79 dprintf(6, "tsc calibrate start=%u end=%u diff=%u\n"
80 , (u32)start, (u32)end, (u32)diff);
81 u32 hz = diff * PIT_TICK_RATE / CALIBRATE_COUNT;
82 SET_GLOBAL(cpu_khz, hz / 1000);
84 dprintf(1, "CPU Mhz=%u\n", hz / 1000000);
90 u64 start = rdtscll();
91 u64 end = start + diff;
92 while (rdtscll() < end)
99 u32 khz = GET_GLOBAL(cpu_khz);
100 tscsleep(count * khz / 1000000);
105 u32 khz = GET_GLOBAL(cpu_khz);
106 tscsleep(count * khz / 1000);
111 u32 khz = GET_GLOBAL(cpu_khz);
112 tscsleep(count * khz);
115 // Return the TSC value that is 'msecs' time in the future.
117 calc_future_tsc(u32 msecs)
119 u32 khz = GET_GLOBAL(cpu_khz);
120 return rdtscll() + ((u64)khz * msecs);
124 /****************************************************************
126 ****************************************************************/
131 // This function checks to see if the update-in-progress bit
132 // is set in CMOS Status Register A. If not, it returns 0.
133 // If it is set, it tries to wait until there is a transition
134 // to 0, and will return 0 if such a transition occurs. A -1
135 // is returned only after timing out. The maximum period
136 // that this bit should be set is constrained to 244useconds, so
137 // we wait for 1 msec max.
139 if ((inb_cmos(CMOS_STATUS_A) & 0x80) == 0)
141 u64 end = calc_future_tsc(1);
143 if ((inb_cmos(CMOS_STATUS_A) & 0x80) == 0)
145 } while (rdtscll() <= end);
147 // update-in-progress never transitioned to 0
154 // timer0: binary count, 16bit count, mode 2
155 outb(PM_SEL_TIMER0|PM_ACCESS_WORD|PM_MODE2|PM_CNT_BINARY, PORT_PIT_MODE);
156 // maximum count of 0000H = 18.2Hz
157 outb(0x0, PORT_PIT_COUNTER0);
158 outb(0x0, PORT_PIT_COUNTER0);
164 return (val & 0xf) + ((val >> 4) * 10);
170 dprintf(3, "init timer\n");
175 u32 seconds = bcd2bin(inb_cmos(CMOS_RTC_SECONDS));
176 u32 ticks = (seconds * 18206507) / 1000000;
177 u32 minutes = bcd2bin(inb_cmos(CMOS_RTC_MINUTES));
178 ticks += (minutes * 10923904) / 10000;
179 u32 hours = bcd2bin(inb_cmos(CMOS_RTC_HOURS));
180 ticks += (hours * 65543427) / 1000;
181 SET_BDA(timer_counter, ticks);
182 SET_BDA(timer_rollover, 0);
184 enable_hwirq(0, entry_08);
185 enable_hwirq(8, entry_70);
191 outb_cmos(0x26, CMOS_STATUS_A);
192 outb_cmos(0x02, CMOS_STATUS_B);
193 inb_cmos(CMOS_STATUS_C);
194 inb_cmos(CMOS_STATUS_D);
198 /****************************************************************
199 * Standard clock functions
200 ****************************************************************/
202 // get current clock count
204 handle_1a00(struct bregs *regs)
206 u32 ticks = GET_BDA(timer_counter);
207 regs->cx = ticks >> 16;
209 regs->al = GET_BDA(timer_rollover);
210 SET_BDA(timer_rollover, 0); // reset flag
214 // Set Current Clock Count
216 handle_1a01(struct bregs *regs)
218 u32 ticks = (regs->cx << 16) | regs->dx;
219 SET_BDA(timer_counter, ticks);
220 SET_BDA(timer_rollover, 0); // reset flag
221 // XXX - should use set_code_success()?
228 handle_1a02(struct bregs *regs)
230 if (rtc_updating()) {
235 regs->dh = inb_cmos(CMOS_RTC_SECONDS);
236 regs->cl = inb_cmos(CMOS_RTC_MINUTES);
237 regs->ch = inb_cmos(CMOS_RTC_HOURS);
238 regs->dl = inb_cmos(CMOS_STATUS_B) & 0x01;
246 handle_1a03(struct bregs *regs)
248 // Using a debugger, I notice the following masking/setting
249 // of bits in Status Register B, by setting Reg B to
250 // a few values and getting its value after INT 1A was called.
253 // before 1111 1101 0111 1101 0000 0000
254 // after 0110 0010 0110 0010 0000 0010
256 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
257 // My assumption: RegB = ((RegB & 01100000b) | 00000010b)
258 if (rtc_updating()) {
260 // fall through as if an update were not in progress
262 outb_cmos(regs->dh, CMOS_RTC_SECONDS);
263 outb_cmos(regs->cl, CMOS_RTC_MINUTES);
264 outb_cmos(regs->ch, CMOS_RTC_HOURS);
265 // Set Daylight Savings time enabled bit to requested value
266 u8 val8 = (inb_cmos(CMOS_STATUS_B) & 0x60) | 0x02 | (regs->dl & 0x01);
267 outb_cmos(val8, CMOS_STATUS_B);
269 regs->al = val8; // val last written to Reg B
275 handle_1a04(struct bregs *regs)
278 if (rtc_updating()) {
282 regs->cl = inb_cmos(CMOS_RTC_YEAR);
283 regs->dh = inb_cmos(CMOS_RTC_MONTH);
284 regs->dl = inb_cmos(CMOS_RTC_DAY_MONTH);
285 regs->ch = inb_cmos(CMOS_CENTURY);
292 handle_1a05(struct bregs *regs)
294 // Using a debugger, I notice the following masking/setting
295 // of bits in Status Register B, by setting Reg B to
296 // a few values and getting its value after INT 1A was called.
298 // try#1 try#2 try#3 try#4
299 // before 1111 1101 0111 1101 0000 0010 0000 0000
300 // after 0110 1101 0111 1101 0000 0010 0000 0000
302 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
303 // My assumption: RegB = (RegB & 01111111b)
304 if (rtc_updating()) {
309 outb_cmos(regs->cl, CMOS_RTC_YEAR);
310 outb_cmos(regs->dh, CMOS_RTC_MONTH);
311 outb_cmos(regs->dl, CMOS_RTC_DAY_MONTH);
312 outb_cmos(regs->ch, CMOS_CENTURY);
313 // clear halt-clock bit
314 u8 val8 = inb_cmos(CMOS_STATUS_B) & ~RTC_B_SET;
315 outb_cmos(val8, CMOS_STATUS_B);
317 regs->al = val8; // AL = val last written to Reg B
321 // Set Alarm Time in CMOS
323 handle_1a06(struct bregs *regs)
325 // Using a debugger, I notice the following masking/setting
326 // of bits in Status Register B, by setting Reg B to
327 // a few values and getting its value after INT 1A was called.
330 // before 1101 1111 0101 1111 0000 0000
331 // after 0110 1111 0111 1111 0010 0000
333 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
334 // My assumption: RegB = ((RegB & 01111111b) | 00100000b)
335 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
338 // Alarm interrupt enabled already
342 if (rtc_updating()) {
344 // fall through as if an update were not in progress
346 outb_cmos(regs->dh, CMOS_RTC_SECONDS_ALARM);
347 outb_cmos(regs->cl, CMOS_RTC_MINUTES_ALARM);
348 outb_cmos(regs->ch, CMOS_RTC_HOURS_ALARM);
349 // enable Status Reg B alarm bit, clear halt clock bit
350 outb_cmos((val8 & ~RTC_B_SET) | RTC_B_AIE, CMOS_STATUS_B);
356 handle_1a07(struct bregs *regs)
358 // Using a debugger, I notice the following masking/setting
359 // of bits in Status Register B, by setting Reg B to
360 // a few values and getting its value after INT 1A was called.
362 // try#1 try#2 try#3 try#4
363 // before 1111 1101 0111 1101 0010 0000 0010 0010
364 // after 0100 0101 0101 0101 0000 0000 0000 0010
366 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
367 // My assumption: RegB = (RegB & 01010111b)
368 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
369 // clear clock-halt bit, disable alarm bit
370 outb_cmos(val8 & ~(RTC_B_SET|RTC_B_AIE), CMOS_STATUS_B);
372 regs->al = val8; // val last written to Reg B
378 handle_1aXX(struct bregs *regs)
383 // INT 1Ah Time-of-day Service Entry Point
385 handle_1a(struct bregs *regs)
387 debug_enter(regs, DEBUG_HDL_1a);
389 case 0x00: handle_1a00(regs); break;
390 case 0x01: handle_1a01(regs); break;
391 case 0x02: handle_1a02(regs); break;
392 case 0x03: handle_1a03(regs); break;
393 case 0x04: handle_1a04(regs); break;
394 case 0x05: handle_1a05(regs); break;
395 case 0x06: handle_1a06(regs); break;
396 case 0x07: handle_1a07(regs); break;
397 case 0xb1: handle_1ab1(regs); break;
398 default: handle_1aXX(regs); break;
402 // INT 08h System Timer ISR Entry Point
406 debug_isr(DEBUG_ISR_08);
410 u32 counter = GET_BDA(timer_counter);
412 // compare to one days worth of timer ticks at 18.2 hz
413 if (counter >= 0x001800B0) {
414 // there has been a midnight rollover at this point
416 SET_BDA(timer_rollover, GET_BDA(timer_rollover) + 1);
419 SET_BDA(timer_counter, counter);
421 // chain to user timer tick INT #0x1c
423 call16_simpint(0x1c, &eax, &flags);
429 /****************************************************************
431 ****************************************************************/
434 set_usertimer(u32 usecs, u16 seg, u16 offset)
436 if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING)
439 // Interval not already set.
440 SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
441 SET_BDA(ptr_user_wait_complete_flag, (seg << 16) | offset);
442 SET_BDA(user_wait_timeout, usecs);
444 // Turn on the Periodic Interrupt timer
445 u8 bRegister = inb_cmos(CMOS_STATUS_B);
446 outb_cmos(bRegister | RTC_B_PIE, CMOS_STATUS_B);
454 // Turn off status byte.
455 SET_BDA(rtc_wait_flag, 0);
456 // Clear the Periodic Interrupt.
457 u8 bRegister = inb_cmos(CMOS_STATUS_B);
458 outb_cmos(bRegister & ~RTC_B_PIE, CMOS_STATUS_B);
461 #define RET_ECLOCKINUSE 0x83
463 // Wait for CX:DX microseconds
465 handle_1586(struct bregs *regs)
467 // Use the rtc to wait for the specified time.
469 u32 count = (regs->cx << 16) | regs->dx;
470 int ret = set_usertimer(count, GET_SEG(SS), (u32)&statusflag);
472 set_code_fail(regs, RET_ECLOCKINUSE);
482 // Set Interval requested.
484 handle_158300(struct bregs *regs)
486 int ret = set_usertimer((regs->cx << 16) | regs->dx, regs->es, regs->bx);
488 // Interval already set.
489 set_code_fail(regs, RET_EUNSUPPORTED);
494 // Clear interval requested
496 handle_158301(struct bregs *regs)
503 handle_1583XX(struct bregs *regs)
505 set_code_fail(regs, RET_EUNSUPPORTED);
510 handle_1583(struct bregs *regs)
513 case 0x00: handle_158300(regs); break;
514 case 0x01: handle_158301(regs); break;
515 default: handle_1583XX(regs); break;
519 // int70h: IRQ8 - CMOS RTC
523 debug_isr(DEBUG_ISR_70);
525 // Check which modes are enabled and have occurred.
526 u8 registerB = inb_cmos(CMOS_STATUS_B);
527 u8 registerC = inb_cmos(CMOS_STATUS_C);
529 if (!(registerB & (RTC_B_PIE|RTC_B_AIE)))
531 if (registerC & 0x20) {
532 // Handle Alarm Interrupt.
534 call16_simpint(0x4a, &eax, &flags);
536 if (!(registerC & 0x40))
539 // Handle Periodic Interrupt.
541 if (!GET_BDA(rtc_wait_flag))
544 // Wait Interval (Int 15, AH=83) active.
545 u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds.
547 // Done waiting - write to specified flag byte.
548 u32 segoff = GET_BDA(ptr_user_wait_complete_flag);
549 u16 segment = segoff >> 16;
550 u16 offset = segoff & 0xffff;
551 u8 oldval = GET_FARVAR(segment, *(u8*)(offset+0));
552 SET_FARVAR(segment, *(u8*)(offset+0), oldval | 0x80);
558 SET_BDA(user_wait_timeout, time);