1 // 16bit code to handle system clocks.
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2002 MandrakeSoft S.A.
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "biosvar.h" // SET_BDA
9 #include "util.h" // debug_enter
10 #include "disk.h" // floppy_tick
11 #include "cmos.h" // inb_cmos
12 #include "pic.h" // eoi_pic1
13 #include "bregs.h" // struct bregs
14 #include "biosvar.h" // GET_GLOBAL
15 #include "usb-hid.h" // usb_check_key
18 #define RTC_A_UIP 0x80
20 #define RTC_B_SET 0x80
21 #define RTC_B_PIE 0x40
22 #define RTC_B_AIE 0x20
23 #define RTC_B_UIE 0x10
24 #define RTC_B_BIN 0x04
25 #define RTC_B_24HR 0x02
26 #define RTC_B_DSE 0x01
29 // Bits for PORT_PS2_CTRLB
30 #define PPCB_T2GATE (1<<0)
31 #define PPCB_SPKR (1<<1)
32 #define PPCB_T2OUT (1<<5)
34 // Bits for PORT_PIT_MODE
35 #define PM_SEL_TIMER0 (0<<6)
36 #define PM_SEL_TIMER1 (1<<6)
37 #define PM_SEL_TIMER2 (2<<6)
38 #define PM_SEL_READBACK (3<<6)
39 #define PM_ACCESS_LATCH (0<<4)
40 #define PM_ACCESS_LOBYTE (1<<4)
41 #define PM_ACCESS_HIBYTE (2<<4)
42 #define PM_ACCESS_WORD (3<<4)
43 #define PM_MODE0 (0<<1)
44 #define PM_MODE1 (1<<1)
45 #define PM_MODE2 (2<<1)
46 #define PM_MODE3 (3<<1)
47 #define PM_MODE4 (4<<1)
48 #define PM_MODE5 (5<<1)
49 #define PM_CNT_BINARY (0<<0)
50 #define PM_CNT_BCD (1<<0)
53 /****************************************************************
55 ****************************************************************/
57 #define TICKS_PER_DAY (u32)((u64)60*60*24*PIT_TICK_RATE / PIT_TICK_INTERVAL)
58 #define CALIBRATE_COUNT 0x800 // Approx 1.7ms
60 u32 cpu_khz VAR16VISIBLE;
66 u8 orig = inb(PORT_PS2_CTRLB);
67 outb((orig & ~PPCB_SPKR) | PPCB_T2GATE, PORT_PS2_CTRLB);
68 /* binary, mode 0, LSB/MSB, Ch 2 */
69 outb(PM_SEL_TIMER2|PM_ACCESS_WORD|PM_MODE0|PM_CNT_BINARY, PORT_PIT_MODE);
71 outb(CALIBRATE_COUNT & 0xFF, PORT_PIT_COUNTER2);
73 outb(CALIBRATE_COUNT >> 8, PORT_PIT_COUNTER2);
75 u64 start = rdtscll();
76 while ((inb(PORT_PS2_CTRLB) & PPCB_T2OUT) == 0)
80 // Restore PORT_PS2_CTRLB
81 outb(orig, PORT_PS2_CTRLB);
83 // Store calibrated cpu khz.
84 u64 diff = end - start;
85 dprintf(6, "tsc calibrate start=%u end=%u diff=%u\n"
86 , (u32)start, (u32)end, (u32)diff);
87 u32 hz = diff * PIT_TICK_RATE / CALIBRATE_COUNT;
88 SET_GLOBAL(cpu_khz, hz / 1000);
90 dprintf(1, "CPU Mhz=%u\n", hz / 1000000);
96 u64 start = rdtscll();
97 u64 end = start + diff;
98 while (!check_time(end))
105 u64 start = rdtscll();
106 u64 end = start + diff;
107 while (!check_time(end))
111 void ndelay(u32 count) {
112 tscdelay(count * GET_GLOBAL(cpu_khz) / 1000000);
114 void udelay(u32 count) {
115 tscdelay(count * GET_GLOBAL(cpu_khz) / 1000);
117 void mdelay(u32 count) {
118 tscdelay(count * GET_GLOBAL(cpu_khz));
121 void nsleep(u32 count) {
122 tscsleep(count * GET_GLOBAL(cpu_khz) / 1000000);
124 void usleep(u32 count) {
125 tscsleep(count * GET_GLOBAL(cpu_khz) / 1000);
127 void msleep(u32 count) {
128 tscsleep(count * GET_GLOBAL(cpu_khz));
131 // Return the TSC value that is 'msecs' time in the future.
133 calc_future_tsc(u32 msecs)
135 u32 khz = GET_GLOBAL(cpu_khz);
136 return rdtscll() + ((u64)khz * msecs);
139 calc_future_tsc_usec(u32 usecs)
141 u32 khz = GET_GLOBAL(cpu_khz);
142 return rdtscll() + ((u64)(khz/1000) * usecs);
146 /****************************************************************
148 ****************************************************************/
153 // This function checks to see if the update-in-progress bit
154 // is set in CMOS Status Register A. If not, it returns 0.
155 // If it is set, it tries to wait until there is a transition
156 // to 0, and will return 0 if such a transition occurs. A -1
157 // is returned only after timing out. The maximum period
158 // that this bit should be set is constrained to (1984+244)
159 // useconds, so we wait for 3 msec max.
161 if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
163 u64 end = calc_future_tsc(3);
165 if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
167 } while (!check_time(end));
169 // update-in-progress never transitioned to 0
176 // timer0: binary count, 16bit count, mode 2
177 outb(PM_SEL_TIMER0|PM_ACCESS_WORD|PM_MODE2|PM_CNT_BINARY, PORT_PIT_MODE);
178 // maximum count of 0000H = 18.2Hz
179 outb(0x0, PORT_PIT_COUNTER0);
180 outb(0x0, PORT_PIT_COUNTER0);
186 outb_cmos(0x26, CMOS_STATUS_A); // 32,768Khz src, 976.5625us updates
187 u8 regB = inb_cmos(CMOS_STATUS_B);
188 outb_cmos((regB & RTC_B_DSE) | RTC_B_24HR, CMOS_STATUS_B);
189 inb_cmos(CMOS_STATUS_C);
190 inb_cmos(CMOS_STATUS_D);
196 return (val & 0xf) + ((val >> 4) * 10);
202 dprintf(3, "init timer\n");
208 u32 seconds = bcd2bin(inb_cmos(CMOS_RTC_SECONDS));
209 u32 minutes = bcd2bin(inb_cmos(CMOS_RTC_MINUTES));
210 u32 hours = bcd2bin(inb_cmos(CMOS_RTC_HOURS));
211 u32 ticks = (hours * 60 + minutes) * 60 + seconds;
212 ticks = ((u64)ticks * PIT_TICK_RATE) / PIT_TICK_INTERVAL;
213 SET_BDA(timer_counter, ticks);
214 SET_BDA(timer_rollover, 0);
216 enable_hwirq(0, entry_08);
217 enable_hwirq(8, entry_70);
221 /****************************************************************
222 * Standard clock functions
223 ****************************************************************/
225 // get current clock count
227 handle_1a00(struct bregs *regs)
229 u32 ticks = GET_BDA(timer_counter);
230 regs->cx = ticks >> 16;
232 regs->al = GET_BDA(timer_rollover);
233 SET_BDA(timer_rollover, 0); // reset flag
237 // Set Current Clock Count
239 handle_1a01(struct bregs *regs)
241 u32 ticks = (regs->cx << 16) | regs->dx;
242 SET_BDA(timer_counter, ticks);
243 SET_BDA(timer_rollover, 0); // reset flag
244 // XXX - should use set_code_success()?
251 handle_1a02(struct bregs *regs)
253 if (rtc_updating()) {
258 regs->dh = inb_cmos(CMOS_RTC_SECONDS);
259 regs->cl = inb_cmos(CMOS_RTC_MINUTES);
260 regs->ch = inb_cmos(CMOS_RTC_HOURS);
261 regs->dl = inb_cmos(CMOS_STATUS_B) & RTC_B_DSE;
269 handle_1a03(struct bregs *regs)
271 // Using a debugger, I notice the following masking/setting
272 // of bits in Status Register B, by setting Reg B to
273 // a few values and getting its value after INT 1A was called.
276 // before 1111 1101 0111 1101 0000 0000
277 // after 0110 0010 0110 0010 0000 0010
279 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
280 // My assumption: RegB = ((RegB & 01100000b) | 00000010b)
281 if (rtc_updating()) {
283 // fall through as if an update were not in progress
285 outb_cmos(regs->dh, CMOS_RTC_SECONDS);
286 outb_cmos(regs->cl, CMOS_RTC_MINUTES);
287 outb_cmos(regs->ch, CMOS_RTC_HOURS);
288 // Set Daylight Savings time enabled bit to requested value
289 u8 val8 = ((inb_cmos(CMOS_STATUS_B) & (RTC_B_PIE|RTC_B_AIE))
290 | RTC_B_24HR | (regs->dl & RTC_B_DSE));
291 outb_cmos(val8, CMOS_STATUS_B);
293 regs->al = val8; // val last written to Reg B
299 handle_1a04(struct bregs *regs)
302 if (rtc_updating()) {
306 regs->cl = inb_cmos(CMOS_RTC_YEAR);
307 regs->dh = inb_cmos(CMOS_RTC_MONTH);
308 regs->dl = inb_cmos(CMOS_RTC_DAY_MONTH);
309 if (CONFIG_COREBOOT) {
315 regs->ch = inb_cmos(CMOS_CENTURY);
323 handle_1a05(struct bregs *regs)
325 // Using a debugger, I notice the following masking/setting
326 // of bits in Status Register B, by setting Reg B to
327 // a few values and getting its value after INT 1A was called.
329 // try#1 try#2 try#3 try#4
330 // before 1111 1101 0111 1101 0000 0010 0000 0000
331 // after 0110 1101 0111 1101 0000 0010 0000 0000
333 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
334 // My assumption: RegB = (RegB & 01111111b)
335 if (rtc_updating()) {
340 outb_cmos(regs->cl, CMOS_RTC_YEAR);
341 outb_cmos(regs->dh, CMOS_RTC_MONTH);
342 outb_cmos(regs->dl, CMOS_RTC_DAY_MONTH);
343 if (!CONFIG_COREBOOT)
344 outb_cmos(regs->ch, CMOS_CENTURY);
345 // clear halt-clock bit
346 u8 val8 = inb_cmos(CMOS_STATUS_B) & ~RTC_B_SET;
347 outb_cmos(val8, CMOS_STATUS_B);
349 regs->al = val8; // AL = val last written to Reg B
353 // Set Alarm Time in CMOS
355 handle_1a06(struct bregs *regs)
357 // Using a debugger, I notice the following masking/setting
358 // of bits in Status Register B, by setting Reg B to
359 // a few values and getting its value after INT 1A was called.
362 // before 1101 1111 0101 1111 0000 0000
363 // after 0110 1111 0111 1111 0010 0000
365 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
366 // My assumption: RegB = ((RegB & 01111111b) | 00100000b)
367 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
369 if (val8 & RTC_B_AIE) {
370 // Alarm interrupt enabled already
374 if (rtc_updating()) {
376 // fall through as if an update were not in progress
378 outb_cmos(regs->dh, CMOS_RTC_SECONDS_ALARM);
379 outb_cmos(regs->cl, CMOS_RTC_MINUTES_ALARM);
380 outb_cmos(regs->ch, CMOS_RTC_HOURS_ALARM);
381 // enable Status Reg B alarm bit, clear halt clock bit
382 outb_cmos((val8 & ~RTC_B_SET) | RTC_B_AIE, CMOS_STATUS_B);
388 handle_1a07(struct bregs *regs)
390 // Using a debugger, I notice the following masking/setting
391 // of bits in Status Register B, by setting Reg B to
392 // a few values and getting its value after INT 1A was called.
394 // try#1 try#2 try#3 try#4
395 // before 1111 1101 0111 1101 0010 0000 0010 0010
396 // after 0100 0101 0101 0101 0000 0000 0000 0010
398 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
399 // My assumption: RegB = (RegB & 01010111b)
400 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
401 // clear clock-halt bit, disable alarm bit
402 outb_cmos(val8 & ~(RTC_B_SET|RTC_B_AIE), CMOS_STATUS_B);
404 regs->al = val8; // val last written to Reg B
410 handle_1aXX(struct bregs *regs)
412 set_unimplemented(regs);
415 // INT 1Ah Time-of-day Service Entry Point
417 handle_1a(struct bregs *regs)
419 debug_enter(regs, DEBUG_HDL_1a);
421 case 0x00: handle_1a00(regs); break;
422 case 0x01: handle_1a01(regs); break;
423 case 0x02: handle_1a02(regs); break;
424 case 0x03: handle_1a03(regs); break;
425 case 0x04: handle_1a04(regs); break;
426 case 0x05: handle_1a05(regs); break;
427 case 0x06: handle_1a06(regs); break;
428 case 0x07: handle_1a07(regs); break;
429 case 0xb1: handle_1ab1(regs); break;
430 default: handle_1aXX(regs); break;
434 // INT 08h System Timer ISR Entry Point
438 debug_isr(DEBUG_ISR_08);
442 u32 counter = GET_BDA(timer_counter);
444 // compare to one days worth of timer ticks at 18.2 hz
445 if (counter >= TICKS_PER_DAY) {
446 // there has been a midnight rollover at this point
448 SET_BDA(timer_rollover, GET_BDA(timer_rollover) + 1);
451 SET_BDA(timer_counter, counter);
455 // chain to user timer tick INT #0x1c
457 call16_simpint(0x1c, &eax, &flags);
463 /****************************************************************
465 ****************************************************************/
470 u16 ebda_seg = get_ebda_seg();
471 int count = GET_EBDA2(ebda_seg, RTCusers);
472 SET_EBDA2(ebda_seg, RTCusers, count+1);
475 // Turn on the Periodic Interrupt timer
476 u8 bRegister = inb_cmos(CMOS_STATUS_B);
477 outb_cmos(bRegister | RTC_B_PIE, CMOS_STATUS_B);
483 u16 ebda_seg = get_ebda_seg();
484 int count = GET_EBDA2(ebda_seg, RTCusers);
485 SET_EBDA2(ebda_seg, RTCusers, count-1);
488 // Clear the Periodic Interrupt.
489 u8 bRegister = inb_cmos(CMOS_STATUS_B);
490 outb_cmos(bRegister & ~RTC_B_PIE, CMOS_STATUS_B);
494 set_usertimer(u32 usecs, u16 seg, u16 offset)
496 if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING)
499 // Interval not already set.
500 SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
501 SET_BDA(user_wait_complete_flag, SEGOFF(seg, offset));
502 SET_BDA(user_wait_timeout, usecs);
508 clear_usertimer(void)
510 if (!(GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING))
512 // Turn off status byte.
513 SET_BDA(rtc_wait_flag, 0);
517 #define RET_ECLOCKINUSE 0x83
519 // Wait for CX:DX microseconds
521 handle_1586(struct bregs *regs)
523 // Use the rtc to wait for the specified time.
525 u32 count = (regs->cx << 16) | regs->dx;
526 int ret = set_usertimer(count, GET_SEG(SS), (u32)&statusflag);
528 set_code_invalid(regs, RET_ECLOCKINUSE);
536 // Set Interval requested.
538 handle_158300(struct bregs *regs)
540 int ret = set_usertimer((regs->cx << 16) | regs->dx, regs->es, regs->bx);
542 // Interval already set.
543 set_code_invalid(regs, RET_EUNSUPPORTED);
548 // Clear interval requested
550 handle_158301(struct bregs *regs)
557 handle_1583XX(struct bregs *regs)
559 set_code_unimplemented(regs, RET_EUNSUPPORTED);
564 handle_1583(struct bregs *regs)
567 case 0x00: handle_158300(regs); break;
568 case 0x01: handle_158301(regs); break;
569 default: handle_1583XX(regs); break;
573 #define USEC_PER_RTC DIV_ROUND_CLOSEST(1000000, 1024)
575 // int70h: IRQ8 - CMOS RTC
579 debug_isr(DEBUG_ISR_70);
581 // Check which modes are enabled and have occurred.
582 u8 registerB = inb_cmos(CMOS_STATUS_B);
583 u8 registerC = inb_cmos(CMOS_STATUS_C);
585 if (!(registerB & (RTC_B_PIE|RTC_B_AIE)))
587 if (registerC & RTC_B_AIE) {
588 // Handle Alarm Interrupt.
590 call16_simpint(0x4a, &eax, &flags);
592 if (!(registerC & RTC_B_PIE))
595 // Handle Periodic Interrupt.
599 if (!GET_BDA(rtc_wait_flag))
602 // Wait Interval (Int 15, AH=83) active.
603 u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds.
604 if (time < USEC_PER_RTC) {
605 // Done waiting - write to specified flag byte.
606 struct segoff_s segoff = GET_BDA(user_wait_complete_flag);
607 u16 ptr_seg = segoff.seg;
608 u8 *ptr_far = (u8*)(segoff.offset+0);
609 u8 oldval = GET_FARVAR(ptr_seg, *ptr_far);
610 SET_FARVAR(ptr_seg, *ptr_far, oldval | 0x80);
615 time -= USEC_PER_RTC;
616 SET_BDA(user_wait_timeout, time);