1 // 16bit code to handle system clocks.
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2002 MandrakeSoft S.A.
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "biosvar.h" // SET_BDA
9 #include "util.h" // debug_enter
10 #include "disk.h" // floppy_tick
11 #include "cmos.h" // inb_cmos
12 #include "pic.h" // eoi_pic1
13 #include "bregs.h" // struct bregs
14 #include "biosvar.h" // GET_GLOBAL
17 #define RTC_A_UIP 0x80
19 #define RTC_B_SET 0x80
20 #define RTC_B_PIE 0x40
21 #define RTC_B_AIE 0x20
22 #define RTC_B_UIE 0x10
23 #define RTC_B_BIN 0x04
24 #define RTC_B_24HR 0x02
25 #define RTC_B_DSE 0x01
28 // Bits for PORT_PS2_CTRLB
29 #define PPCB_T2GATE (1<<0)
30 #define PPCB_SPKR (1<<1)
31 #define PPCB_T2OUT (1<<5)
33 // Bits for PORT_PIT_MODE
34 #define PM_SEL_TIMER0 (0<<6)
35 #define PM_SEL_TIMER1 (1<<6)
36 #define PM_SEL_TIMER2 (2<<6)
37 #define PM_SEL_READBACK (3<<6)
38 #define PM_ACCESS_LATCH (0<<4)
39 #define PM_ACCESS_LOBYTE (1<<4)
40 #define PM_ACCESS_HIBYTE (2<<4)
41 #define PM_ACCESS_WORD (3<<4)
42 #define PM_MODE0 (0<<1)
43 #define PM_MODE1 (1<<1)
44 #define PM_MODE2 (2<<1)
45 #define PM_MODE3 (3<<1)
46 #define PM_MODE4 (4<<1)
47 #define PM_MODE5 (5<<1)
48 #define PM_CNT_BINARY (0<<0)
49 #define PM_CNT_BCD (1<<0)
52 /****************************************************************
54 ****************************************************************/
56 #define PIT_TICK_RATE 1193180 // Underlying HZ of PIT
57 #define PIT_TICK_INTERVAL 65536 // Default interval for 18.2Hz timer
58 #define TICKS_PER_DAY (u32)((u64)60*60*24*PIT_TICK_RATE / PIT_TICK_INTERVAL)
59 #define CALIBRATE_COUNT 0x800 // Approx 1.7ms
61 u32 cpu_khz VAR16VISIBLE;
67 u8 orig = inb(PORT_PS2_CTRLB);
68 outb((orig & ~PPCB_SPKR) | PPCB_T2GATE, PORT_PS2_CTRLB);
69 /* binary, mode 0, LSB/MSB, Ch 2 */
70 outb(PM_SEL_TIMER2|PM_ACCESS_WORD|PM_MODE0|PM_CNT_BINARY, PORT_PIT_MODE);
72 outb(CALIBRATE_COUNT & 0xFF, PORT_PIT_COUNTER2);
74 outb(CALIBRATE_COUNT >> 8, PORT_PIT_COUNTER2);
76 u64 start = rdtscll();
77 while ((inb(PORT_PS2_CTRLB) & PPCB_T2OUT) == 0)
81 // Restore PORT_PS2_CTRLB
82 outb(orig, PORT_PS2_CTRLB);
84 // Store calibrated cpu khz.
85 u64 diff = end - start;
86 dprintf(6, "tsc calibrate start=%u end=%u diff=%u\n"
87 , (u32)start, (u32)end, (u32)diff);
88 u32 hz = diff * PIT_TICK_RATE / CALIBRATE_COUNT;
89 SET_GLOBAL(cpu_khz, hz / 1000);
91 dprintf(1, "CPU Mhz=%u\n", hz / 1000000);
97 u64 start = rdtscll();
98 u64 end = start + diff;
99 while (rdtscll() <= end)
106 u32 khz = GET_GLOBAL(cpu_khz);
107 tscsleep(count * khz / 1000000);
112 u32 khz = GET_GLOBAL(cpu_khz);
113 tscsleep(count * khz / 1000);
118 u32 khz = GET_GLOBAL(cpu_khz);
119 tscsleep(count * khz);
122 // Return the TSC value that is 'msecs' time in the future.
124 calc_future_tsc(u32 msecs)
126 u32 khz = GET_GLOBAL(cpu_khz);
127 return rdtscll() + ((u64)khz * msecs);
131 /****************************************************************
133 ****************************************************************/
138 // This function checks to see if the update-in-progress bit
139 // is set in CMOS Status Register A. If not, it returns 0.
140 // If it is set, it tries to wait until there is a transition
141 // to 0, and will return 0 if such a transition occurs. A -1
142 // is returned only after timing out. The maximum period
143 // that this bit should be set is constrained to (1984+244)
144 // useconds, so we wait for 3 msec max.
146 if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
148 u64 end = calc_future_tsc(3);
150 if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
152 } while (rdtscll() <= end);
154 // update-in-progress never transitioned to 0
161 // timer0: binary count, 16bit count, mode 2
162 outb(PM_SEL_TIMER0|PM_ACCESS_WORD|PM_MODE2|PM_CNT_BINARY, PORT_PIT_MODE);
163 // maximum count of 0000H = 18.2Hz
164 outb(0x0, PORT_PIT_COUNTER0);
165 outb(0x0, PORT_PIT_COUNTER0);
171 outb_cmos(0x26, CMOS_STATUS_A); // 32,768Khz src, 976.5625us updates
172 u8 regB = inb_cmos(CMOS_STATUS_B);
173 outb_cmos((regB & RTC_B_DSE) | RTC_B_24HR, CMOS_STATUS_B);
174 inb_cmos(CMOS_STATUS_C);
175 inb_cmos(CMOS_STATUS_D);
181 return (val & 0xf) + ((val >> 4) * 10);
187 dprintf(3, "init timer\n");
193 u32 seconds = bcd2bin(inb_cmos(CMOS_RTC_SECONDS));
194 u32 minutes = bcd2bin(inb_cmos(CMOS_RTC_MINUTES));
195 u32 hours = bcd2bin(inb_cmos(CMOS_RTC_HOURS));
196 u32 ticks = (hours * 60 + minutes) * 60 + seconds;
197 ticks = ((u64)ticks * PIT_TICK_RATE) / PIT_TICK_INTERVAL;
198 SET_BDA(timer_counter, ticks);
199 SET_BDA(timer_rollover, 0);
201 enable_hwirq(0, entry_08);
202 enable_hwirq(8, entry_70);
206 /****************************************************************
207 * Standard clock functions
208 ****************************************************************/
210 // get current clock count
212 handle_1a00(struct bregs *regs)
214 u32 ticks = GET_BDA(timer_counter);
215 regs->cx = ticks >> 16;
217 regs->al = GET_BDA(timer_rollover);
218 SET_BDA(timer_rollover, 0); // reset flag
222 // Set Current Clock Count
224 handle_1a01(struct bregs *regs)
226 u32 ticks = (regs->cx << 16) | regs->dx;
227 SET_BDA(timer_counter, ticks);
228 SET_BDA(timer_rollover, 0); // reset flag
229 // XXX - should use set_code_success()?
236 handle_1a02(struct bregs *regs)
238 if (rtc_updating()) {
243 regs->dh = inb_cmos(CMOS_RTC_SECONDS);
244 regs->cl = inb_cmos(CMOS_RTC_MINUTES);
245 regs->ch = inb_cmos(CMOS_RTC_HOURS);
246 regs->dl = inb_cmos(CMOS_STATUS_B) & RTC_B_DSE;
254 handle_1a03(struct bregs *regs)
256 // Using a debugger, I notice the following masking/setting
257 // of bits in Status Register B, by setting Reg B to
258 // a few values and getting its value after INT 1A was called.
261 // before 1111 1101 0111 1101 0000 0000
262 // after 0110 0010 0110 0010 0000 0010
264 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
265 // My assumption: RegB = ((RegB & 01100000b) | 00000010b)
266 if (rtc_updating()) {
268 // fall through as if an update were not in progress
270 outb_cmos(regs->dh, CMOS_RTC_SECONDS);
271 outb_cmos(regs->cl, CMOS_RTC_MINUTES);
272 outb_cmos(regs->ch, CMOS_RTC_HOURS);
273 // Set Daylight Savings time enabled bit to requested value
274 u8 val8 = ((inb_cmos(CMOS_STATUS_B) & (RTC_B_PIE|RTC_B_AIE))
275 | RTC_B_24HR | (regs->dl & RTC_B_DSE));
276 outb_cmos(val8, CMOS_STATUS_B);
278 regs->al = val8; // val last written to Reg B
284 handle_1a04(struct bregs *regs)
287 if (rtc_updating()) {
291 regs->cl = inb_cmos(CMOS_RTC_YEAR);
292 regs->dh = inb_cmos(CMOS_RTC_MONTH);
293 regs->dl = inb_cmos(CMOS_RTC_DAY_MONTH);
294 if (CONFIG_COREBOOT) {
300 regs->ch = inb_cmos(CMOS_CENTURY);
308 handle_1a05(struct bregs *regs)
310 // Using a debugger, I notice the following masking/setting
311 // of bits in Status Register B, by setting Reg B to
312 // a few values and getting its value after INT 1A was called.
314 // try#1 try#2 try#3 try#4
315 // before 1111 1101 0111 1101 0000 0010 0000 0000
316 // after 0110 1101 0111 1101 0000 0010 0000 0000
318 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
319 // My assumption: RegB = (RegB & 01111111b)
320 if (rtc_updating()) {
325 outb_cmos(regs->cl, CMOS_RTC_YEAR);
326 outb_cmos(regs->dh, CMOS_RTC_MONTH);
327 outb_cmos(regs->dl, CMOS_RTC_DAY_MONTH);
328 if (!CONFIG_COREBOOT)
329 outb_cmos(regs->ch, CMOS_CENTURY);
330 // clear halt-clock bit
331 u8 val8 = inb_cmos(CMOS_STATUS_B) & ~RTC_B_SET;
332 outb_cmos(val8, CMOS_STATUS_B);
334 regs->al = val8; // AL = val last written to Reg B
338 // Set Alarm Time in CMOS
340 handle_1a06(struct bregs *regs)
342 // Using a debugger, I notice the following masking/setting
343 // of bits in Status Register B, by setting Reg B to
344 // a few values and getting its value after INT 1A was called.
347 // before 1101 1111 0101 1111 0000 0000
348 // after 0110 1111 0111 1111 0010 0000
350 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
351 // My assumption: RegB = ((RegB & 01111111b) | 00100000b)
352 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
354 if (val8 & RTC_B_AIE) {
355 // Alarm interrupt enabled already
359 if (rtc_updating()) {
361 // fall through as if an update were not in progress
363 outb_cmos(regs->dh, CMOS_RTC_SECONDS_ALARM);
364 outb_cmos(regs->cl, CMOS_RTC_MINUTES_ALARM);
365 outb_cmos(regs->ch, CMOS_RTC_HOURS_ALARM);
366 // enable Status Reg B alarm bit, clear halt clock bit
367 outb_cmos((val8 & ~RTC_B_SET) | RTC_B_AIE, CMOS_STATUS_B);
373 handle_1a07(struct bregs *regs)
375 // Using a debugger, I notice the following masking/setting
376 // of bits in Status Register B, by setting Reg B to
377 // a few values and getting its value after INT 1A was called.
379 // try#1 try#2 try#3 try#4
380 // before 1111 1101 0111 1101 0010 0000 0010 0010
381 // after 0100 0101 0101 0101 0000 0000 0000 0010
383 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
384 // My assumption: RegB = (RegB & 01010111b)
385 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
386 // clear clock-halt bit, disable alarm bit
387 outb_cmos(val8 & ~(RTC_B_SET|RTC_B_AIE), CMOS_STATUS_B);
389 regs->al = val8; // val last written to Reg B
395 handle_1aXX(struct bregs *regs)
400 // INT 1Ah Time-of-day Service Entry Point
402 handle_1a(struct bregs *regs)
404 debug_enter(regs, DEBUG_HDL_1a);
406 case 0x00: handle_1a00(regs); break;
407 case 0x01: handle_1a01(regs); break;
408 case 0x02: handle_1a02(regs); break;
409 case 0x03: handle_1a03(regs); break;
410 case 0x04: handle_1a04(regs); break;
411 case 0x05: handle_1a05(regs); break;
412 case 0x06: handle_1a06(regs); break;
413 case 0x07: handle_1a07(regs); break;
414 case 0xb1: handle_1ab1(regs); break;
415 default: handle_1aXX(regs); break;
419 // INT 08h System Timer ISR Entry Point
423 debug_isr(DEBUG_ISR_08);
427 u32 counter = GET_BDA(timer_counter);
429 // compare to one days worth of timer ticks at 18.2 hz
430 if (counter >= TICKS_PER_DAY) {
431 // there has been a midnight rollover at this point
433 SET_BDA(timer_rollover, GET_BDA(timer_rollover) + 1);
436 SET_BDA(timer_counter, counter);
438 // chain to user timer tick INT #0x1c
440 call16_simpint(0x1c, &eax, &flags);
446 /****************************************************************
448 ****************************************************************/
451 set_usertimer(u32 usecs, u16 seg, u16 offset)
453 if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING)
456 // Interval not already set.
457 SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
458 SET_BDA(user_wait_complete_flag, SEGOFF(seg, offset));
459 SET_BDA(user_wait_timeout, usecs);
461 // Turn on the Periodic Interrupt timer
462 u8 bRegister = inb_cmos(CMOS_STATUS_B);
463 outb_cmos(bRegister | RTC_B_PIE, CMOS_STATUS_B);
471 // Turn off status byte.
472 SET_BDA(rtc_wait_flag, 0);
473 // Clear the Periodic Interrupt.
474 u8 bRegister = inb_cmos(CMOS_STATUS_B);
475 outb_cmos(bRegister & ~RTC_B_PIE, CMOS_STATUS_B);
478 #define RET_ECLOCKINUSE 0x83
480 // Wait for CX:DX microseconds
482 handle_1586(struct bregs *regs)
484 // Use the rtc to wait for the specified time.
486 u32 count = (regs->cx << 16) | regs->dx;
487 int ret = set_usertimer(count, GET_SEG(SS), (u32)&statusflag);
489 set_code_fail(regs, RET_ECLOCKINUSE);
497 // Set Interval requested.
499 handle_158300(struct bregs *regs)
501 int ret = set_usertimer((regs->cx << 16) | regs->dx, regs->es, regs->bx);
503 // Interval already set.
504 set_code_fail(regs, RET_EUNSUPPORTED);
509 // Clear interval requested
511 handle_158301(struct bregs *regs)
518 handle_1583XX(struct bregs *regs)
520 set_code_fail(regs, RET_EUNSUPPORTED);
525 handle_1583(struct bregs *regs)
528 case 0x00: handle_158300(regs); break;
529 case 0x01: handle_158301(regs); break;
530 default: handle_1583XX(regs); break;
534 #define USEC_PER_RTC DIV_ROUND_CLOSEST(1000000, 1024)
536 // int70h: IRQ8 - CMOS RTC
540 debug_isr(DEBUG_ISR_70);
542 // Check which modes are enabled and have occurred.
543 u8 registerB = inb_cmos(CMOS_STATUS_B);
544 u8 registerC = inb_cmos(CMOS_STATUS_C);
546 if (!(registerB & (RTC_B_PIE|RTC_B_AIE)))
548 if (registerC & RTC_B_AIE) {
549 // Handle Alarm Interrupt.
551 call16_simpint(0x4a, &eax, &flags);
553 if (!(registerC & RTC_B_PIE))
556 // Handle Periodic Interrupt.
558 if (!GET_BDA(rtc_wait_flag))
561 // Wait Interval (Int 15, AH=83) active.
562 u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds.
563 if (time < USEC_PER_RTC) {
564 // Done waiting - write to specified flag byte.
565 struct segoff_s segoff = GET_BDA(user_wait_complete_flag);
566 u16 ptr_seg = segoff.seg;
567 u8 *ptr_far = (u8*)(segoff.offset+0);
568 u8 oldval = GET_FARVAR(ptr_seg, *ptr_far);
569 SET_FARVAR(ptr_seg, *ptr_far, oldval | 0x80);
574 time -= USEC_PER_RTC;
575 SET_BDA(user_wait_timeout, time);