1 // 16bit code to handle system clocks.
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2002 MandrakeSoft S.A.
6 // This file may be distributed under the terms of the GNU GPLv3 license.
8 #include "biosvar.h" // struct bregs
9 #include "util.h" // debug_enter
10 #include "disk.h" // floppy_tick
11 #include "cmos.h" // inb_cmos
13 #define DEBUGF1(fmt, args...) bprintf(0, fmt , ##args)
14 #define DEBUGF(fmt, args...)
17 #define RTC_A_UIP 0x80
18 #define RTC_B_SET 0x80
19 #define RTC_B_PIE 0x40
20 #define RTC_B_AIE 0x20
21 #define RTC_B_UIE 0x10
24 /****************************************************************
26 ****************************************************************/
31 // timer0: binary count, 16bit count, mode 2
32 outb(0x34, PORT_PIT_MODE);
33 // maximum count of 0000H = 18.2Hz
34 outb(0x0, PORT_PIT_COUNTER0);
35 outb(0x0, PORT_PIT_COUNTER0);
41 return (val & 0xf) + ((val >> 4) * 10);
49 u32 seconds = bcd2bin(inb_cmos(CMOS_RTC_SECONDS));
50 u32 ticks = (seconds * 18206507) / 1000000;
51 u32 minutes = bcd2bin(inb_cmos(CMOS_RTC_MINUTES));
52 ticks += (minutes * 10923904) / 10000;
53 u32 hours = bcd2bin(inb_cmos(CMOS_RTC_HOURS));
54 ticks += (hours * 65543427) / 1000;
55 SET_BDA(timer_counter, ticks);
56 SET_BDA(timer_rollover, 0);
62 outb_cmos(0x26, CMOS_STATUS_A);
63 outb_cmos(0x02, CMOS_STATUS_B);
64 inb_cmos(CMOS_STATUS_C);
65 inb_cmos(CMOS_STATUS_D);
69 /****************************************************************
70 * Standard clock functions
71 ****************************************************************/
76 // This function checks to see if the update-in-progress bit
77 // is set in CMOS Status Register A. If not, it returns 0.
78 // If it is set, it tries to wait until there is a transition
79 // to 0, and will return 0 if such a transition occurs. A 1
80 // is returned only after timing out. The maximum period
81 // that this bit should be set is constrained to 244useconds.
82 // The count I use below guarantees coverage or more than
83 // this time, with any reasonable IPS setting.
86 while (--count != 0) {
87 if ( (inb_cmos(CMOS_STATUS_A) & 0x80) == 0 )
90 return 1; // update-in-progress never transitioned to 0
93 // get current clock count
95 handle_1a00(struct bregs *regs)
97 u32 ticks = GET_BDA(timer_counter);
98 regs->cx = ticks >> 16;
100 regs->al = GET_BDA(timer_rollover);
101 SET_BDA(timer_rollover, 0); // reset flag
105 // Set Current Clock Count
107 handle_1a01(struct bregs *regs)
109 u32 ticks = (regs->cx << 16) | regs->dx;
110 SET_BDA(timer_counter, ticks);
111 SET_BDA(timer_rollover, 0); // reset flag
118 handle_1a02(struct bregs *regs)
120 if (rtc_updating()) {
125 regs->dh = inb_cmos(CMOS_RTC_SECONDS);
126 regs->cl = inb_cmos(CMOS_RTC_MINUTES);
127 regs->ch = inb_cmos(CMOS_RTC_HOURS);
128 regs->dl = inb_cmos(CMOS_STATUS_B) & 0x01;
136 handle_1a03(struct bregs *regs)
138 // Using a debugger, I notice the following masking/setting
139 // of bits in Status Register B, by setting Reg B to
140 // a few values and getting its value after INT 1A was called.
143 // before 1111 1101 0111 1101 0000 0000
144 // after 0110 0010 0110 0010 0000 0010
146 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
147 // My assumption: RegB = ((RegB & 01100000b) | 00000010b)
148 if (rtc_updating()) {
150 // fall through as if an update were not in progress
152 outb_cmos(regs->dh, CMOS_RTC_SECONDS);
153 outb_cmos(regs->cl, CMOS_RTC_MINUTES);
154 outb_cmos(regs->ch, CMOS_RTC_HOURS);
155 // Set Daylight Savings time enabled bit to requested value
156 u8 val8 = (inb_cmos(CMOS_STATUS_B) & 0x60) | 0x02 | (regs->dl & 0x01);
157 outb_cmos(val8, CMOS_STATUS_B);
159 regs->al = val8; // val last written to Reg B
165 handle_1a04(struct bregs *regs)
168 if (rtc_updating()) {
172 regs->cl = inb_cmos(CMOS_RTC_YEAR);
173 regs->dh = inb_cmos(CMOS_RTC_MONTH);
174 regs->dl = inb_cmos(CMOS_RTC_DAY_MONTH);
175 regs->ch = inb_cmos(CMOS_CENTURY);
182 handle_1a05(struct bregs *regs)
184 // Using a debugger, I notice the following masking/setting
185 // of bits in Status Register B, by setting Reg B to
186 // a few values and getting its value after INT 1A was called.
188 // try#1 try#2 try#3 try#4
189 // before 1111 1101 0111 1101 0000 0010 0000 0000
190 // after 0110 1101 0111 1101 0000 0010 0000 0000
192 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
193 // My assumption: RegB = (RegB & 01111111b)
194 if (rtc_updating()) {
199 outb_cmos(regs->cl, CMOS_RTC_YEAR);
200 outb_cmos(regs->dh, CMOS_RTC_MONTH);
201 outb_cmos(regs->dl, CMOS_RTC_DAY_MONTH);
202 outb_cmos(regs->ch, CMOS_CENTURY);
203 // clear halt-clock bit
204 u8 val8 = inb_cmos(CMOS_STATUS_B) & ~RTC_B_SET;
205 outb_cmos(val8, CMOS_STATUS_B);
207 regs->al = val8; // AL = val last written to Reg B
211 // Set Alarm Time in CMOS
213 handle_1a06(struct bregs *regs)
215 // Using a debugger, I notice the following masking/setting
216 // of bits in Status Register B, by setting Reg B to
217 // a few values and getting its value after INT 1A was called.
220 // before 1101 1111 0101 1111 0000 0000
221 // after 0110 1111 0111 1111 0010 0000
223 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
224 // My assumption: RegB = ((RegB & 01111111b) | 00100000b)
225 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
228 // Alarm interrupt enabled already
232 if (rtc_updating()) {
234 // fall through as if an update were not in progress
236 outb_cmos(regs->dh, CMOS_RTC_SECONDS_ALARM);
237 outb_cmos(regs->cl, CMOS_RTC_MINUTES_ALARM);
238 outb_cmos(regs->ch, CMOS_RTC_HOURS_ALARM);
239 outb(inb(PORT_PIC2_DATA) & ~PIC2_IRQ8, PORT_PIC2_DATA); // enable IRQ 8
240 // enable Status Reg B alarm bit, clear halt clock bit
241 outb_cmos((val8 & ~RTC_B_SET) | RTC_B_AIE, CMOS_STATUS_B);
247 handle_1a07(struct bregs *regs)
249 // Using a debugger, I notice the following masking/setting
250 // of bits in Status Register B, by setting Reg B to
251 // a few values and getting its value after INT 1A was called.
253 // try#1 try#2 try#3 try#4
254 // before 1111 1101 0111 1101 0010 0000 0010 0010
255 // after 0100 0101 0101 0101 0000 0000 0000 0010
257 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
258 // My assumption: RegB = (RegB & 01010111b)
259 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
260 // clear clock-halt bit, disable alarm bit
261 outb_cmos(val8 & ~(RTC_B_SET|RTC_B_AIE), CMOS_STATUS_B);
263 regs->al = val8; // val last written to Reg B
269 handle_1aXX(struct bregs *regs)
274 // INT 1Ah Time-of-day Service Entry Point
276 handle_1a(struct bregs *regs)
280 case 0x00: handle_1a00(regs); break;
281 case 0x01: handle_1a01(regs); break;
282 case 0x02: handle_1a02(regs); break;
283 case 0x03: handle_1a03(regs); break;
284 case 0x04: handle_1a04(regs); break;
285 case 0x05: handle_1a05(regs); break;
286 case 0x06: handle_1a06(regs); break;
287 case 0x07: handle_1a07(regs); break;
288 case 0xb1: handle_1ab1(regs); break;
289 default: handle_1aXX(regs); break;
300 // INT 08h System Timer ISR Entry Point
309 u32 counter = GET_BDA(timer_counter);
311 // compare to one days worth of timer ticks at 18.2 hz
312 if (counter >= 0x001800B0) {
313 // there has been a midnight rollover at this point
315 SET_BDA(timer_rollover, GET_BDA(timer_rollover) + 1);
318 SET_BDA(timer_counter, counter);
320 // chain to user timer tick INT #0x1c
322 memset(&br, 0, sizeof(br));
323 call16_int(0x1c, &br);
331 /****************************************************************
333 ****************************************************************/
336 set_usertimer(u32 msecs, u16 seg, u16 offset)
338 if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING)
341 // Interval not already set.
342 SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
343 SET_BDA(ptr_user_wait_complete_flag, (seg << 16) | offset);
344 SET_BDA(user_wait_timeout, msecs);
346 // Unmask IRQ8 so INT70 will get through.
347 u8 irqDisable = inb(PORT_PIC2_DATA);
348 outb(irqDisable & ~PIC2_IRQ8, PORT_PIC2_DATA);
349 // Turn on the Periodic Interrupt timer
350 u8 bRegister = inb_cmos(CMOS_STATUS_B);
351 outb_cmos(bRegister | RTC_B_PIE, CMOS_STATUS_B);
359 // Turn off status byte.
360 SET_BDA(rtc_wait_flag, 0);
361 // Clear the Periodic Interrupt.
362 u8 bRegister = inb_cmos(CMOS_STATUS_B);
363 outb_cmos(bRegister & ~RTC_B_PIE, CMOS_STATUS_B);
366 // Sleep for n microseconds.
371 // In 16bit mode, use the rtc to wait for the specified time.
373 int ret = set_usertimer(count, GET_SEG(SS), (u32)&statusflag);
382 // In 32bit mode, we need to call into 16bit mode to sleep.
384 memset(&br, 0, sizeof(br));
388 call16_int(0x15, &br);
395 #define RET_ECLOCKINUSE 0x83
397 // Wait for CX:DX microseconds. currently using the
398 // refresh request port 0x61 bit4, toggling every 15usec
400 handle_1586(struct bregs *regs)
402 int ret = usleep((regs->cx << 16) | regs->dx);
404 set_code_fail(regs, RET_ECLOCKINUSE);
409 // Set Interval requested.
411 handle_158300(struct bregs *regs)
413 int ret = set_usertimer((regs->cx << 16) | regs->dx, regs->es, regs->bx);
415 // Interval already set.
416 set_code_fail(regs, RET_EUNSUPPORTED);
421 // Clear interval requested
423 handle_158301(struct bregs *regs)
430 handle_1583XX(struct bregs *regs)
432 set_code_fail(regs, RET_EUNSUPPORTED);
437 handle_1583(struct bregs *regs)
440 case 0x00: handle_158300(regs); break;
441 case 0x01: handle_158301(regs); break;
442 default: handle_1583XX(regs); break;
446 // int70h: IRQ8 - CMOS RTC
452 // Check which modes are enabled and have occurred.
453 u8 registerB = inb_cmos(CMOS_STATUS_B);
454 u8 registerC = inb_cmos(CMOS_STATUS_C);
456 if (!(registerB & (RTC_B_PIE|RTC_B_AIE)))
458 if (registerC & 0x20) {
459 // Handle Alarm Interrupt.
461 memset(&br, 0, sizeof(br));
462 call16_int(0x4a, &br);
465 if (!(registerC & 0x40))
468 // Handle Periodic Interrupt.
470 if (!GET_BDA(rtc_wait_flag))
473 // Wait Interval (Int 15, AH=83) active.
474 u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds.
476 // Done waiting - write to specified flag byte.
477 u32 segoff = GET_BDA(ptr_user_wait_complete_flag);
478 u16 segment = segoff >> 16;
479 u16 offset = segoff & 0xffff;
480 u8 oldval = GET_FARVAR(segment, *(u8*)(offset+0));
481 SET_FARVAR(segment, *(u8*)(offset+0), oldval | 0x80);
487 SET_BDA(user_wait_timeout, time);