1 // 16bit code to handle system clocks.
3 // Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2002 MandrakeSoft S.A.
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "biosvar.h" // SET_BDA
9 #include "util.h" // debug_enter
10 #include "disk.h" // floppy_tick
11 #include "cmos.h" // inb_cmos
12 #include "pic.h" // eoi_pic1
13 #include "bregs.h" // struct bregs
14 #include "biosvar.h" // GET_GLOBAL
15 #include "usb-hid.h" // usb_check_event
18 #define RTC_A_UIP 0x80
20 #define RTC_B_SET 0x80
21 #define RTC_B_PIE 0x40
22 #define RTC_B_AIE 0x20
23 #define RTC_B_UIE 0x10
24 #define RTC_B_BIN 0x04
25 #define RTC_B_24HR 0x02
26 #define RTC_B_DSE 0x01
29 // Bits for PORT_PS2_CTRLB
30 #define PPCB_T2GATE (1<<0)
31 #define PPCB_SPKR (1<<1)
32 #define PPCB_T2OUT (1<<5)
34 // Bits for PORT_PIT_MODE
35 #define PM_SEL_TIMER0 (0<<6)
36 #define PM_SEL_TIMER1 (1<<6)
37 #define PM_SEL_TIMER2 (2<<6)
38 #define PM_SEL_READBACK (3<<6)
39 #define PM_ACCESS_LATCH (0<<4)
40 #define PM_ACCESS_LOBYTE (1<<4)
41 #define PM_ACCESS_HIBYTE (2<<4)
42 #define PM_ACCESS_WORD (3<<4)
43 #define PM_MODE0 (0<<1)
44 #define PM_MODE1 (1<<1)
45 #define PM_MODE2 (2<<1)
46 #define PM_MODE3 (3<<1)
47 #define PM_MODE4 (4<<1)
48 #define PM_MODE5 (5<<1)
49 #define PM_CNT_BINARY (0<<0)
50 #define PM_CNT_BCD (1<<0)
51 #define PM_READ_COUNTER0 (1<<1)
52 #define PM_READ_COUNTER1 (1<<2)
53 #define PM_READ_COUNTER2 (1<<3)
54 #define PM_READ_STATUSVALUE (0<<4)
55 #define PM_READ_VALUE (1<<4)
56 #define PM_READ_STATUS (2<<4)
59 /****************************************************************
61 ****************************************************************/
63 #define CALIBRATE_COUNT 0x800 // Approx 1.7ms
65 u32 cpu_khz VAR16VISIBLE;
66 u8 no_tsc VAR16VISIBLE;
71 u32 eax, ebx, ecx, edx, cpuid_features = 0;
72 cpuid(0, &eax, &ebx, &ecx, &edx);
74 cpuid(1, &eax, &ebx, &ecx, &cpuid_features);
76 if (!(cpuid_features & CPUID_TSC)) {
77 SET_GLOBAL(no_tsc, 1);
78 SET_GLOBAL(cpu_khz, PIT_TICK_RATE / 1000);
79 dprintf(3, "386/486 class CPU. Using TSC emulation\n");
84 u8 orig = inb(PORT_PS2_CTRLB);
85 outb((orig & ~PPCB_SPKR) | PPCB_T2GATE, PORT_PS2_CTRLB);
86 /* binary, mode 0, LSB/MSB, Ch 2 */
87 outb(PM_SEL_TIMER2|PM_ACCESS_WORD|PM_MODE0|PM_CNT_BINARY, PORT_PIT_MODE);
89 outb(CALIBRATE_COUNT & 0xFF, PORT_PIT_COUNTER2);
91 outb(CALIBRATE_COUNT >> 8, PORT_PIT_COUNTER2);
93 u64 start = rdtscll();
94 while ((inb(PORT_PS2_CTRLB) & PPCB_T2OUT) == 0)
98 // Restore PORT_PS2_CTRLB
99 outb(orig, PORT_PS2_CTRLB);
101 // Store calibrated cpu khz.
102 u64 diff = end - start;
103 dprintf(6, "tsc calibrate start=%u end=%u diff=%u\n"
104 , (u32)start, (u32)end, (u32)diff);
105 u32 hz = diff * PIT_TICK_RATE / CALIBRATE_COUNT;
106 SET_GLOBAL(cpu_khz, hz / 1000);
108 dprintf(1, "CPU Mhz=%u\n", hz / 1000000);
115 u16 ebda_seg = get_ebda_seg();
117 /* read timer 0 current count */
118 ret = GET_EBDA2(ebda_seg, tsc_8254);
119 /* readback mode has slightly shifted registers, works on all 8254, readback PIT0 latch */
120 outb(PM_SEL_READBACK | PM_READ_VALUE | PM_READ_COUNTER0, PORT_PIT_MODE);
121 cnt = (inb(PORT_PIT_COUNTER0) | (inb(PORT_PIT_COUNTER0) << 8));
122 d = GET_EBDA2(ebda_seg, last_tsc_8254) - cnt;
123 /* Determine the ticks count from last invocation of this function */
124 ret += (d > 0) ? d : (PIT_TICK_INTERVAL + d);
125 SET_EBDA2(ebda_seg, last_tsc_8254, cnt);
126 SET_EBDA2(ebda_seg, tsc_8254, ret);
133 if (unlikely(GET_GLOBAL(no_tsc)))
134 return emulate_tsc();
141 return (s64)(get_tsc() - end) > 0;
147 u64 start = get_tsc();
148 u64 end = start + diff;
149 while (!check_tsc(end))
156 u64 start = get_tsc();
157 u64 end = start + diff;
158 while (!check_tsc(end))
162 void ndelay(u32 count) {
163 tscdelay(count * GET_GLOBAL(cpu_khz) / 1000000);
165 void udelay(u32 count) {
166 tscdelay(count * GET_GLOBAL(cpu_khz) / 1000);
168 void mdelay(u32 count) {
169 tscdelay(count * GET_GLOBAL(cpu_khz));
172 void nsleep(u32 count) {
173 tscsleep(count * GET_GLOBAL(cpu_khz) / 1000000);
175 void usleep(u32 count) {
176 tscsleep(count * GET_GLOBAL(cpu_khz) / 1000);
178 void msleep(u32 count) {
179 tscsleep(count * GET_GLOBAL(cpu_khz));
182 // Return the TSC value that is 'msecs' time in the future.
184 calc_future_tsc(u32 msecs)
186 u32 khz = GET_GLOBAL(cpu_khz);
187 return get_tsc() + ((u64)khz * msecs);
190 calc_future_tsc_usec(u32 usecs)
192 u32 khz = GET_GLOBAL(cpu_khz);
193 return get_tsc() + ((u64)(khz/1000) * usecs);
197 /****************************************************************
199 ****************************************************************/
204 // This function checks to see if the update-in-progress bit
205 // is set in CMOS Status Register A. If not, it returns 0.
206 // If it is set, it tries to wait until there is a transition
207 // to 0, and will return 0 if such a transition occurs. A -1
208 // is returned only after timing out. The maximum period
209 // that this bit should be set is constrained to (1984+244)
210 // useconds, but we wait for longer just to be sure.
212 if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
214 u64 end = calc_future_tsc(15);
216 if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
219 // update-in-progress never transitioned to 0
228 // timer0: binary count, 16bit count, mode 2
229 outb(PM_SEL_TIMER0|PM_ACCESS_WORD|PM_MODE2|PM_CNT_BINARY, PORT_PIT_MODE);
230 // maximum count of 0000H = 18.2Hz
231 outb(0x0, PORT_PIT_COUNTER0);
232 outb(0x0, PORT_PIT_COUNTER0);
238 outb_cmos(0x26, CMOS_STATUS_A); // 32,768Khz src, 976.5625us updates
239 u8 regB = inb_cmos(CMOS_STATUS_B);
240 outb_cmos((regB & RTC_B_DSE) | RTC_B_24HR, CMOS_STATUS_B);
241 inb_cmos(CMOS_STATUS_C);
242 inb_cmos(CMOS_STATUS_D);
248 return (val & 0xf) + ((val >> 4) * 10);
254 dprintf(3, "init timer\n");
260 u32 seconds = bcd2bin(inb_cmos(CMOS_RTC_SECONDS));
261 u32 minutes = bcd2bin(inb_cmos(CMOS_RTC_MINUTES));
262 u32 hours = bcd2bin(inb_cmos(CMOS_RTC_HOURS));
263 u32 ticks = (hours * 60 + minutes) * 60 + seconds;
264 ticks = ((u64)ticks * PIT_TICK_RATE) / PIT_TICK_INTERVAL;
265 SET_BDA(timer_counter, ticks);
267 enable_hwirq(0, FUNC16(entry_08));
268 enable_hwirq(8, FUNC16(entry_70));
272 /****************************************************************
273 * Standard clock functions
274 ****************************************************************/
276 #define TICKS_PER_DAY (u32)((u64)60*60*24*PIT_TICK_RATE / PIT_TICK_INTERVAL)
278 // Calculate the timer value at 'count' number of full timer ticks in
281 calc_future_timer_ticks(u32 count)
283 return (GET_BDA(timer_counter) + count + 1) % TICKS_PER_DAY;
286 // Return the timer value that is 'msecs' time in the future.
288 calc_future_timer(u32 msecs)
291 return GET_BDA(timer_counter);
292 u32 kticks = DIV_ROUND_UP((u64)msecs * PIT_TICK_RATE, PIT_TICK_INTERVAL);
293 u32 ticks = DIV_ROUND_UP(kticks, 1000);
294 return calc_future_timer_ticks(ticks);
297 // Check if the given timer value has passed.
301 return (((GET_BDA(timer_counter) + TICKS_PER_DAY - end) % TICKS_PER_DAY)
302 < (TICKS_PER_DAY/2));
305 // get current clock count
307 handle_1a00(struct bregs *regs)
310 u32 ticks = GET_BDA(timer_counter);
311 regs->cx = ticks >> 16;
313 regs->al = GET_BDA(timer_rollover);
314 SET_BDA(timer_rollover, 0); // reset flag
318 // Set Current Clock Count
320 handle_1a01(struct bregs *regs)
322 u32 ticks = (regs->cx << 16) | regs->dx;
323 SET_BDA(timer_counter, ticks);
324 SET_BDA(timer_rollover, 0); // reset flag
325 // XXX - should use set_code_success()?
332 handle_1a02(struct bregs *regs)
334 if (rtc_updating()) {
339 regs->dh = inb_cmos(CMOS_RTC_SECONDS);
340 regs->cl = inb_cmos(CMOS_RTC_MINUTES);
341 regs->ch = inb_cmos(CMOS_RTC_HOURS);
342 regs->dl = inb_cmos(CMOS_STATUS_B) & RTC_B_DSE;
350 handle_1a03(struct bregs *regs)
352 // Using a debugger, I notice the following masking/setting
353 // of bits in Status Register B, by setting Reg B to
354 // a few values and getting its value after INT 1A was called.
357 // before 1111 1101 0111 1101 0000 0000
358 // after 0110 0010 0110 0010 0000 0010
360 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
361 // My assumption: RegB = ((RegB & 01100000b) | 00000010b)
362 if (rtc_updating()) {
364 // fall through as if an update were not in progress
366 outb_cmos(regs->dh, CMOS_RTC_SECONDS);
367 outb_cmos(regs->cl, CMOS_RTC_MINUTES);
368 outb_cmos(regs->ch, CMOS_RTC_HOURS);
369 // Set Daylight Savings time enabled bit to requested value
370 u8 val8 = ((inb_cmos(CMOS_STATUS_B) & (RTC_B_PIE|RTC_B_AIE))
371 | RTC_B_24HR | (regs->dl & RTC_B_DSE));
372 outb_cmos(val8, CMOS_STATUS_B);
374 regs->al = val8; // val last written to Reg B
380 handle_1a04(struct bregs *regs)
383 if (rtc_updating()) {
387 regs->cl = inb_cmos(CMOS_RTC_YEAR);
388 regs->dh = inb_cmos(CMOS_RTC_MONTH);
389 regs->dl = inb_cmos(CMOS_RTC_DAY_MONTH);
390 if (CONFIG_COREBOOT) {
396 regs->ch = inb_cmos(CMOS_CENTURY);
404 handle_1a05(struct bregs *regs)
406 // Using a debugger, I notice the following masking/setting
407 // of bits in Status Register B, by setting Reg B to
408 // a few values and getting its value after INT 1A was called.
410 // try#1 try#2 try#3 try#4
411 // before 1111 1101 0111 1101 0000 0010 0000 0000
412 // after 0110 1101 0111 1101 0000 0010 0000 0000
414 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
415 // My assumption: RegB = (RegB & 01111111b)
416 if (rtc_updating()) {
421 outb_cmos(regs->cl, CMOS_RTC_YEAR);
422 outb_cmos(regs->dh, CMOS_RTC_MONTH);
423 outb_cmos(regs->dl, CMOS_RTC_DAY_MONTH);
424 if (!CONFIG_COREBOOT)
425 outb_cmos(regs->ch, CMOS_CENTURY);
426 // clear halt-clock bit
427 u8 val8 = inb_cmos(CMOS_STATUS_B) & ~RTC_B_SET;
428 outb_cmos(val8, CMOS_STATUS_B);
430 regs->al = val8; // AL = val last written to Reg B
434 // Set Alarm Time in CMOS
436 handle_1a06(struct bregs *regs)
438 // Using a debugger, I notice the following masking/setting
439 // of bits in Status Register B, by setting Reg B to
440 // a few values and getting its value after INT 1A was called.
443 // before 1101 1111 0101 1111 0000 0000
444 // after 0110 1111 0111 1111 0010 0000
446 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
447 // My assumption: RegB = ((RegB & 01111111b) | 00100000b)
448 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
450 if (val8 & RTC_B_AIE) {
451 // Alarm interrupt enabled already
455 if (rtc_updating()) {
457 // fall through as if an update were not in progress
459 outb_cmos(regs->dh, CMOS_RTC_SECONDS_ALARM);
460 outb_cmos(regs->cl, CMOS_RTC_MINUTES_ALARM);
461 outb_cmos(regs->ch, CMOS_RTC_HOURS_ALARM);
462 // enable Status Reg B alarm bit, clear halt clock bit
463 outb_cmos((val8 & ~RTC_B_SET) | RTC_B_AIE, CMOS_STATUS_B);
469 handle_1a07(struct bregs *regs)
471 // Using a debugger, I notice the following masking/setting
472 // of bits in Status Register B, by setting Reg B to
473 // a few values and getting its value after INT 1A was called.
475 // try#1 try#2 try#3 try#4
476 // before 1111 1101 0111 1101 0010 0000 0010 0010
477 // after 0100 0101 0101 0101 0000 0000 0000 0010
479 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
480 // My assumption: RegB = (RegB & 01010111b)
481 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
482 // clear clock-halt bit, disable alarm bit
483 outb_cmos(val8 & ~(RTC_B_SET|RTC_B_AIE), CMOS_STATUS_B);
485 regs->al = val8; // val last written to Reg B
491 handle_1aXX(struct bregs *regs)
493 set_unimplemented(regs);
496 // INT 1Ah Time-of-day Service Entry Point
498 handle_1a(struct bregs *regs)
500 debug_enter(regs, DEBUG_HDL_1a);
502 case 0x00: handle_1a00(regs); break;
503 case 0x01: handle_1a01(regs); break;
504 case 0x02: handle_1a02(regs); break;
505 case 0x03: handle_1a03(regs); break;
506 case 0x04: handle_1a04(regs); break;
507 case 0x05: handle_1a05(regs); break;
508 case 0x06: handle_1a06(regs); break;
509 case 0x07: handle_1a07(regs); break;
510 case 0xb1: handle_1ab1(regs); break;
511 default: handle_1aXX(regs); break;
515 // INT 08h System Timer ISR Entry Point
519 debug_isr(DEBUG_ISR_08);
523 u32 counter = GET_BDA(timer_counter);
525 // compare to one days worth of timer ticks at 18.2 hz
526 if (counter >= TICKS_PER_DAY) {
527 // there has been a midnight rollover at this point
529 SET_BDA(timer_rollover, GET_BDA(timer_rollover) + 1);
532 SET_BDA(timer_counter, counter);
536 // chain to user timer tick INT #0x1c
538 call16_simpint(0x1c, &eax, &flags);
544 /****************************************************************
546 ****************************************************************/
551 u16 ebda_seg = get_ebda_seg();
552 int count = GET_EBDA2(ebda_seg, RTCusers);
553 SET_EBDA2(ebda_seg, RTCusers, count+1);
556 // Turn on the Periodic Interrupt timer
557 u8 bRegister = inb_cmos(CMOS_STATUS_B);
558 outb_cmos(bRegister | RTC_B_PIE, CMOS_STATUS_B);
564 u16 ebda_seg = get_ebda_seg();
565 int count = GET_EBDA2(ebda_seg, RTCusers);
566 SET_EBDA2(ebda_seg, RTCusers, count-1);
569 // Clear the Periodic Interrupt.
570 u8 bRegister = inb_cmos(CMOS_STATUS_B);
571 outb_cmos(bRegister & ~RTC_B_PIE, CMOS_STATUS_B);
575 set_usertimer(u32 usecs, u16 seg, u16 offset)
577 if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING)
580 // Interval not already set.
581 SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
582 SET_BDA(user_wait_complete_flag, SEGOFF(seg, offset));
583 SET_BDA(user_wait_timeout, usecs);
589 clear_usertimer(void)
591 if (!(GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING))
593 // Turn off status byte.
594 SET_BDA(rtc_wait_flag, 0);
598 #define RET_ECLOCKINUSE 0x83
600 // Wait for CX:DX microseconds
602 handle_1586(struct bregs *regs)
604 // Use the rtc to wait for the specified time.
606 u32 count = (regs->cx << 16) | regs->dx;
607 int ret = set_usertimer(count, GET_SEG(SS), (u32)&statusflag);
609 set_code_invalid(regs, RET_ECLOCKINUSE);
617 // Set Interval requested.
619 handle_158300(struct bregs *regs)
621 int ret = set_usertimer((regs->cx << 16) | regs->dx, regs->es, regs->bx);
623 // Interval already set.
624 set_code_invalid(regs, RET_EUNSUPPORTED);
629 // Clear interval requested
631 handle_158301(struct bregs *regs)
638 handle_1583XX(struct bregs *regs)
640 set_code_unimplemented(regs, RET_EUNSUPPORTED);
645 handle_1583(struct bregs *regs)
648 case 0x00: handle_158300(regs); break;
649 case 0x01: handle_158301(regs); break;
650 default: handle_1583XX(regs); break;
654 #define USEC_PER_RTC DIV_ROUND_CLOSEST(1000000, 1024)
656 // int70h: IRQ8 - CMOS RTC
660 debug_isr(DEBUG_ISR_70);
662 // Check which modes are enabled and have occurred.
663 u8 registerB = inb_cmos(CMOS_STATUS_B);
664 u8 registerC = inb_cmos(CMOS_STATUS_C);
666 if (!(registerB & (RTC_B_PIE|RTC_B_AIE)))
668 if (registerC & RTC_B_AIE) {
669 // Handle Alarm Interrupt.
671 call16_simpint(0x4a, &eax, &flags);
673 if (!(registerC & RTC_B_PIE))
676 // Handle Periodic Interrupt.
680 if (!GET_BDA(rtc_wait_flag))
683 // Wait Interval (Int 15, AH=83) active.
684 u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds.
685 if (time < USEC_PER_RTC) {
686 // Done waiting - write to specified flag byte.
687 struct segoff_s segoff = GET_BDA(user_wait_complete_flag);
688 u16 ptr_seg = segoff.seg;
689 u8 *ptr_far = (u8*)(segoff.offset+0);
690 u8 oldval = GET_FARVAR(ptr_seg, *ptr_far);
691 SET_FARVAR(ptr_seg, *ptr_far, oldval | 0x80);
696 time -= USEC_PER_RTC;
697 SET_BDA(user_wait_timeout, time);