1 // Low level AHCI disk access
3 // Copyright (C) 2010 Gerd Hoffmann <kraxel@redhat.com>
5 // This file may be distributed under the terms of the GNU LGPLv3 license.
7 #include "types.h" // u8
8 #include "ioport.h" // inb
9 #include "util.h" // dprintf
10 #include "biosvar.h" // GET_EBDA
11 #include "pci.h" // foreachpci
12 #include "pci_ids.h" // PCI_CLASS_STORAGE_OTHER
13 #include "pci_regs.h" // PCI_INTERRUPT_LINE
14 #include "boot.h" // add_bcv_hd
15 #include "disk.h" // struct ata_s
16 #include "ata.h" // ATA_CB_STAT
17 #include "ahci.h" // CDB_CMD_READ_10
18 #include "blockcmd.h" // CDB_CMD_READ_10
20 #define AHCI_MAX_RETRIES 5
22 /****************************************************************
23 * these bits must run in both 16bit and 32bit modes
24 ****************************************************************/
26 // prepare sata command fis
27 static void sata_prep_simple(struct sata_cmd_fis *fis, u8 command)
29 memset_fl(fis, 0, sizeof(*fis));
30 SET_FLATPTR(fis->command, command);
33 static void sata_prep_readwrite(struct sata_cmd_fis *fis,
34 struct disk_op_s *op, int iswrite)
39 memset_fl(fis, 0, sizeof(*fis));
41 if (op->count >= (1<<8) || lba + op->count >= (1<<28)) {
42 SET_FLATPTR(fis->sector_count2, op->count >> 8);
43 SET_FLATPTR(fis->lba_low2, lba >> 24);
44 SET_FLATPTR(fis->lba_mid2, lba >> 32);
45 SET_FLATPTR(fis->lba_high2, lba >> 40);
47 command = (iswrite ? ATA_CMD_WRITE_DMA_EXT
48 : ATA_CMD_READ_DMA_EXT);
50 command = (iswrite ? ATA_CMD_WRITE_DMA
53 SET_FLATPTR(fis->feature, 1); /* dma */
54 SET_FLATPTR(fis->command, command);
55 SET_FLATPTR(fis->sector_count, op->count);
56 SET_FLATPTR(fis->lba_low, lba);
57 SET_FLATPTR(fis->lba_mid, lba >> 8);
58 SET_FLATPTR(fis->lba_high, lba >> 16);
59 SET_FLATPTR(fis->device, ((lba >> 24) & 0xf) | ATA_CB_DH_LBA);
62 static void sata_prep_atapi(struct sata_cmd_fis *fis, u16 blocksize)
64 memset_fl(fis, 0, sizeof(*fis));
65 SET_FLATPTR(fis->command, ATA_CMD_PACKET);
66 SET_FLATPTR(fis->feature, 1); /* dma */
67 SET_FLATPTR(fis->lba_mid, blocksize);
68 SET_FLATPTR(fis->lba_high, blocksize >> 8);
71 // ahci register access helpers
72 static u32 ahci_ctrl_readl(struct ahci_ctrl_s *ctrl, u32 reg)
74 u32 addr = GET_GLOBALFLAT(ctrl->iobase) + reg;
75 return pci_readl(addr);
78 static void ahci_ctrl_writel(struct ahci_ctrl_s *ctrl, u32 reg, u32 val)
80 u32 addr = GET_GLOBALFLAT(ctrl->iobase) + reg;
81 pci_writel(addr, val);
84 static u32 ahci_port_to_ctrl(u32 pnr, u32 port_reg)
87 ctrl_reg += pnr * 0x80;
92 static u32 ahci_port_readl(struct ahci_ctrl_s *ctrl, u32 pnr, u32 reg)
94 u32 ctrl_reg = ahci_port_to_ctrl(pnr, reg);
95 return ahci_ctrl_readl(ctrl, ctrl_reg);
98 static void ahci_port_writel(struct ahci_ctrl_s *ctrl, u32 pnr, u32 reg, u32 val)
100 u32 ctrl_reg = ahci_port_to_ctrl(pnr, reg);
101 ahci_ctrl_writel(ctrl, ctrl_reg, val);
104 // submit ahci command + wait for result
105 static int ahci_command(struct ahci_port_s *port, int iswrite, int isatapi,
106 void *buffer, u32 bsize)
108 u32 val, status, success, flags, intbits, error;
109 struct ahci_ctrl_s *ctrl = GET_GLOBAL(port->ctrl);
110 struct ahci_cmd_s *cmd = GET_GLOBAL(port->cmd);
111 struct ahci_fis_s *fis = GET_GLOBAL(port->fis);
112 struct ahci_list_s *list = GET_GLOBAL(port->list);
113 u32 pnr = GET_GLOBAL(port->pnr);
115 SET_FLATPTR(cmd->fis.reg, 0x27);
116 SET_FLATPTR(cmd->fis.pmp_type, (1 << 7)); /* cmd fis */
117 SET_FLATPTR(cmd->prdt[0].base, ((u32)buffer));
118 SET_FLATPTR(cmd->prdt[0].baseu, 0);
119 SET_FLATPTR(cmd->prdt[0].flags, bsize-1);
121 flags = ((1 << 16) | /* one prd entry */
122 (iswrite ? (1 << 6) : 0) |
123 (isatapi ? (1 << 5) : 0) |
124 (5 << 0)); /* fis length (dwords) */
125 SET_FLATPTR(list[0].flags, flags);
126 SET_FLATPTR(list[0].bytes, 0);
127 SET_FLATPTR(list[0].base, ((u32)(cmd)));
128 SET_FLATPTR(list[0].baseu, 0);
130 dprintf(2, "AHCI/%d: send cmd ...\n", pnr);
131 intbits = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT);
133 ahci_port_writel(ctrl, pnr, PORT_IRQ_STAT, intbits);
134 ahci_port_writel(ctrl, pnr, PORT_SCR_ACT, 1);
135 ahci_port_writel(ctrl, pnr, PORT_CMD_ISSUE, 1);
139 intbits = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT);
141 ahci_port_writel(ctrl, pnr, PORT_IRQ_STAT, intbits);
142 if (intbits & 0x02) {
143 status = GET_FLATPTR(fis->psfis[2]);
144 error = GET_FLATPTR(fis->psfis[3]);
147 if (intbits & 0x01) {
148 status = GET_FLATPTR(fis->rfis[2]);
149 error = GET_FLATPTR(fis->rfis[3]);
155 dprintf(2, "AHCI/%d: ... intbits 0x%x, status 0x%x ...\n",
156 pnr, intbits, status);
157 } while (status & ATA_CB_STAT_BSY);
159 success = (0x00 == (status & (ATA_CB_STAT_BSY | ATA_CB_STAT_DF |
160 ATA_CB_STAT_DRQ | ATA_CB_STAT_ERR)) &&
161 ATA_CB_STAT_RDY == (status & (ATA_CB_STAT_RDY)));
163 dprintf(2, "AHCI/%d: ... finished, status 0x%x, OK\n", pnr,
166 dprintf(2, "AHCI/%d: ... finished, status 0x%x, ERROR 0x%x\n", pnr,
169 // non-queued error recovery (AHCI 1.3 section 6.2.2.1)
170 // Clears PxCMD.ST to 0 to reset the PxCI register
171 val = ahci_port_readl(ctrl, pnr, PORT_CMD);
172 ahci_port_writel(ctrl, pnr, PORT_CMD, val & ~PORT_CMD_START);
174 // waits for PxCMD.CR to clear to 0
176 val = ahci_port_readl(ctrl, pnr, PORT_CMD);
177 if ((val & PORT_CMD_LIST_ON) == 0)
182 // Clears any error bits in PxSERR to enable capturing new errors
183 val = ahci_port_readl(ctrl, pnr, PORT_SCR_ERR);
184 ahci_port_writel(ctrl, pnr, PORT_SCR_ERR, val);
186 // Clears status bits in PxIS as appropriate
187 val = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT);
188 ahci_port_writel(ctrl, pnr, PORT_IRQ_STAT, val);
190 // If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to 1, issue
191 // a COMRESET to the device to put it in an idle state
192 val = ahci_port_readl(ctrl, pnr, PORT_TFDATA);
193 if (val & (ATA_CB_STAT_BSY | ATA_CB_STAT_DRQ)) {
194 dprintf(2, "AHCI/%d: issue comreset\n", pnr);
195 val = ahci_port_readl(ctrl, pnr, PORT_SCR_CTL);
196 // set Device Detection Initialization (DET) to 1 for 1 ms for comreset
197 ahci_port_writel(ctrl, pnr, PORT_SCR_CTL, val | 1);
199 ahci_port_writel(ctrl, pnr, PORT_SCR_CTL, val);
202 // Sets PxCMD.ST to 1 to enable issuing new commands
203 val = ahci_port_readl(ctrl, pnr, PORT_CMD);
204 ahci_port_writel(ctrl, pnr, PORT_CMD, val | PORT_CMD_START);
206 return success ? 0 : -1;
209 #define CDROM_CDB_SIZE 12
211 int ahci_cmd_data(struct disk_op_s *op, void *cdbcmd, u16 blocksize)
216 struct ahci_port_s *port = container_of(
217 op->drive_g, struct ahci_port_s, drive);
218 struct ahci_cmd_s *cmd = GET_GLOBAL(port->cmd);
222 sata_prep_atapi(&cmd->fis, blocksize);
223 for (i = 0; i < CDROM_CDB_SIZE; i++) {
224 SET_FLATPTR(cmd->atapi[i], atapi[i]);
226 rc = ahci_command(port, 0, 1, op->buf_fl,
227 op->count * blocksize);
229 return DISK_RET_EBADTRACK;
230 return DISK_RET_SUCCESS;
233 // read/write count blocks from a harddrive.
235 ahci_disk_readwrite(struct disk_op_s *op, int iswrite)
237 struct ahci_port_s *port = container_of(
238 op->drive_g, struct ahci_port_s, drive);
239 struct ahci_cmd_s *cmd = GET_GLOBAL(port->cmd);
242 sata_prep_readwrite(&cmd->fis, op, iswrite);
243 rc = ahci_command(port, iswrite, 0, op->buf_fl,
244 op->count * DISK_SECTOR_SIZE);
245 dprintf(2, "ahci disk %s, lba %6x, count %3x, buf %p, rc %d\n",
246 iswrite ? "write" : "read", (u32)op->lba, op->count, op->buf_fl, rc);
248 return DISK_RET_EBADTRACK;
249 return DISK_RET_SUCCESS;
253 int process_ahci_op(struct disk_op_s *op)
255 struct ahci_port_s *port;
261 port = container_of(op->drive_g, struct ahci_port_s, drive);
262 atapi = GET_GLOBAL(port->atapi);
265 switch (op->command) {
270 return DISK_RET_EWRITEPROTECT;
272 /* FIXME: what should we do here? */
275 return DISK_RET_SUCCESS;
277 dprintf(1, "AHCI: unknown cdrom command %d\n", op->command);
279 return DISK_RET_EPARAM;
282 switch (op->command) {
284 return ahci_disk_readwrite(op, 0);
286 return ahci_disk_readwrite(op, 1);
288 /* FIXME: what should we do here? */
292 return DISK_RET_SUCCESS;
294 dprintf(1, "AHCI: unknown disk command %d\n", op->command);
296 return DISK_RET_EPARAM;
301 /****************************************************************
302 * everything below is pure 32bit code
303 ****************************************************************/
306 ahci_port_reset(struct ahci_ctrl_s *ctrl, u32 pnr)
310 /* disable FIS + CMD */
311 val = ahci_port_readl(ctrl, pnr, PORT_CMD);
312 while (val & (PORT_CMD_FIS_RX | PORT_CMD_START |
313 PORT_CMD_FIS_ON | PORT_CMD_LIST_ON) &&
314 count < AHCI_MAX_RETRIES) {
315 val &= ~(PORT_CMD_FIS_RX | PORT_CMD_START);
316 ahci_port_writel(ctrl, pnr, PORT_CMD, val);
318 val = ahci_port_readl(ctrl, pnr, PORT_CMD);
323 val = ahci_port_readl(ctrl, pnr, PORT_SCR_ERR);
325 ahci_port_writel(ctrl, pnr, PORT_SCR_ERR, val);
327 /* disable + clear IRQs */
328 ahci_port_writel(ctrl, pnr, PORT_IRQ_MASK, val);
329 val = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT);
331 ahci_port_writel(ctrl, pnr, PORT_IRQ_STAT, val);
335 ahci_port_probe(struct ahci_ctrl_s *ctrl, u32 pnr)
339 val = ahci_port_readl(ctrl, pnr, PORT_TFDATA);
340 while (val & ((1 << 7) /* BSY */ |
341 (1 << 3) /* DRQ */)) {
343 val = ahci_port_readl(ctrl, pnr, PORT_TFDATA);
345 if (count >= AHCI_MAX_RETRIES)
349 val = ahci_port_readl(ctrl, pnr, PORT_SCR_STAT);
350 if ((val & 0x07) != 0x03)
357 static struct ahci_port_s*
358 ahci_port_init(struct ahci_ctrl_s *ctrl, u32 pnr)
360 struct ahci_port_s *port = malloc_fseg(sizeof(*port));
361 char model[MAXMODEL+1];
372 port->list = memalign_low(1024, 1024);
373 port->fis = memalign_low(256, 256);
374 port->cmd = memalign_low(256, 256);
375 if (port->list == NULL || port->fis == NULL || port->cmd == NULL) {
379 memset(port->list, 0, 1024);
380 memset(port->fis, 0, 256);
381 memset(port->cmd, 0, 256);
383 ahci_port_writel(ctrl, pnr, PORT_LST_ADDR, (u32)port->list);
384 ahci_port_writel(ctrl, pnr, PORT_FIS_ADDR, (u32)port->fis);
385 val = ahci_port_readl(ctrl, pnr, PORT_CMD);
386 val |= PORT_CMD_FIS_RX;
387 ahci_port_writel(ctrl, pnr, PORT_CMD, val);
388 val |= PORT_CMD_START;
389 ahci_port_writel(ctrl, pnr, PORT_CMD, val);
391 sata_prep_simple(&port->cmd->fis, ATA_CMD_IDENTIFY_PACKET_DEVICE);
392 rc = ahci_command(port, 0, 0, buffer, sizeof(buffer));
397 sata_prep_simple(&port->cmd->fis, ATA_CMD_IDENTIFY_DEVICE);
398 rc = ahci_command(port, 0, 0, buffer, sizeof(buffer));
403 port->drive.type = DTYPE_AHCI;
404 port->drive.cntl_id = pnr;
405 port->drive.removable = (buffer[0] & 0x80) ? 1 : 0;
409 port->drive.blksize = DISK_SECTOR_SIZE;
410 port->drive.pchs.cylinders = buffer[1];
411 port->drive.pchs.heads = buffer[3];
412 port->drive.pchs.spt = buffer[6];
415 if (buffer[83] & (1 << 10)) // word 83 - lba48 support
416 sectors = *(u64*)&buffer[100]; // word 100-103
418 sectors = *(u32*)&buffer[60]; // word 60 and word 61
419 port->drive.sectors = sectors;
420 u64 adjsize = sectors >> 11;
421 char adjprefix = 'M';
422 if (adjsize >= (1 << 16)) {
426 char *desc = znprintf(MAXDESCSIZE
427 , "AHCI/%d: %s ATA-%d Hard-Disk (%u %ciBytes)"
429 , ata_extract_model(model, MAXMODEL, buffer)
430 , ata_extract_version(buffer)
431 , (u32)adjsize, adjprefix);
432 dprintf(1, "%s\n", desc);
434 // Register with bcv system.
435 boot_add_hd(&port->drive, desc, -1);
437 // found cdrom (atapi)
438 port->drive.blksize = CDROM_SECTOR_SIZE;
439 port->drive.sectors = (u64)-1;
440 u8 iscd = ((buffer[0] >> 8) & 0x1f) == 0x05;
441 char *desc = znprintf(MAXDESCSIZE
442 , "DVD/CD [AHCI/%d: %s ATAPI-%d %s]"
444 , ata_extract_model(model, MAXMODEL, buffer)
445 , ata_extract_version(buffer)
446 , (iscd ? "DVD/CD" : "Device"));
447 dprintf(1, "%s\n", desc);
451 boot_add_cd(&port->drive, desc, -1);
457 dprintf(1, "AHCI/%d: init failure, reset\n", port->pnr);
458 ahci_port_reset(ctrl, pnr);
462 // Detect any drives attached to a given controller.
464 ahci_detect(void *data)
466 struct ahci_ctrl_s *ctrl = data;
467 struct ahci_port_s *port;
471 max = ctrl->caps & 0x1f;
472 for (pnr = 0; pnr <= max; pnr++) {
473 if (!(ctrl->ports & (1 << pnr)))
475 dprintf(2, "AHCI/%d: probing\n", pnr);
476 ahci_port_reset(ctrl, pnr);
477 rc = ahci_port_probe(ctrl, pnr);
478 dprintf(1, "AHCI/%d: link %s\n", pnr, rc == 0 ? "up" : "down");
481 port = ahci_port_init(ctrl, pnr);
485 // Initialize an ata controller and detect its drives.
487 ahci_init_controller(int bdf)
489 struct ahci_ctrl_s *ctrl = malloc_fseg(sizeof(*ctrl));
497 ctrl->iobase = pci_config_readl(bdf, PCI_BASE_ADDRESS_5);
498 ctrl->irq = pci_config_readb(bdf, PCI_INTERRUPT_LINE);
499 dprintf(1, "AHCI controller at %02x.%x, iobase %x, irq %d\n",
500 bdf >> 3, bdf & 7, ctrl->iobase, ctrl->irq);
502 pci_config_maskw(bdf, PCI_COMMAND, 0,
503 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
505 val = ahci_ctrl_readl(ctrl, HOST_CTL);
506 ahci_ctrl_writel(ctrl, HOST_CTL, val | HOST_CTL_AHCI_EN);
508 ctrl->caps = ahci_ctrl_readl(ctrl, HOST_CAP);
509 ctrl->ports = ahci_ctrl_readl(ctrl, HOST_PORTS_IMPL);
510 dprintf(2, "AHCI: cap 0x%x, ports_impl 0x%x\n",
511 ctrl->caps, ctrl->ports);
513 run_thread(ahci_detect, ctrl);
516 // Locate and init ahci controllers.
520 // Scan PCI bus for ATA adapters
521 struct pci_device *pci;
523 if (pci->class != PCI_CLASS_STORAGE_SATA)
525 if (pci->prog_if != 1 /* AHCI rev 1 */)
527 ahci_init_controller(pci->bdf);
538 dprintf(3, "init ahci\n");