1 // Support for generating ACPI tables (on emulators)
3 // Copyright (C) 2008,2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "acpi.h" // struct rsdp_descriptor
9 #include "util.h" // memcpy
10 #include "pci.h" // pci_find_device
11 #include "biosvar.h" // GET_EBDA
12 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
13 #include "pci_regs.h" // PCI_INTERRUPT_LINE
16 /****************************************************/
17 /* ACPI tables init */
19 /* Table structure from Linux kernel (the ACPI tables are under the
22 #define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
23 u32 signature; /* ACPI signature (4 ASCII characters) */ \
24 u32 length; /* Length of table, in bytes, including header */ \
25 u8 revision; /* ACPI Specification minor version # */ \
26 u8 checksum; /* To make sum of entire table == 0 */ \
27 u8 oem_id [6]; /* OEM identification */ \
28 u8 oem_table_id [8]; /* OEM table identification */ \
29 u32 oem_revision; /* OEM revision number */ \
30 u8 asl_compiler_id [4]; /* ASL compiler vendor ID */ \
31 u32 asl_compiler_revision; /* ASL compiler revision number */
34 struct acpi_table_header /* ACPI common table header */
40 * ACPI 1.0 Root System Description Table (RSDT)
42 #define RSDT_SIGNATURE 0x54445352 // RSDT
43 struct rsdt_descriptor_rev1
45 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
46 u32 table_offset_entry[0]; /* Array of pointers to other */
51 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
53 #define FACS_SIGNATURE 0x53434146 // FACS
54 struct facs_descriptor_rev1
56 u32 signature; /* ACPI Signature */
57 u32 length; /* Length of structure, in bytes */
58 u32 hardware_signature; /* Hardware configuration signature */
59 u32 firmware_waking_vector; /* ACPI OS waking vector */
60 u32 global_lock; /* Global Lock */
61 u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */
62 u32 reserved1 : 31; /* Must be 0 */
63 u8 resverved3 [40]; /* Reserved - must be zero */
68 * ACPI 1.0 Fixed ACPI Description Table (FADT)
70 #define FACP_SIGNATURE 0x50434146 // FACP
71 struct fadt_descriptor_rev1
73 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
74 u32 firmware_ctrl; /* Physical address of FACS */
75 u32 dsdt; /* Physical address of DSDT */
76 u8 model; /* System Interrupt Model */
77 u8 reserved1; /* Reserved */
78 u16 sci_int; /* System vector of SCI interrupt */
79 u32 smi_cmd; /* Port address of SMI command port */
80 u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */
81 u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */
82 u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
83 u8 reserved2; /* Reserved - must be zero */
84 u32 pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
85 u32 pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
86 u32 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
87 u32 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
88 u32 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
89 u32 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
90 u32 gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
91 u32 gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
92 u8 pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
93 u8 pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
94 u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
95 u8 pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
96 u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
97 u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
98 u8 gpe1_base; /* Offset in gpe model where gpe1 events start */
99 u8 reserved3; /* Reserved */
100 u16 plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
101 u16 plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
102 u16 flush_size; /* Size of area read to flush caches */
103 u16 flush_stride; /* Stride used in flushing caches */
104 u8 duty_offset; /* Bit location of duty cycle field in p_cnt reg */
105 u8 duty_width; /* Bit width of duty cycle field in p_cnt reg */
106 u8 day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
107 u8 mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
108 u8 century; /* Index to century in RTC CMOS RAM */
109 u8 reserved4; /* Reserved */
110 u8 reserved4a; /* Reserved */
111 u8 reserved4b; /* Reserved */
113 u32 wb_invd : 1; /* The wbinvd instruction works properly */
114 u32 wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
115 u32 proc_c1 : 1; /* All processors support C1 state */
116 u32 plvl2_up : 1; /* C2 state works on MP system */
117 u32 pwr_button : 1; /* Power button is handled as a generic feature */
118 u32 sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
119 u32 fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
120 u32 rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
121 u32 tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
122 u32 reserved5 : 23; /* Reserved - must be zero */
129 * MADT values and structures
132 /* Values for MADT PCATCompat */
135 #define MULTIPLE_APIC 1
140 #define APIC_SIGNATURE 0x43495041 // APIC
141 struct multiple_apic_table
143 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
144 u32 local_apic_address; /* Physical address of local APIC */
146 u32 PCATcompat : 1; /* A one indicates system also has dual 8259s */
154 /* Values for Type in APIC_HEADER_DEF */
156 #define APIC_PROCESSOR 0
158 #define APIC_XRUPT_OVERRIDE 2
160 #define APIC_LOCAL_NMI 4
161 #define APIC_ADDRESS_OVERRIDE 5
162 #define APIC_IO_SAPIC 6
163 #define APIC_LOCAL_SAPIC 7
164 #define APIC_XRUPT_SOURCE 8
165 #define APIC_RESERVED 9 /* 9 and greater are reserved */
168 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
170 #define APIC_HEADER_DEF /* Common APIC sub-structure header */\
174 /* Sub-structures for MADT */
176 struct madt_processor_apic
179 u8 processor_id; /* ACPI processor id */
180 u8 local_apic_id; /* Processor's local APIC id */
182 u32 processor_enabled: 1; /* Processor is usable if set */
183 u32 reserved2 : 31; /* Reserved, must be zero */
192 u8 io_apic_id; /* I/O APIC ID */
193 u8 reserved; /* Reserved - must be zero */
194 u32 address; /* APIC physical address */
195 u32 interrupt; /* Global system interrupt where INTI
201 #define PCI_ISA_IRQ_MASK 0x0e20
203 #define PCI_ISA_IRQ_MASK 0x0000
206 struct madt_intsrcovr {
214 #include "acpi-dsdt.hex"
216 static inline u16 cpu_to_le16(u16 x)
221 static inline u32 cpu_to_le32(u32 x)
227 build_header(struct acpi_table_header *h, u32 sig, int len, u8 rev)
230 h->length = cpu_to_le32(len);
232 memcpy(h->oem_id, CONFIG_APPNAME6, 6);
233 memcpy(h->oem_table_id, CONFIG_APPNAME4, 4);
234 memcpy(h->asl_compiler_id, CONFIG_APPNAME4, 4);
235 memcpy(h->oem_table_id + 4, (void*)&sig, 4);
236 h->oem_revision = cpu_to_le32(1);
237 h->asl_compiler_revision = cpu_to_le32(1);
238 h->checksum -= checksum(h, len);
244 struct fadt_descriptor_rev1 *fadt = malloc_high(sizeof(*fadt));
245 struct facs_descriptor_rev1 *facs = memalign_high(64, sizeof(*facs));
246 void *dsdt = malloc_high(sizeof(AmlCode));
248 if (!fadt || !facs || !dsdt) {
249 dprintf(1, "Not enough memory for fadt!\n");
254 memset(facs, 0, sizeof(*facs));
255 facs->signature = FACS_SIGNATURE;
256 facs->length = cpu_to_le32(sizeof(*facs));
259 memcpy(dsdt, AmlCode, sizeof(AmlCode));
262 memset(fadt, 0, sizeof(*fadt));
263 fadt->firmware_ctrl = cpu_to_le32((u32)facs);
264 fadt->dsdt = cpu_to_le32((u32)dsdt);
267 int pm_sci_int = pci_config_readb(bdf, PCI_INTERRUPT_LINE);
268 fadt->sci_int = cpu_to_le16(pm_sci_int);
269 fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
270 fadt->acpi_enable = 0xf1;
271 fadt->acpi_disable = 0xf0;
272 fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE);
273 fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04);
274 fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08);
275 fadt->pm1_evt_len = 4;
276 fadt->pm1_cnt_len = 2;
277 fadt->pm_tmr_len = 4;
278 fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
279 fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
280 /* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
281 fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6));
283 build_header((void*)fadt, FACP_SIGNATURE, sizeof(*fadt), 1);
291 int smp_cpus = CountCPUs;
292 int madt_size = (sizeof(struct multiple_apic_table)
293 + sizeof(struct madt_processor_apic) * smp_cpus
294 + sizeof(struct madt_io_apic)
295 + sizeof(struct madt_intsrcovr) * 16);
296 struct multiple_apic_table *madt = malloc_high(madt_size);
298 dprintf(1, "Not enough memory for madt!\n");
301 memset(madt, 0, madt_size);
302 madt->local_apic_address = cpu_to_le32(BUILD_APIC_ADDR);
303 madt->flags = cpu_to_le32(1);
304 struct madt_processor_apic *apic = (void*)&madt[1];
306 for (i=0; i<smp_cpus; i++) {
307 apic->type = APIC_PROCESSOR;
308 apic->length = sizeof(*apic);
309 apic->processor_id = i;
310 apic->local_apic_id = i;
311 apic->flags = cpu_to_le32(1);
314 struct madt_io_apic *io_apic = (void*)apic;
315 io_apic->type = APIC_IO;
316 io_apic->length = sizeof(*io_apic);
317 io_apic->io_apic_id = smp_cpus;
318 io_apic->address = cpu_to_le32(BUILD_IOAPIC_ADDR);
319 io_apic->interrupt = cpu_to_le32(0);
321 struct madt_intsrcovr *intsrcovr = (void*)&io_apic[1];
323 memset(intsrcovr, 0, sizeof(*intsrcovr));
324 intsrcovr->type = APIC_XRUPT_OVERRIDE;
325 intsrcovr->length = sizeof(*intsrcovr);
326 intsrcovr->source = 0;
328 intsrcovr->flags = 0; /* conforms to bus specifications */
331 for (i = 1; i < 16; i++) {
332 if (!(PCI_ISA_IRQ_MASK & (1 << i)))
333 /* No need for a INT source override structure. */
335 memset(intsrcovr, 0, sizeof(*intsrcovr));
336 intsrcovr->type = APIC_XRUPT_OVERRIDE;
337 intsrcovr->length = sizeof(*intsrcovr);
338 intsrcovr->source = i;
340 intsrcovr->flags = 0xd; /* active high, level triggered */
344 build_header((void*)madt, APIC_SIGNATURE, (void*)intsrcovr - (void*)madt, 1);
348 #define SSDT_SIGNATURE 0x54445353 // SSDT
352 int smp_cpus = CountCPUs;
353 int acpi_cpus = smp_cpus > 0xff ? 0xff : smp_cpus;
354 // calculate the length of processor block and scope block
355 // excluding PkgLength
356 int cpu_length = 13 * acpi_cpus + 4;
358 int length = sizeof(struct acpi_table_header) + 3 + cpu_length;
359 u8 *ssdt = malloc_high(length);
361 dprintf(1, "No space for ssdt!\n");
366 ssdt_ptr[9] = 0; // checksum;
367 ssdt_ptr += sizeof(struct acpi_table_header);
369 // build processor scope header
370 *(ssdt_ptr++) = 0x10; // ScopeOp
371 if (cpu_length <= 0x3e) {
372 *(ssdt_ptr++) = cpu_length + 1;
374 *(ssdt_ptr++) = 0x7F;
375 *(ssdt_ptr++) = (cpu_length + 2) >> 6;
377 *(ssdt_ptr++) = '_'; // Name
382 // build object for each processor
384 for (i=0; i<acpi_cpus; i++) {
385 *(ssdt_ptr++) = 0x5B; // ProcessorOp
386 *(ssdt_ptr++) = 0x83;
387 *(ssdt_ptr++) = 0x0B; // Length
388 *(ssdt_ptr++) = 'C'; // Name (CPUxx)
391 *(ssdt_ptr++) = (i >> 4) < 0xa ? (i >> 4) + '0' : (i >> 4) + 'A' - 0xa;
394 *(ssdt_ptr++) = (i & 0xf) < 0xa ? (i & 0xf) + '0' : (i & 0xf) + 'A' - 0xa;
396 *(ssdt_ptr++) = 0x10; // Processor block address
397 *(ssdt_ptr++) = 0xb0;
400 *(ssdt_ptr++) = 6; // Processor block length
403 build_header((void*)ssdt, SSDT_SIGNATURE, ssdt_ptr - ssdt, 1);
408 struct rsdp_descriptor *RsdpAddr;
410 #define MAX_ACPI_TABLES 20
417 dprintf(3, "init ACPI tables\n");
419 // This code is hardcoded for PIIX4 Power Management device.
420 int bdf = pci_find_device(PCI_VENDOR_ID_INTEL
421 , PCI_DEVICE_ID_INTEL_82371AB_3);
426 // Create initial rsdt table
427 struct rsdp_descriptor *rsdp = malloc_fseg(sizeof(*rsdp));
429 dprintf(1, "Not enough memory for acpi rsdp table!\n");
433 u32 tables[MAX_ACPI_TABLES], tbl_idx = 0;
435 #define ACPI_INIT_TABLE(X) \
437 tables[tbl_idx] = (u32)(X); \
438 if (tables[tbl_idx]) \
443 ACPI_INIT_TABLE(build_fadt(bdf));
444 ACPI_INIT_TABLE(build_ssdt());
445 ACPI_INIT_TABLE(build_madt());
447 u16 i, external_tables = qemu_cfg_acpi_additional_tables();
449 for(i = 0; i < external_tables; i++) {
450 u16 len = qemu_cfg_next_acpi_table_len();
451 void *addr = malloc_high(len);
453 dprintf(1, "Not enogh memory of ext acpi table of size %d!\n", len);
456 ACPI_INIT_TABLE(qemu_cfg_next_acpi_table_load(addr, len));
457 if (tbl_idx == MAX_ACPI_TABLES) {
458 dprintf(1, "To many external table!\n");
463 struct rsdt_descriptor_rev1 *rsdt;
464 size_t rsdt_len = sizeof(*rsdt) + sizeof(u32) * tbl_idx;
465 rsdt = malloc_high(rsdt_len);
468 dprintf(1, "Not enough memory for acpi rsdt table!\n");
471 memset(rsdt, 0, rsdt_len);
472 memcpy(rsdt->table_offset_entry, tables, sizeof(u32) * tbl_idx);
474 build_header((void*)rsdt, RSDT_SIGNATURE, rsdt_len, 1);
476 // Build rsdp pointer table
477 memset(rsdp, 0, sizeof(*rsdp));
478 rsdp->signature = RSDP_SIGNATURE;
479 memcpy(rsdp->oem_id, CONFIG_APPNAME6, 6);
480 rsdp->rsdt_physical_address = cpu_to_le32((u32)rsdt);
481 rsdp->checksum -= checksum(rsdp, 20);
483 dprintf(1, "ACPI tables: RSDP=%p RSDT=%p\n", rsdp, rsdt);
489 dprintf(4, "rsdp=%p\n", RsdpAddr);
490 if (!RsdpAddr || RsdpAddr->signature != RSDP_SIGNATURE)
492 struct rsdt_descriptor_rev1 *rsdt = (void*)RsdpAddr->rsdt_physical_address;
493 dprintf(4, "rsdt=%p\n", rsdt);
494 if (!rsdt || rsdt->signature != RSDT_SIGNATURE)
496 void *end = (void*)rsdt + rsdt->length;
498 for (i=0; (void*)&rsdt->table_offset_entry[i] < end; i++) {
499 struct fadt_descriptor_rev1 *fadt = (void*)rsdt->table_offset_entry[i];
500 if (!fadt || fadt->signature != FACP_SIGNATURE)
502 dprintf(4, "fadt=%p\n", fadt);
503 struct facs_descriptor_rev1 *facs = (void*)fadt->firmware_ctrl;
504 dprintf(4, "facs=%p\n", facs);
505 if (! facs || facs->signature != FACS_SIGNATURE)
508 dprintf(4, "resume addr=%d\n", facs->firmware_waking_vector);
509 return facs->firmware_waking_vector;