5 * Copyright (C) 2008 Nguyen Anh Quynh <aquynh@gmail.com>
6 * Copyright (C) 2002 MandrakeSoft S.A.
8 * This file may be distributed under the terms of the GNU GPLv3 license.
14 #include "util.h" // memcpy
15 #include "smp.h" // smp_cpus
16 #include "acpi.h" // ACPI_DATA_SIZE
17 #include "../out/acpi-dsdt.hex"
19 #define SMI_CMD_IO_ADDR 0xb2
23 /****************************************************/
24 /* ACPI tables init */
26 /* Table structure from Linux kernel (the ACPI tables are under the
28 #define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
29 u8 signature [4]; /* ACPI signature (4 ASCII characters) */\
30 u32 length; /* Length of table, in bytes, including header */\
31 u8 revision; /* ACPI Specification minor version # */\
32 u8 checksum; /* To make sum of entire table == 0 */\
33 u8 oem_id [6]; /* OEM identification */\
34 u8 oem_table_id [8]; /* OEM table identification */\
35 u32 oem_revision; /* OEM revision number */\
36 u8 asl_compiler_id [4]; /* ASL compiler vendor ID */\
37 u32 asl_compiler_revision; /* ASL compiler revision number */
39 /* ACPI common table header */
40 struct acpi_table_header {
44 /* Root System Descriptor Pointer */
45 struct rsdp_descriptor {
46 u8 signature [8]; /* ACPI signature, contains "RSD PTR " */
47 u8 checksum; /* To make sum of struct == 0 */
48 u8 oem_id [6]; /* OEM identification */
49 u8 revision; /* Must be 0 for 1.0, 2 for 2.0 */
50 u32 rsdt_physical_address; /* 32-bit physical address of RSDT */
51 u32 length; /* XSDT Length in bytes including hdr */
52 u64 xsdt_physical_address; /* 64-bit physical address of XSDT */
53 u8 extended_checksum; /* Checksum of entire table */
54 u8 reserved [3]; /* Reserved field must be 0 */
57 /* ACPI 1.0 Root System Description Table (RSDT) */
58 struct rsdt_descriptor_rev1 {
59 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
60 u32 table_offset_entry [3]; /* Array of pointers to other */
64 /* ACPI 1.0 Firmware ACPI Control Structure (FACS) */
65 struct facs_descriptor_rev1 {
66 u8 signature[4]; /* ACPI Signature */
67 u32 length; /* Length of structure, in bytes */
68 u32 hardware_signature; /* Hardware configuration signature */
69 u32 firmware_waking_vector; /* ACPI OS waking vector */
70 u32 global_lock; /* Global Lock */
71 u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */
72 u32 reserved1 : 31; /* Must be 0 */
73 u8 resverved3 [40]; /* Reserved - must be zero */
77 /* ACPI 1.0 Fixed ACPI Description Table (FADT) */
78 struct fadt_descriptor_rev1 {
79 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
80 u32 firmware_ctrl; /* Physical address of FACS */
81 u32 dsdt; /* Physical address of DSDT */
82 u8 model; /* System Interrupt Model */
83 u8 reserved1; /* Reserved */
84 u16 sci_int; /* System vector of SCI interrupt */
85 u32 smi_cmd; /* Port address of SMI command port */
86 u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */
87 u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */
88 u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
89 u8 reserved2; /* Reserved - must be zero */
90 u32 pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
91 u32 pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
92 u32 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
93 u32 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
94 u32 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
95 u32 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
96 u32 gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
97 u32 gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
98 u8 pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
99 u8 pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
100 u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
101 u8 pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
102 u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
103 u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
104 u8 gpe1_base; /* Offset in gpe model where gpe1 events start */
105 u8 reserved3; /* Reserved */
106 u16 plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
107 u16 plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
108 u16 flush_size; /* Size of area read to flush caches */
109 u16 flush_stride; /* Stride used in flushing caches */
110 u8 duty_offset; /* Bit location of duty cycle field in p_cnt reg */
111 u8 duty_width; /* Bit width of duty cycle field in p_cnt reg */
112 u8 day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
113 u8 mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
114 u8 century; /* Index to century in RTC CMOS RAM */
115 u8 reserved4; /* Reserved */
116 u8 reserved4a; /* Reserved */
117 u8 reserved4b; /* Reserved */
119 u32 wb_invd : 1; /* The wbinvd instruction works properly */
120 u32 wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
121 u32 proc_c1 : 1; /* All processors support C1 state */
122 u32 plvl2_up : 1; /* C2 state works on MP system */
123 u32 pwr_button : 1; /* Power button is handled as a generic feature */
124 u32 sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
125 u32 fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
126 u32 rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
127 u32 tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
128 u32 reserved5 : 23; /* Reserved - must be zero */
135 * MADT values and structures
138 /* Values for MADT PCATCompat */
141 #define MULTIPLE_APIC 1
146 struct multiple_apic_table {
147 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
148 u32 local_apic_address; /* Physical address of local APIC */
150 u32 PCATcompat : 1; /* A one indicates system also has dual 8259s */
158 /* Values for Type in APIC_HEADER_DEF */
159 #define APIC_PROCESSOR 0
161 #define APIC_XRUPT_OVERRIDE 2
163 #define APIC_LOCAL_NMI 4
164 #define APIC_ADDRESS_OVERRIDE 5
165 #define APIC_IO_SAPIC 6
166 #define APIC_LOCAL_SAPIC 7
167 #define APIC_XRUPT_SOURCE 8
168 #define APIC_RESERVED 9 /* 9 and greater are reserved */
171 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
173 #define APIC_HEADER_DEF /* Common APIC sub-structure header */\
177 /* Sub-structures for MADT */
178 struct madt_processor_apic {
180 u8 processor_id; /* ACPI processor id */
181 u8 local_apic_id; /* Processor's local APIC id */
183 u32 processor_enabled: 1; /* Processor is usable if set */
184 u32 reserved2 : 31; /* Reserved, must be zero */
190 struct madt_io_apic {
192 u8 io_apic_id; /* I/O APIC ID */
193 u8 reserved; /* Reserved - must be zero */
194 u32 address; /* APIC physical address */
195 u32 interrupt; /* Global system interrupt where INTI lines start */
199 u16 cpu_to_le16(u16 x)
205 u32 cpu_to_le32(u32 x)
211 acpi_checksum(const u8 *data, int len)
216 for(i = 0; i < len; i++)
219 return (-sum) & 0xff;
223 acpi_build_table_header(struct acpi_table_header *h,
224 char *sig, int len, u8 rev)
226 memcpy(h->signature, sig, 4);
227 h->length = cpu_to_le32(len);
230 memcpy(h->oem_id, "QEMU ", 6);
231 memcpy(h->oem_table_id, "QEMU", 4);
233 memcpy(h->oem_id, "BOCHS ", 6);
234 memcpy(h->oem_table_id, "BXPC", 4);
236 memcpy(h->oem_table_id + 4, sig, 4);
237 h->oem_revision = cpu_to_le32(1);
239 memcpy(h->asl_compiler_id, "QEMU", 4);
241 memcpy(h->asl_compiler_id, "BXPC", 4);
243 h->asl_compiler_revision = cpu_to_le32(1);
244 h->checksum = acpi_checksum((void *)h, len);
248 acpi_build_processor_ssdt(u8 *ssdt)
252 int acpi_cpus = smp_cpus > 0xff ? 0xff : smp_cpus;
254 ssdt_ptr[9] = 0; // checksum;
255 ssdt_ptr += sizeof(struct acpi_table_header);
257 // caluculate the length of processor block and scope block excluding PkgLength
258 length = 0x0d * acpi_cpus + 4;
260 // build processor scope header
261 *(ssdt_ptr++) = 0x10; // ScopeOp
262 if (length <= 0x3e) {
263 *(ssdt_ptr++) = length + 1;
265 *(ssdt_ptr++) = 0x7F;
266 *(ssdt_ptr++) = (length + 2) >> 6;
268 *(ssdt_ptr++) = '_'; // Name
273 // build object for each processor
274 for(i=0;i<acpi_cpus;i++) {
275 *(ssdt_ptr++) = 0x5B; // ProcessorOp
276 *(ssdt_ptr++) = 0x83;
277 *(ssdt_ptr++) = 0x0B; // Length
278 *(ssdt_ptr++) = 'C'; // Name (CPUxx)
281 *(ssdt_ptr++) = (i >> 4) < 0xa ? (i >> 4) + '0' : (i >> 4) + 'A' - 0xa;
284 *(ssdt_ptr++) = (i & 0xf) < 0xa ? (i & 0xf) + '0' : (i & 0xf) + 'A' - 0xa;
286 *(ssdt_ptr++) = 0x10; // Processor block address
287 *(ssdt_ptr++) = 0xb0;
290 *(ssdt_ptr++) = 6; // Processor block length
293 acpi_build_table_header((struct acpi_table_header *)ssdt,
294 "SSDT", ssdt_ptr - ssdt, 1);
296 return ssdt_ptr - ssdt;
302 struct rsdp_descriptor *rsdp;
303 struct rsdt_descriptor_rev1 *rsdt;
304 struct fadt_descriptor_rev1 *fadt;
305 struct facs_descriptor_rev1 *facs;
306 struct multiple_apic_table *madt;
307 struct madt_processor_apic *apic;
308 struct madt_io_apic *io_apic;
310 /* base_addr must be a multiple of 4KB */
311 u32 base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr, ssdt_addr;
312 u32 acpi_tables_size, madt_addr, madt_size;
315 /* reserve memory space for tables */
316 #ifdef CONFIG_USE_EBDA_TABLES
317 ebda_cur_addr = align(ebda_cur_addr, 16);
318 rsdp = (void *)(ebda_cur_addr);
319 ebda_cur_addr += sizeof(*rsdp);
321 bios_table_cur_addr = align(bios_table_cur_addr, 16);
322 rsdp = (void *)(bios_table_cur_addr);
323 bios_table_cur_addr += sizeof(*rsdp);
326 addr = base_addr = ram_size - ACPI_DATA_SIZE;
328 rsdt = (void *)(addr);
329 addr += sizeof(*rsdt);
332 fadt = (void *)(addr);
333 addr += sizeof(*fadt);
335 /* XXX: FACS should be in RAM */
336 addr = (addr + 63) & ~63; /* 64 byte alignment for FACS */
338 facs = (void *)(addr);
339 addr += sizeof(*facs);
342 dsdt = (void *)(addr);
343 addr += sizeof(AmlCode);
346 ssdt = (void *)(addr);
347 addr += acpi_build_processor_ssdt(ssdt);
349 addr = (addr + 7) & ~7;
351 madt_size = sizeof(*madt) +
352 sizeof(struct madt_processor_apic) * smp_cpus +
353 sizeof(struct madt_io_apic);
354 madt = (void *)(addr);
357 acpi_tables_size = addr - base_addr;
359 BX_INFO("ACPI tables: RSDP addr=0x%08lx ACPI DATA addr=0x%08lx size=0x%x\n",
361 (unsigned long)rsdt, acpi_tables_size);
364 memset(rsdp, 0, sizeof(*rsdp));
365 memcpy(rsdp->signature, "RSD PTR ", 8);
367 memcpy(rsdp->oem_id, "QEMU ", 6);
369 memcpy(rsdp->oem_id, "BOCHS ", 6);
371 rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr);
372 rsdp->checksum = acpi_checksum((void *)rsdp, 20);
375 memset(rsdt, 0, sizeof(*rsdt));
376 rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
377 rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
378 rsdt->table_offset_entry[2] = cpu_to_le32(ssdt_addr);
379 acpi_build_table_header((struct acpi_table_header *)rsdt,
380 "RSDT", sizeof(*rsdt), 1);
383 memset(fadt, 0, sizeof(*fadt));
384 fadt->firmware_ctrl = cpu_to_le32(facs_addr);
385 fadt->dsdt = cpu_to_le32(dsdt_addr);
388 fadt->sci_int = cpu_to_le16(pm_sci_int);
389 fadt->smi_cmd = cpu_to_le32(SMI_CMD_IO_ADDR);
390 fadt->acpi_enable = 0xf1;
391 fadt->acpi_disable = 0xf0;
392 fadt->pm1a_evt_blk = cpu_to_le32(pm_io_base);
393 fadt->pm1a_cnt_blk = cpu_to_le32(pm_io_base + 0x04);
394 fadt->pm_tmr_blk = cpu_to_le32(pm_io_base + 0x08);
395 fadt->pm1_evt_len = 4;
396 fadt->pm1_cnt_len = 2;
397 fadt->pm_tmr_len = 4;
398 fadt->plvl2_lat = cpu_to_le16(50);
399 fadt->plvl3_lat = cpu_to_le16(50);
400 fadt->plvl3_lat = cpu_to_le16(50);
401 /* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
402 fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6));
403 acpi_build_table_header((struct acpi_table_header *)fadt, "FACP",
407 memset(facs, 0, sizeof(*facs));
408 memcpy(facs->signature, "FACS", 4);
409 facs->length = cpu_to_le32(sizeof(*facs));
412 memcpy(dsdt, AmlCode, sizeof(AmlCode));
415 memset(madt, 0, madt_size);
416 madt->local_apic_address = cpu_to_le32(0xfee00000);
417 madt->flags = cpu_to_le32(1);
418 apic = (void *)(madt + 1);
420 for (i=0; i<smp_cpus; i++) {
421 apic->type = APIC_PROCESSOR;
422 apic->length = sizeof(*apic);
423 apic->processor_id = i;
424 apic->local_apic_id = i;
425 apic->flags = cpu_to_le32(1);
429 io_apic = (void *)apic;
430 io_apic->type = APIC_IO;
431 io_apic->length = sizeof(*io_apic);
432 io_apic->io_apic_id = smp_cpus;
433 io_apic->address = cpu_to_le32(0xfec00000);
434 io_apic->interrupt = cpu_to_le32(0);
436 acpi_build_table_header((struct acpi_table_header *)madt,
437 "APIC", madt_size, 1);