1 // Support for generating ACPI tables (on emulators)
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU GPLv3 license.
8 #include "acpi.h" // struct rsdp_descriptor
9 #include "util.h" // memcpy
10 #include "memmap.h" // bios_table_cur_addr
11 #include "pci.h" // pci_find_device
12 #include "biosvar.h" // GET_EBDA
13 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
14 #include "pci_regs.h" // PCI_INTERRUPT_LINE
17 /****************************************************/
18 /* ACPI tables init */
20 /* Table structure from Linux kernel (the ACPI tables are under the
23 #define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
24 u32 signature; /* ACPI signature (4 ASCII characters) */\
25 u32 length; /* Length of table, in bytes, including header */\
26 u8 revision; /* ACPI Specification minor version # */\
27 u8 checksum; /* To make sum of entire table == 0 */\
28 u8 oem_id [6]; /* OEM identification */\
29 u8 oem_table_id [8]; /* OEM table identification */\
30 u32 oem_revision; /* OEM revision number */\
31 u8 asl_compiler_id [4]; /* ASL compiler vendor ID */\
32 u32 asl_compiler_revision; /* ASL compiler revision number */
35 struct acpi_table_header /* ACPI common table header */
41 * ACPI 1.0 Root System Description Table (RSDT)
43 #define RSDT_SIGNATURE 0x54445352 // RSDT
44 struct rsdt_descriptor_rev1
46 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
47 u32 table_offset_entry [3]; /* Array of pointers to other */
52 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
54 #define FACS_SIGNATURE 0x53434146 // FACS
55 struct facs_descriptor_rev1
57 u32 signature; /* ACPI Signature */
58 u32 length; /* Length of structure, in bytes */
59 u32 hardware_signature; /* Hardware configuration signature */
60 u32 firmware_waking_vector; /* ACPI OS waking vector */
61 u32 global_lock; /* Global Lock */
62 u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */
63 u32 reserved1 : 31; /* Must be 0 */
64 u8 resverved3 [40]; /* Reserved - must be zero */
69 * ACPI 1.0 Fixed ACPI Description Table (FADT)
71 #define FACP_SIGNATURE 0x50434146 // FACP
72 struct fadt_descriptor_rev1
74 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
75 u32 firmware_ctrl; /* Physical address of FACS */
76 u32 dsdt; /* Physical address of DSDT */
77 u8 model; /* System Interrupt Model */
78 u8 reserved1; /* Reserved */
79 u16 sci_int; /* System vector of SCI interrupt */
80 u32 smi_cmd; /* Port address of SMI command port */
81 u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */
82 u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */
83 u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
84 u8 reserved2; /* Reserved - must be zero */
85 u32 pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
86 u32 pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
87 u32 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
88 u32 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
89 u32 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
90 u32 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
91 u32 gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
92 u32 gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
93 u8 pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
94 u8 pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
95 u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
96 u8 pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
97 u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
98 u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
99 u8 gpe1_base; /* Offset in gpe model where gpe1 events start */
100 u8 reserved3; /* Reserved */
101 u16 plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
102 u16 plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
103 u16 flush_size; /* Size of area read to flush caches */
104 u16 flush_stride; /* Stride used in flushing caches */
105 u8 duty_offset; /* Bit location of duty cycle field in p_cnt reg */
106 u8 duty_width; /* Bit width of duty cycle field in p_cnt reg */
107 u8 day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
108 u8 mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
109 u8 century; /* Index to century in RTC CMOS RAM */
110 u8 reserved4; /* Reserved */
111 u8 reserved4a; /* Reserved */
112 u8 reserved4b; /* Reserved */
114 u32 wb_invd : 1; /* The wbinvd instruction works properly */
115 u32 wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
116 u32 proc_c1 : 1; /* All processors support C1 state */
117 u32 plvl2_up : 1; /* C2 state works on MP system */
118 u32 pwr_button : 1; /* Power button is handled as a generic feature */
119 u32 sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
120 u32 fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
121 u32 rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
122 u32 tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
123 u32 reserved5 : 23; /* Reserved - must be zero */
130 * MADT values and structures
133 /* Values for MADT PCATCompat */
136 #define MULTIPLE_APIC 1
141 #define APIC_SIGNATURE 0x43495041 // APIC
142 struct multiple_apic_table
144 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
145 u32 local_apic_address; /* Physical address of local APIC */
147 u32 PCATcompat : 1; /* A one indicates system also has dual 8259s */
155 /* Values for Type in APIC_HEADER_DEF */
157 #define APIC_PROCESSOR 0
159 #define APIC_XRUPT_OVERRIDE 2
161 #define APIC_LOCAL_NMI 4
162 #define APIC_ADDRESS_OVERRIDE 5
163 #define APIC_IO_SAPIC 6
164 #define APIC_LOCAL_SAPIC 7
165 #define APIC_XRUPT_SOURCE 8
166 #define APIC_RESERVED 9 /* 9 and greater are reserved */
169 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
171 #define APIC_HEADER_DEF /* Common APIC sub-structure header */\
175 /* Sub-structures for MADT */
177 struct madt_processor_apic
180 u8 processor_id; /* ACPI processor id */
181 u8 local_apic_id; /* Processor's local APIC id */
183 u32 processor_enabled: 1; /* Processor is usable if set */
184 u32 reserved2 : 31; /* Reserved, must be zero */
193 u8 io_apic_id; /* I/O APIC ID */
194 u8 reserved; /* Reserved - must be zero */
195 u32 address; /* APIC physical address */
196 u32 interrupt; /* Global system interrupt where INTI
202 #define PCI_ISA_IRQ_MASK 0x0e20
204 #define PCI_ISA_IRQ_MASK 0x0000
207 struct madt_intsrcovr {
215 #include "acpi-dsdt.hex"
217 static inline u16 cpu_to_le16(u16 x)
222 static inline u32 cpu_to_le32(u32 x)
227 static void acpi_build_table_header(struct acpi_table_header *h,
228 u32 sig, int len, u8 rev)
231 h->length = cpu_to_le32(len);
233 memcpy(h->oem_id, CONFIG_APPNAME6, 6);
234 memcpy(h->oem_table_id, CONFIG_APPNAME4, 4);
235 memcpy(h->asl_compiler_id, CONFIG_APPNAME4, 4);
236 memcpy(h->oem_table_id + 4, (void*)&sig, 4);
237 h->oem_revision = cpu_to_le32(1);
238 h->asl_compiler_revision = cpu_to_le32(1);
239 h->checksum = -checksum((void *)h, len);
242 #define SSDT_SIGNATURE 0x54445353// SSDT
244 acpi_build_processor_ssdt(u8 *ssdt)
248 int smp_cpus = smp_probe();
249 int acpi_cpus = smp_cpus > 0xff ? 0xff : smp_cpus;
251 ssdt_ptr[9] = 0; // checksum;
252 ssdt_ptr += sizeof(struct acpi_table_header);
254 // caluculate the length of processor block and scope block excluding PkgLength
255 length = 0x0d * acpi_cpus + 4;
257 // build processor scope header
258 *(ssdt_ptr++) = 0x10; // ScopeOp
259 if (length <= 0x3e) {
260 *(ssdt_ptr++) = length + 1;
262 *(ssdt_ptr++) = 0x7F;
263 *(ssdt_ptr++) = (length + 2) >> 6;
265 *(ssdt_ptr++) = '_'; // Name
270 // build object for each processor
271 for(i=0;i<acpi_cpus;i++) {
272 *(ssdt_ptr++) = 0x5B; // ProcessorOp
273 *(ssdt_ptr++) = 0x83;
274 *(ssdt_ptr++) = 0x0B; // Length
275 *(ssdt_ptr++) = 'C'; // Name (CPUxx)
278 *(ssdt_ptr++) = (i >> 4) < 0xa ? (i >> 4) + '0' : (i >> 4) + 'A' - 0xa;
281 *(ssdt_ptr++) = (i & 0xf) < 0xa ? (i & 0xf) + '0' : (i & 0xf) + 'A' - 0xa;
283 *(ssdt_ptr++) = 0x10; // Processor block address
284 *(ssdt_ptr++) = 0xb0;
287 *(ssdt_ptr++) = 6; // Processor block length
290 acpi_build_table_header((struct acpi_table_header *)ssdt,
291 SSDT_SIGNATURE, ssdt_ptr - ssdt, 1);
293 return ssdt_ptr - ssdt;
296 struct rsdp_descriptor *RsdpAddr;
298 /* base_addr must be a multiple of 4KB */
299 void acpi_bios_init(void)
304 dprintf(3, "init ACPI tables\n");
306 // This code is hardcoded for PIIX4 Power Management device.
307 int bdf = pci_find_device(PCI_VENDOR_ID_INTEL
308 , PCI_DEVICE_ID_INTEL_82371AB_3);
313 struct rsdp_descriptor *rsdp;
314 struct rsdt_descriptor_rev1 *rsdt;
315 struct fadt_descriptor_rev1 *fadt;
316 struct facs_descriptor_rev1 *facs;
317 struct multiple_apic_table *madt;
319 u32 base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr, ssdt_addr;
320 u32 acpi_tables_size, madt_addr, madt_size;
323 /* reserve memory space for tables */
324 bios_table_cur_addr = ALIGN(bios_table_cur_addr, 16);
325 rsdp = (void *)(bios_table_cur_addr);
326 bios_table_cur_addr += sizeof(*rsdp);
328 addr = base_addr = RamSize - CONFIG_ACPI_DATA_SIZE;
329 add_e820(addr, CONFIG_ACPI_DATA_SIZE, E820_ACPI);
331 rsdt = (void *)(addr);
332 addr += sizeof(*rsdt);
335 fadt = (void *)(addr);
336 addr += sizeof(*fadt);
338 addr = ALIGN(addr, 64);
340 facs = (void *)(addr);
341 addr += sizeof(*facs);
344 dsdt = (void *)(addr);
345 addr += sizeof(AmlCode);
348 ssdt = (void *)(addr);
349 addr += acpi_build_processor_ssdt(ssdt);
351 int smp_cpus = smp_probe();
352 addr = ALIGN(addr, 8);
354 madt_size = sizeof(*madt) +
355 sizeof(struct madt_processor_apic) * smp_cpus +
356 sizeof(struct madt_io_apic);
357 madt = (void *)(addr);
360 acpi_tables_size = addr - base_addr;
362 dprintf(1, "ACPI tables: RSDP addr=0x%08lx"
363 " ACPI DATA addr=0x%08lx size=0x%x\n",
365 (unsigned long)rsdt, acpi_tables_size);
368 memset(rsdp, 0, sizeof(*rsdp));
369 rsdp->signature = RSDP_SIGNATURE;
370 memcpy(rsdp->oem_id, CONFIG_APPNAME6, 6);
371 rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr);
372 rsdp->checksum = -checksum((void *)rsdp, 20);
376 memset(rsdt, 0, sizeof(*rsdt));
377 rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
378 rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
379 rsdt->table_offset_entry[2] = cpu_to_le32(ssdt_addr);
380 acpi_build_table_header((struct acpi_table_header *)rsdt,
381 RSDT_SIGNATURE, sizeof(*rsdt), 1);
384 memset(fadt, 0, sizeof(*fadt));
385 fadt->firmware_ctrl = cpu_to_le32(facs_addr);
386 fadt->dsdt = cpu_to_le32(dsdt_addr);
389 int pm_sci_int = pci_config_readb(bdf, PCI_INTERRUPT_LINE);
390 fadt->sci_int = cpu_to_le16(pm_sci_int);
391 fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
392 fadt->acpi_enable = 0xf1;
393 fadt->acpi_disable = 0xf0;
394 fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE);
395 fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04);
396 fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08);
397 fadt->pm1_evt_len = 4;
398 fadt->pm1_cnt_len = 2;
399 fadt->pm_tmr_len = 4;
400 fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
401 fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
402 /* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
403 fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6));
404 acpi_build_table_header((struct acpi_table_header *)fadt, FACP_SIGNATURE,
408 memset(facs, 0, sizeof(*facs));
409 facs->signature = FACS_SIGNATURE;
410 facs->length = cpu_to_le32(sizeof(*facs));
413 memcpy(dsdt, AmlCode, sizeof(AmlCode));
416 memset(madt, 0, madt_size);
417 madt->local_apic_address = cpu_to_le32(BUILD_APIC_ADDR);
418 madt->flags = cpu_to_le32(1);
419 struct madt_processor_apic *apic = (void *)(madt + 1);
420 for(i=0;i<smp_cpus;i++) {
421 apic->type = APIC_PROCESSOR;
422 apic->length = sizeof(*apic);
423 apic->processor_id = i;
424 apic->local_apic_id = i;
425 apic->flags = cpu_to_le32(1);
428 struct madt_io_apic *io_apic = (void *)apic;
429 io_apic->type = APIC_IO;
430 io_apic->length = sizeof(*io_apic);
431 io_apic->io_apic_id = smp_cpus;
432 io_apic->address = cpu_to_le32(BUILD_IOAPIC_ADDR);
433 io_apic->interrupt = cpu_to_le32(0);
435 struct madt_intsrcovr *intsrcovr = (struct madt_intsrcovr*)(io_apic + 1);
436 for (i = 0; i < 16; i++) {
437 if (PCI_ISA_IRQ_MASK & (1 << i)) {
438 memset(intsrcovr, 0, sizeof(*intsrcovr));
439 intsrcovr->type = APIC_XRUPT_OVERRIDE;
440 intsrcovr->length = sizeof(*intsrcovr);
441 intsrcovr->source = i;
443 intsrcovr->flags = 0xd; /* active high, level triggered */
445 /* No need for a INT source override structure. */
449 madt_size += sizeof(struct madt_intsrcovr);
452 acpi_build_table_header((struct acpi_table_header *)madt,
453 APIC_SIGNATURE, madt_size, 1);
459 dprintf(4, "rsdp=%p\n", RsdpAddr);
460 if (!RsdpAddr || RsdpAddr->signature != RSDP_SIGNATURE)
462 struct rsdt_descriptor_rev1 *rsdt = (void*)RsdpAddr->rsdt_physical_address;
463 dprintf(4, "rsdt=%p\n", rsdt);
464 if (!rsdt || rsdt->signature != RSDT_SIGNATURE)
466 void *end = (void*)rsdt + rsdt->length;
468 for (i=0; (void*)&rsdt->table_offset_entry[i] < end; i++) {
469 struct fadt_descriptor_rev1 *fadt = (void*)rsdt->table_offset_entry[i];
470 if (!fadt || fadt->signature != FACP_SIGNATURE)
472 dprintf(4, "fadt=%p\n", fadt);
473 struct facs_descriptor_rev1 *facs = (void*)fadt->firmware_ctrl;
474 dprintf(4, "facs=%p\n", facs);
475 if (! facs || facs->signature != FACS_SIGNATURE)
478 dprintf(4, "resume addr=%d\n", facs->firmware_waking_vector);
479 return facs->firmware_waking_vector;