1 // Support for generating ACPI tables (on emulators)
3 // Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "acpi.h" // struct rsdp_descriptor
9 #include "util.h" // memcpy
10 #include "pci.h" // pci_find_init_device
11 #include "biosvar.h" // GET_EBDA
12 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
13 #include "pci_regs.h" // PCI_INTERRUPT_LINE
16 /****************************************************/
17 /* ACPI tables init */
19 /* Table structure from Linux kernel (the ACPI tables are under the
22 struct acpi_table_header /* ACPI common table header */
28 * ACPI 1.0 Root System Description Table (RSDT)
30 #define RSDT_SIGNATURE 0x54445352 // RSDT
31 struct rsdt_descriptor_rev1
33 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
34 u32 table_offset_entry[0]; /* Array of pointers to other */
39 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
41 #define FACS_SIGNATURE 0x53434146 // FACS
42 struct facs_descriptor_rev1
44 u32 signature; /* ACPI Signature */
45 u32 length; /* Length of structure, in bytes */
46 u32 hardware_signature; /* Hardware configuration signature */
47 u32 firmware_waking_vector; /* ACPI OS waking vector */
48 u32 global_lock; /* Global Lock */
49 u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */
50 u32 reserved1 : 31; /* Must be 0 */
51 u8 resverved3 [40]; /* Reserved - must be zero */
56 * Differentiated System Description Table (DSDT)
58 #define DSDT_SIGNATURE 0x54445344 // DSDT
61 * MADT values and structures
64 /* Values for MADT PCATCompat */
67 #define MULTIPLE_APIC 1
72 #define APIC_SIGNATURE 0x43495041 // APIC
73 struct multiple_apic_table
75 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
76 u32 local_apic_address; /* Physical address of local APIC */
78 u32 PCATcompat : 1; /* A one indicates system also has dual 8259s */
86 /* Values for Type in APIC sub-headers */
88 #define APIC_PROCESSOR 0
90 #define APIC_XRUPT_OVERRIDE 2
92 #define APIC_LOCAL_NMI 4
93 #define APIC_ADDRESS_OVERRIDE 5
94 #define APIC_IO_SAPIC 6
95 #define APIC_LOCAL_SAPIC 7
96 #define APIC_XRUPT_SOURCE 8
97 #define APIC_RESERVED 9 /* 9 and greater are reserved */
100 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
102 #define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\
106 /* Sub-structures for MADT */
108 struct madt_processor_apic
111 u8 processor_id; /* ACPI processor id */
112 u8 local_apic_id; /* Processor's local APIC id */
114 u32 processor_enabled: 1; /* Processor is usable if set */
115 u32 reserved2 : 31; /* Reserved, must be zero */
124 u8 io_apic_id; /* I/O APIC ID */
125 u8 reserved; /* Reserved - must be zero */
126 u32 address; /* APIC physical address */
127 u32 interrupt; /* Global system interrupt where INTI
132 #define PCI_ISA_IRQ_MASK 0x0e20
134 struct madt_intsrcovr {
143 * ACPI 2.0 Generic Address Space definition.
145 struct acpi_20_generic_address {
147 u8 register_bit_width;
148 u8 register_bit_offset;
154 * HPET Description Table
156 struct acpi_20_hpet {
157 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
159 struct acpi_20_generic_address addr;
165 #define HPET_ID 0x000
166 #define HPET_PERIOD 0x004
169 * SRAT (NUMA topology description) table
172 #define SRAT_PROCESSOR 0
173 #define SRAT_MEMORY 1
175 struct system_resource_affinity_table
177 ACPI_TABLE_HEADER_DEF
182 struct srat_processor_affinity
193 struct srat_memory_affinity
198 u32 base_addr_low,base_addr_high;
199 u32 length_low,length_high;
205 #include "acpi-dsdt.hex"
208 build_header(struct acpi_table_header *h, u32 sig, int len, u8 rev)
211 h->length = cpu_to_le32(len);
213 memcpy(h->oem_id, CONFIG_APPNAME6, 6);
214 memcpy(h->oem_table_id, CONFIG_APPNAME4, 4);
215 memcpy(h->oem_table_id + 4, (void*)&sig, 4);
216 h->oem_revision = cpu_to_le32(1);
217 memcpy(h->asl_compiler_id, CONFIG_APPNAME4, 4);
218 h->asl_compiler_revision = cpu_to_le32(1);
219 h->checksum -= checksum(h, len);
222 #define PIIX4_ACPI_ENABLE 0xf1
223 #define PIIX4_ACPI_DISABLE 0xf0
224 #define PIIX4_GPE0_BLK 0xafe0
225 #define PIIX4_GPE0_BLK_LEN 4
227 static void piix4_fadt_init(struct pci_device *pci, void *arg)
229 struct fadt_descriptor_rev1 *fadt = arg;
230 fadt->acpi_enable = PIIX4_ACPI_ENABLE;
231 fadt->acpi_disable = PIIX4_ACPI_DISABLE;
232 fadt->gpe0_blk = cpu_to_le32(PIIX4_GPE0_BLK);
233 fadt->gpe0_blk_len = PIIX4_GPE0_BLK_LEN;
236 static const struct pci_device_id fadt_init_tbl[] = {
237 /* PIIX4 Power Management device (for ACPI) */
238 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
244 static void fill_dsdt(struct fadt_descriptor_rev1 *fadt, void *dsdt)
247 free((void *)le32_to_cpu(fadt->dsdt));
249 fadt->dsdt = cpu_to_le32((u32)dsdt);
250 fadt->checksum -= checksum(fadt, sizeof(*fadt));
251 dprintf(1, "ACPI DSDT=%p\n", dsdt);
255 build_fadt(struct pci_device *pci)
257 struct fadt_descriptor_rev1 *fadt = malloc_high(sizeof(*fadt));
258 struct facs_descriptor_rev1 *facs = memalign_high(64, sizeof(*facs));
260 if (!fadt || !facs) {
266 memset(facs, 0, sizeof(*facs));
267 facs->signature = FACS_SIGNATURE;
268 facs->length = cpu_to_le32(sizeof(*facs));
271 memset(fadt, 0, sizeof(*fadt));
272 fadt->firmware_ctrl = cpu_to_le32((u32)facs);
273 fadt->dsdt = 0; /* dsdt will be filled later in acpi_bios_init()
277 int pm_sci_int = pci_config_readb(pci->bdf, PCI_INTERRUPT_LINE);
278 fadt->sci_int = cpu_to_le16(pm_sci_int);
279 fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
280 fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE);
281 fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04);
282 fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08);
283 fadt->pm1_evt_len = 4;
284 fadt->pm1_cnt_len = 2;
285 fadt->pm_tmr_len = 4;
286 fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
287 fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
288 pci_init_device(fadt_init_tbl, pci, fadt);
289 /* WBINVD + PROC_C1 + SLP_BUTTON + FIX_RTC + RTC_S4 */
290 fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 6) | (1 << 7));
292 build_header((void*)fadt, FACP_SIGNATURE, sizeof(*fadt), 1);
300 int madt_size = (sizeof(struct multiple_apic_table)
301 + sizeof(struct madt_processor_apic) * MaxCountCPUs
302 + sizeof(struct madt_io_apic)
303 + sizeof(struct madt_intsrcovr) * 16);
304 struct multiple_apic_table *madt = malloc_high(madt_size);
309 memset(madt, 0, madt_size);
310 madt->local_apic_address = cpu_to_le32(BUILD_APIC_ADDR);
311 madt->flags = cpu_to_le32(1);
312 struct madt_processor_apic *apic = (void*)&madt[1];
314 for (i=0; i<MaxCountCPUs; i++) {
315 apic->type = APIC_PROCESSOR;
316 apic->length = sizeof(*apic);
317 apic->processor_id = i;
318 apic->local_apic_id = i;
320 apic->flags = cpu_to_le32(1);
322 apic->flags = cpu_to_le32(0);
325 struct madt_io_apic *io_apic = (void*)apic;
326 io_apic->type = APIC_IO;
327 io_apic->length = sizeof(*io_apic);
328 io_apic->io_apic_id = CountCPUs;
329 io_apic->address = cpu_to_le32(BUILD_IOAPIC_ADDR);
330 io_apic->interrupt = cpu_to_le32(0);
332 struct madt_intsrcovr *intsrcovr = (void*)&io_apic[1];
333 if (qemu_cfg_irq0_override()) {
334 memset(intsrcovr, 0, sizeof(*intsrcovr));
335 intsrcovr->type = APIC_XRUPT_OVERRIDE;
336 intsrcovr->length = sizeof(*intsrcovr);
337 intsrcovr->source = 0;
339 intsrcovr->flags = 0; /* conforms to bus specifications */
342 for (i = 1; i < 16; i++) {
343 if (!(PCI_ISA_IRQ_MASK & (1 << i)))
344 /* No need for a INT source override structure. */
346 memset(intsrcovr, 0, sizeof(*intsrcovr));
347 intsrcovr->type = APIC_XRUPT_OVERRIDE;
348 intsrcovr->length = sizeof(*intsrcovr);
349 intsrcovr->source = i;
351 intsrcovr->flags = 0xd; /* active high, level triggered */
355 build_header((void*)madt, APIC_SIGNATURE, (void*)intsrcovr - (void*)madt, 1);
359 // Encode a hex value
360 static inline char getHex(u32 val) {
362 return (val <= 9) ? ('0' + val) : ('A' + val - 10);
365 // Encode a length in an SSDT.
367 encodeLen(u8 *ssdt_ptr, int length, int bytes)
371 case 4: ssdt_ptr[3] = ((length >> 20) & 0xff);
372 case 3: ssdt_ptr[2] = ((length >> 12) & 0xff);
373 case 2: ssdt_ptr[1] = ((length >> 4) & 0xff);
374 ssdt_ptr[0] = (((bytes-1) & 0x3) << 6) | (length & 0x0f);
376 case 1: ssdt_ptr[0] = length & 0x3f;
378 return ssdt_ptr + bytes;
381 #define AmlCode static ssdp_proc_aml
382 #include "ssdt-proc.hex"
385 /* 0x5B 0x83 ProcessorOp PkgLength NameString ProcID */
386 #define SD_OFFSET_CPUHEX (*ssdt_proc_name - *ssdt_proc_start + 2)
387 #define SD_OFFSET_CPUID1 (*ssdt_proc_name - *ssdt_proc_start + 4)
388 #define SD_OFFSET_CPUID2 (*ssdt_proc_id - *ssdt_proc_start)
389 #define SD_SIZEOF (*ssdt_proc_end - *ssdt_proc_start)
390 #define SD_PROC (ssdp_proc_aml + *ssdt_proc_start)
392 #define SSDT_SIGNATURE 0x54445353 // SSDT
396 int acpi_cpus = MaxCountCPUs > 0xff ? 0xff : MaxCountCPUs;
397 // length = ScopeOp + procs + NTYF method + CPON package
398 int length = ((1+3+4)
399 + (acpi_cpus * SD_SIZEOF)
400 + (1+2+5+(12*acpi_cpus))
401 + (6+2+1+(1*acpi_cpus)));
402 u8 *ssdt = malloc_high(sizeof(struct acpi_table_header) + length);
407 u8 *ssdt_ptr = ssdt + sizeof(struct acpi_table_header);
409 // build Scope(_SB_) header
410 *(ssdt_ptr++) = 0x10; // ScopeOp
411 ssdt_ptr = encodeLen(ssdt_ptr, length-1, 3);
417 // build Processor object for each processor
419 for (i=0; i<acpi_cpus; i++) {
420 memcpy(ssdt_ptr, SD_PROC, SD_SIZEOF);
421 ssdt_ptr[SD_OFFSET_CPUHEX] = getHex(i >> 4);
422 ssdt_ptr[SD_OFFSET_CPUHEX+1] = getHex(i);
423 ssdt_ptr[SD_OFFSET_CPUID1] = i;
424 ssdt_ptr[SD_OFFSET_CPUID2] = i;
425 ssdt_ptr += SD_SIZEOF;
428 // build "Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}"
429 *(ssdt_ptr++) = 0x14; // MethodOp
430 ssdt_ptr = encodeLen(ssdt_ptr, 2+5+(12*acpi_cpus), 2);
435 *(ssdt_ptr++) = 0x02;
436 for (i=0; i<acpi_cpus; i++) {
437 *(ssdt_ptr++) = 0xA0; // IfOp
438 ssdt_ptr = encodeLen(ssdt_ptr, 11, 1);
439 *(ssdt_ptr++) = 0x93; // LEqualOp
440 *(ssdt_ptr++) = 0x68; // Arg0Op
441 *(ssdt_ptr++) = 0x0A; // BytePrefix
443 *(ssdt_ptr++) = 0x86; // NotifyOp
446 *(ssdt_ptr++) = getHex(i >> 4);
447 *(ssdt_ptr++) = getHex(i);
448 *(ssdt_ptr++) = 0x69; // Arg1Op
451 // build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
452 *(ssdt_ptr++) = 0x08; // NameOp
457 *(ssdt_ptr++) = 0x12; // PackageOp
458 ssdt_ptr = encodeLen(ssdt_ptr, 2+1+(1*acpi_cpus), 2);
459 *(ssdt_ptr++) = acpi_cpus;
460 for (i=0; i<acpi_cpus; i++)
461 *(ssdt_ptr++) = (i < CountCPUs) ? 0x01 : 0x00;
463 build_header((void*)ssdt, SSDT_SIGNATURE, ssdt_ptr - ssdt, 1);
465 //hexdump(ssdt, ssdt_ptr - ssdt);
470 #define HPET_SIGNATURE 0x54455048 // HPET
474 struct acpi_20_hpet *hpet;
475 const void *hpet_base = (void *)BUILD_HPET_ADDRESS;
476 u32 hpet_vendor = readl(hpet_base + HPET_ID) >> 16;
477 u32 hpet_period = readl(hpet_base + HPET_PERIOD);
479 if (hpet_vendor == 0 || hpet_vendor == 0xffff ||
480 hpet_period == 0 || hpet_period > 100000000)
483 hpet = malloc_high(sizeof(*hpet));
489 memset(hpet, 0, sizeof(*hpet));
490 /* Note timer_block_id value must be kept in sync with value advertised by
493 hpet->timer_block_id = cpu_to_le32(0x8086a201);
494 hpet->addr.address = cpu_to_le32(BUILD_HPET_ADDRESS);
495 build_header((void*)hpet, HPET_SIGNATURE, sizeof(*hpet), 1);
501 acpi_build_srat_memory(struct srat_memory_affinity *numamem,
502 u64 base, u64 len, int node, int enabled)
504 numamem->type = SRAT_MEMORY;
505 numamem->length = sizeof(*numamem);
506 memset(numamem->proximity, 0 ,4);
507 numamem->proximity[0] = node;
508 numamem->flags = cpu_to_le32(!!enabled);
509 numamem->base_addr_low = base & 0xFFFFFFFF;
510 numamem->base_addr_high = base >> 32;
511 numamem->length_low = len & 0xFFFFFFFF;
512 numamem->length_high = len >> 32;
515 #define SRAT_SIGNATURE 0x54415253 // SRAT
519 int nb_numa_nodes = qemu_cfg_get_numa_nodes();
521 if (nb_numa_nodes == 0)
524 u64 *numadata = malloc_tmphigh(sizeof(u64) * (MaxCountCPUs + nb_numa_nodes));
530 qemu_cfg_get_numa_data(numadata, MaxCountCPUs + nb_numa_nodes);
532 struct system_resource_affinity_table *srat;
533 int srat_size = sizeof(*srat) +
534 sizeof(struct srat_processor_affinity) * MaxCountCPUs +
535 sizeof(struct srat_memory_affinity) * (nb_numa_nodes + 2);
537 srat = malloc_high(srat_size);
544 memset(srat, 0, srat_size);
546 struct srat_processor_affinity *core = (void*)(srat + 1);
550 for (i = 0; i < MaxCountCPUs; ++i) {
551 core->type = SRAT_PROCESSOR;
552 core->length = sizeof(*core);
553 core->local_apic_id = i;
554 curnode = *numadata++;
555 core->proximity_lo = curnode;
556 memset(core->proximity_hi, 0, 3);
557 core->local_sapic_eid = 0;
559 core->flags = cpu_to_le32(1);
566 /* the memory map is a bit tricky, it contains at least one hole
567 * from 640k-1M and possibly another one from 3.5G-4G.
569 struct srat_memory_affinity *numamem = (void*)core;
571 u64 mem_len, mem_base, next_base = 0;
573 acpi_build_srat_memory(numamem, 0, 640*1024, 0, 1);
574 next_base = 1024 * 1024;
577 for (i = 1; i < nb_numa_nodes + 1; ++i) {
578 mem_base = next_base;
579 mem_len = *numadata++;
581 mem_len -= 1024 * 1024;
582 next_base = mem_base + mem_len;
584 /* Cut out the PCI hole */
585 if (mem_base <= RamSize && next_base > RamSize) {
586 mem_len -= next_base - RamSize;
588 acpi_build_srat_memory(numamem, mem_base, mem_len, i-1, 1);
592 mem_base = 1ULL << 32;
593 mem_len = next_base - RamSize;
594 next_base += (1ULL << 32) - RamSize;
596 acpi_build_srat_memory(numamem, mem_base, mem_len, i-1, 1);
600 for (; slots < nb_numa_nodes + 2; slots++) {
601 acpi_build_srat_memory(numamem, 0, 0, 0, 0);
605 build_header((void*)srat, SRAT_SIGNATURE, srat_size, 1);
611 static const struct pci_device_id acpi_find_tbl[] = {
612 /* PIIX4 Power Management device. */
613 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, NULL),
618 struct rsdp_descriptor *RsdpAddr;
620 #define MAX_ACPI_TABLES 20
627 dprintf(3, "init ACPI tables\n");
629 // This code is hardcoded for PIIX4 Power Management device.
630 struct pci_device *pci = pci_find_init_device(acpi_find_tbl, NULL);
636 u32 tables[MAX_ACPI_TABLES], tbl_idx = 0;
638 #define ACPI_INIT_TABLE(X) \
640 tables[tbl_idx] = (u32)(X); \
641 if (tables[tbl_idx]) \
645 struct fadt_descriptor_rev1 *fadt = build_fadt(pci);
646 ACPI_INIT_TABLE(fadt);
647 ACPI_INIT_TABLE(build_ssdt());
648 ACPI_INIT_TABLE(build_madt());
649 ACPI_INIT_TABLE(build_hpet());
650 ACPI_INIT_TABLE(build_srat());
652 u16 i, external_tables = qemu_cfg_acpi_additional_tables();
654 for (i = 0; i < external_tables; i++) {
655 u16 len = qemu_cfg_next_acpi_table_len();
656 void *addr = malloc_high(len);
661 struct acpi_table_header *header =
662 qemu_cfg_next_acpi_table_load(addr, len);
663 if (header->signature == DSDT_SIGNATURE) {
665 fill_dsdt(fadt, addr);
668 ACPI_INIT_TABLE(header);
670 if (tbl_idx == MAX_ACPI_TABLES) {
675 if (fadt && !fadt->dsdt) {
677 void *dsdt = malloc_high(sizeof(AmlCode));
682 memcpy(dsdt, AmlCode, sizeof(AmlCode));
683 fill_dsdt(fadt, dsdt);
686 // Build final rsdt table
687 struct rsdt_descriptor_rev1 *rsdt;
688 size_t rsdt_len = sizeof(*rsdt) + sizeof(u32) * tbl_idx;
689 rsdt = malloc_high(rsdt_len);
694 memset(rsdt, 0, rsdt_len);
695 memcpy(rsdt->table_offset_entry, tables, sizeof(u32) * tbl_idx);
696 build_header((void*)rsdt, RSDT_SIGNATURE, rsdt_len, 1);
698 // Build rsdp pointer table
699 struct rsdp_descriptor *rsdp = malloc_fseg(sizeof(*rsdp));
704 memset(rsdp, 0, sizeof(*rsdp));
705 rsdp->signature = RSDP_SIGNATURE;
706 memcpy(rsdp->oem_id, CONFIG_APPNAME6, 6);
707 rsdp->rsdt_physical_address = cpu_to_le32((u32)rsdt);
708 rsdp->checksum -= checksum(rsdp, 20);
710 dprintf(1, "ACPI tables: RSDP=%p RSDT=%p\n", rsdp, rsdt);
714 find_resume_vector(void)
716 dprintf(4, "rsdp=%p\n", RsdpAddr);
717 if (!RsdpAddr || RsdpAddr->signature != RSDP_SIGNATURE)
719 struct rsdt_descriptor_rev1 *rsdt = (void*)RsdpAddr->rsdt_physical_address;
720 dprintf(4, "rsdt=%p\n", rsdt);
721 if (!rsdt || rsdt->signature != RSDT_SIGNATURE)
723 void *end = (void*)rsdt + rsdt->length;
725 for (i=0; (void*)&rsdt->table_offset_entry[i] < end; i++) {
726 struct fadt_descriptor_rev1 *fadt = (void*)rsdt->table_offset_entry[i];
727 if (!fadt || fadt->signature != FACP_SIGNATURE)
729 dprintf(4, "fadt=%p\n", fadt);
730 struct facs_descriptor_rev1 *facs = (void*)fadt->firmware_ctrl;
731 dprintf(4, "facs=%p\n", facs);
732 if (! facs || facs->signature != FACS_SIGNATURE)
735 dprintf(4, "resume addr=%d\n", facs->firmware_waking_vector);
736 return facs->firmware_waking_vector;