1 # Kconfig SeaBIOS configuration
3 mainmenu "SeaBIOS Configuration"
5 menu "General Features"
8 bool "Build for coreboot"
11 Configure as a coreboot payload.
15 bool "Build for Xen HVM"
18 Configure to be used by xen hvmloader, for a HVM guest.
21 bool "Parallelize hardware init"
24 Support running hardware initialization in parallel.
25 config THREAD_OPTIONROMS
27 bool "Hardware init during option ROM execution"
30 Allow hardware init to run in parallel with optionrom execution.
32 This can reduce boot time, but can cause some timing
33 variations during option ROM code execution. It is not
34 known if all option ROMs will behave properly with this
38 bool "Copy init code to high memory"
41 Support relocating the one time initialization code to high memory.
48 Support an interactive boot menu at end of post.
51 bool "Graphical boot splash screen"
54 Support showing a graphical boot splash screen.
60 Support controlling of the boot order via the fw_cfg/CBFS
65 bool "coreboot CBFS support"
68 Support searching coreboot flash format.
70 depends on COREBOOT_FLASH
71 bool "CBFS lzma support"
74 Support CBFS files compressed using the lzma decompression
77 depends on COREBOOT_FLASH
78 bool "Floppy images in CBFS"
81 Support floppy images in coreboot flash.
85 menu "Hardware support"
88 bool "ATA controllers"
91 Support for IDE disk code.
97 Detect and try to use ATA bus mastering DMA controllers.
103 Use 32bit PIO accesses on ATA (minor optimization on PCI transfers).
106 bool "AHCI controllers"
109 Support for AHCI disk code.
111 depends on DRIVES && !COREBOOT
112 bool "VirtIO controllers"
115 Support boot from virtio storage.
118 bool "Floppy controller"
121 Support floppy drive access.
124 depends on KEYBOARD || MOUSE
128 Support PS2 ports (keyboard and mouse).
129 config PS2_KEYBOARD_SPINUP
130 depends on PS2PORT && COREBOOT
131 int "Extra time (in ms) to allow a keyboard to initialize"
134 Some PS2 keyboards don't respond to commands immediately
135 after powering on. Specify a positive value here to allow
136 additional time for the keyboard to become responsive.
145 bool "USB UHCI controllers"
148 Support USB UHCI controllers.
151 bool "USB OHCI controllers"
154 Support USB OHCI controllers.
157 bool "USB EHCI controllers"
160 Support USB EHCI controllers.
162 depends on USB && DRIVES
174 depends on USB && KEYBOARD
178 Support USB keyboards.
180 depends on USB && MOUSE
190 Support serial ports. This also enables int 14 serial port calls.
195 Support parallel ports. This also enables int 17 parallel port calls.
197 config EXTRA_PCI_ROOTS
198 int "Number of extra root buses"
201 If the target machine has multiple independent root buses
202 set this to a positive value. The SeaBIOS PCI probe will
203 then search for the given number of extra root buses.
205 Most machines do not have multiple root buses and this
206 setting should be zero.
210 bool "System Management Mode (SMM)"
213 Support System Management Mode (on emulators).
216 bool "Initialize MTRRs"
219 Initialize the Memory Type Range Registers (on emulators).
222 menu "BIOS interfaces"
224 bool "Drive interface"
227 Support int13 disk/floppy drive functions.
231 bool "DVD/CDROM booting"
234 Support for booting from a CD. (El Torito spec support.)
236 depends on CDROM_BOOT
237 bool "DVD/CDROM boot drive emulation"
240 Support bootable CDROMs that emulate a floppy/harddrive.
243 bool "PCIBIOS interface"
246 Support int 1a/b1 PCI BIOS calls.
251 Support int 15/53 APM BIOS calls.
253 bool "PnP BIOS interface"
256 Support PnP BIOS entry point.
261 Support finding and running option roms during POST.
262 config OPTIONROMS_DEPLOYED
263 depends on OPTIONROMS
264 bool "Option roms are already at 0xc0000-0xf0000"
267 Select this if option ROMs are already copied to
268 0xc0000-0xf0000. This must only be selected when using
269 Bochs or QEMU versions older than 0.12.
270 config OPTIONROMS_CHECKSUM
271 depends on OPTIONROMS
272 bool "Require correct checksum on option ROMs"
275 Option ROMs are required to have correct checksums.
276 However, some option ROMs in the wild don't correctly
277 follow the specifications and have bad checksums.
278 Say N here to allow SeaBIOS to execute them anyways.
282 depends on OPTIONROMS
286 Support Post Memory Manager (PMM) entry point.
288 bool "Boot interface"
291 Support int 19/18 system bootup support.
293 bool "Keyboard interface"
296 Support int 16 keyboard calls.
297 config KBD_CALL_INT15_4F
299 bool "Keyboard hook interface"
302 Support calling int155f on each keyboard event.
304 bool "Mouse interface"
307 Support for int15c2 mouse calls.
313 Support S3 resume handler.
314 config S3_RESUME_VGA_INIT
316 bool "Run VGA rom on S3 resume"
319 Run the vga rom during S3 resume.
323 bool "Hardware specific VGA helpers"
326 Support int 155f BIOS callbacks specific to some Intel and
327 VIA on-board vga devices.
333 Disable A20 on 16bit boot.
342 Support generation of a PIR table in 0xf000 segment.
348 Support generation of MPTable.
353 Support generation of SM BIOS tables. This is also
354 sometimes called DMI.
360 Support generation of ACPI tables.
368 Control how verbose debug output is. The higher the
369 number, the more verbose SeaBIOS will be.
371 Set to zero to disable debugging.
374 depends on DEBUG_LEVEL != 0
375 bool "Serial port debugging"
378 Send debugging information to serial port.
379 config DEBUG_SERIAL_PORT
380 depends on DEBUG_SERIAL
381 hex "Serial port base address"
384 Base port for serial - generally 0x3f8, 0x2f8, 0x3e8, or 0x2e8.
386 config SCREEN_AND_DEBUG
387 depends on DEBUG_LEVEL != 0
388 bool "Show screen writes on debug ports"
391 Send characters that SeaBIOS writes to the screen to the