4 ;=========================================================================================
5 ; 4.1 Controller Device
6 ;=========================================================================================
7 #set MB91464A 2 ; MB91460 series
9 #set MB91467B 10 ; MB91460 series
11 #set MB91467C 11 ; MB91460 series
13 #set MB91467D 4 ; MB91460 series
15 #set MB91469G 6 ; MB91460 series
17 #set MB91465K 3 ; MB91460 series
19 #set MB91463N 8 ; MB91460 series
21 #set MB91461R 1 ; MB91460 series
22 #set MB91467R 5 ; MB91460 series
24 #set MB91465X 9 ; MB91460 series
26 #set others 7 ; MB91460 series
29 #set DEVICE MB91465X ; <<< select device
30 ;=========================================================================================
31 ; 4.3 Stack Type and Stack Size
32 ;=========================================================================================
34 #set USRSTACK 0 ; user stack: for main program
35 #set SYSSTACK 1 ; system stack: for main program and
38 #set STACKUSE SYSSTACK ; <<< set active stack
40 #set STACK_RESERVE ON ; <<< reserve stack area in
42 #set STACK_SYS_SIZE 0x400-4 ; <<< byte size of System stack
43 #set STACK_USR_SIZE 0x2 ; <<< byte size of User stack
45 ; - If the active stack is set to SYSSTACK, it is used for main program and interrupts.
46 ; In this case, the user stack could be set to a dummy size. If the active stack is
47 ; set to user stack, it is used for the main program but the system stack is
48 ; automatically activated, if an interrupt is serviced. Both stack areas must have a
50 ; - If STACK_RESERVE is ON, the sections USTACK and SSTACK are reserved in this module.
51 ; Otherwise, they have to be reserved in other modules. If STACK_RESERVE is OFF, the
52 ; size definitions STACK_SYS_SIZE and STACK_USR_SIZE have no meaning.
53 ; - Even if they are reverved in other modules, they are still initialised in this
56 ; Note: Several library functions require quite a big stack (due to ANSI).
57 ; Check the stack information files (*.stk) in the LIB\911 directory.
59 ;=========================================================================================
60 ; 4.7 Clock Configuration
61 ;=========================================================================================
62 ;=========================================================================================
63 ; 4.7.1 Clock Selection
64 ;=========================================================================================
69 ; Sub-oscillation input: 32 kHz
70 #set SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ 0x11
72 ; Oscillation input: 4 MHz
73 #set PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ 0x23
75 ; MB91461R only: Oscillation input: 10 MHz
76 #set PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ 0x41
78 ; MB91461R only: Oscillation input: 20 MHz
79 #set PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ 0x51
86 #set CLOCKSPEED PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ
87 ; ; <<< Select clock configuration
89 ;=========================================================================================
90 ; 4.7.2 Select Clock Modulator
91 ;=========================================================================================
93 #set CLOMO OFF ; <<< Enable /disable clock modulator
95 #set CMPR 0x026F ; <<< Ref. to the data sheet, CMPR
97 ; Please refer to the data sheet of the device if you enable clock modulation. The
98 ; register CMPR dependant on the PLL-Clock.
100 ; Note: If the CLKCAN source is set either to main oscillator or to PLL output then the
101 ; clock for the CAN is not influenced by the clock modulation. If the CLKCAN
102 ; source is set CPU clock (CLKB) then the clock for the CAN is also modulated (if
103 ; the clock modulator is enabled).
105 ; Note: If the clock modulator is enabled, the wait states of the internal flash wait
106 ; states must be adapted to maximum frequency. Please check the wait states
109 ; Note: This feature is not supported by every device, e.g. MB91461. Please check the
112 ;=========================================================================================
113 ; 4.8 External Bus Interface
115 ; The rest of the configuration is only applicable for devices with an external bus
118 ; If the device does not offer an external bus interface, the configuration can be
119 ; stoped at this point.
121 ;=========================================================================================
122 ; 5 Definition of Configurations
123 ;=========================================================================================
125 #set NOCLOCK 0 ; do not touch CKSCR register
126 #set MAINCLOCK 1 ; select main clock
127 ; ; MB91461R : 1/4 of oscillation input
128 ; ; Others: 1/2 of oscillation input
129 #set MAINPLLCLOCK 2 ; select main clock with PLL
130 #set SUBCLOCK 3 ; select subclock (if available)
132 #set PSCLOCK_CLKB 0x00 ; select core clock (initial)
133 #set PSCLOCK_PLL 0x10 ; select PLL output (x)
134 #set PSCLOCK_MAIN 0x30 ; select Main Oscillation
136 ;=========================================================================================
137 ; 5.2 CLOCKSPEED == NO_CLOCK
138 ;=========================================================================================
140 #if (CLOCKSPEED == NO_CLOCK )
141 #set CLOCKSOURCE NOCLOCK
143 ;=========================================================================================
144 ; 5.5 CLOCKSPEED == PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ
145 ;=========================================================================================
147 #if (CLOCKSPEED == PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ )
149 ; Start restriction; Maximum frequency
150 #if (DEVICE == MB91461R)
151 #error: Frequency is not supported by this device.
155 #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
156 #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
157 #set PLLSPEED 0x010F ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 64 MHz
158 #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
159 #set MUL_G 0x0F ; 0x48Fh: PLLMULG;
161 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 64 MHz
162 #set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 16 MHz
163 #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 32 MHz
165 #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 128 MHz
166 #set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 16 MHz
167 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
169 #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
170 #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
172 #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
173 #set FLASHREADT 0xC413 ; 0x7004h: FMWT;
174 #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;
177 ;=========================================================================================
178 ; 6 Section and Data Declaration
179 ;=========================================================================================
182 ;=========================================================================================
183 ; 6.1 Define Stack Size
184 ;=========================================================================================
185 .section DATA, data, align=4
186 .SECTION SSTACK, STACK, ALIGN=4
187 #if STACK_RESERVE == ON
188 .EXPORT __systemstack, __systemstack_top
190 .RES.B STACK_SYS_SIZE
194 ;=========================================================================================
195 ; 6.2 Define Sections
196 ;=========================================================================================
197 .section CODE, code, align=4
199 ;-----------------------------------------------------------------------------------------
200 ; MACRO Clear RC Watchdog
201 ;-----------------------------------------------------------------------------------------
202 #macro ClearRCwatchdog
203 LDI #0x4C7,R7 ; clear RC watchdog
206 .section CODE_START, code, align=4
208 ;=========================================================================================
210 ;=========================================================================================
211 __start: ; start point
215 ANDCCR #0xEF ; disable interrupts
216 STILM #31 ; set interrupt level to low prior
217 ClearRCwatchdog ; clear harware watchdog
219 ;=========================================================================================
220 ; 7.1 Initialise Stack Pointer
221 ;=========================================================================================
222 #if STACKUSE == SYSSTACK
224 LDI #__systemstack_top, SP ; initialize SP
227 #if (CLOCKSOURCE != NOCLOCK)
228 ;=========================================================================================
229 ; 7.2 Check for CSV reset and set CSV
230 ;=========================================================================================
231 ; Start restriction; No clock supervisor (CSV)
232 #if (DEVICE != MB91461R) && (DEVICE != MB91467R) && (DEVICE != MB91463N)
234 LDI:20 #0x04AD, R0 ; CSVCR
235 BORL #0x8, @R0 ; Enable Main Osc CSV
236 BTSTH #0x4, @R0 ; Check for Main Osc missing
237 BEQ NoMAINCSVreset ; Main osc available -> branch
239 BANDL #0x7, @R0 ; Disable Main Osc CSV
241 LDI #noClockStartup, R0 ; Main Clock missing -> no
242 JMP @R0 ; clock startup
247 BORL #0x4, @R0 ; Enable Sub Osc CSV
248 BTSTH #0x2, @R0 ; Check for Sub Osc missing
249 BEQ NoSUBCSVreset ; Sub osc available -> branch
251 BANDL #0xB, @R0 ; Disable Sub Osc SCSV
252 #if (CLOCKSOURCE == SUBCLOCK)
253 LDI #noClockStartup, R0 ; Sub Clock missing -> no
254 JMP @R0 ; clock startup
258 ;=========================================================================================
259 ; 7.3 Check Clock Condition
260 ;=========================================================================================
261 LDI #0x484, R0 ; Check for Default Values
266 ;=========================================================================================
267 ; 7.4 Restore Default Settings after Reset
268 ;=========================================================================================
269 ;=========================================================================================
270 ; 7.4.1 Disable Clock Modulator
271 ;=========================================================================================
272 LDI #0x04BB, R0 ; Clock Modulator Control Reg
273 BANDL #0xD, @R0 ; Disable Frequency modulation
275 BTSTL #8, @R0 ; Wait until Frequency modulation
276 BNE FMODwait ; is disabled
278 BANDL #0xE, @R0 ; Power down clock modulator
280 ;=========================================================================================
281 ; 7.4.2 Check if running on Sub Clock, change to Main Clock
282 ;=========================================================================================
283 LDI:20 #0x0484,R12 ; Check if running on sub clock
290 LDI:20 #0x04CC,R12 ; Check if Main Clock is stopped
294 BANDL #0xE, @R12 ; Start Main Oscillation
296 LDI #0x4C8, R0 ; Main Stabilisation Wait Time
297 LDI #0x04, R1 ; 32.7 ms
301 mainStabTime: ; Wait for stabilisation time
302 ClearRCwatchdog ; clear harware watchdog
309 LDI:20 #0x0484, R12 ; disable sub clock as source
310 BANDL #0xD, @R12 ; Clock source = 0x01 (Main/2)
313 ;=========================================================================================
314 ; 7.4.3 Disable Sub Clock
315 ;=========================================================================================
316 #if ENABLE_SUBCLOCK != ON
317 LDI #0x0484, R0 ; Clock source control reg CLKR
318 BANDL #0x7, @R0 ; Disable PLL
321 ;=========================================================================================
322 ; 7.4.4 Check if running on PLL, Gear Down PLL
323 ;=========================================================================================
324 LDI:20 #0x0484,R12 ; Check if running on PLL
331 LDI:20 #0x0490, R11 ; clear flags
335 STB R1, @R11 ; Set Flag for Simulator; no Effekt on
338 BANDL #0xC, @R12 ; disable PLL as clock source
339 ; Clock Source = 0x00 (Main/2)
341 LDI:20 #0x048E,R12 ; check if DivG != 0
348 ClearRCwatchdog ; clear harware watchdog
349 BTSTL #4, @R11 ; Gear Down
352 LDI #0x00,R1 ; Clear Flags
356 ;=========================================================================================
358 ;=========================================================================================
359 LDI #0x0484, R0 ; Clock source control reg CLKR
360 BANDL #0xB, @R0 ; Disable PLL
362 ;=========================================================================================
363 ; 7.4.6 Set to Main Clock
364 ;=========================================================================================
365 LDI:20 #0x0484,R12 ; Check if running on PLL
366 BANDL #0xC, @R12 ; disable PLL as clock source
367 ; Clock Source = 0x00 (Main/2)
370 ;=========================================================================================
371 ; 7.5 Set Memory Controller
372 ;=========================================================================================
373 ; Start restriction; No embedded flash
374 #if DEVICE != MB91461R
376 LDI #0x7002, R1 ; FLASH Controller Reg.
377 LDI #FLASHCONTROL, R2 ; Flash Controller Settings
378 STH R2, @R1 ; set register
379 LDI #0x7004, R1 ; FLASH Memory Wait Timing Reg.
380 LDI #FLASHREADT, R2 ; wait settings
381 STH R2, @R1 ; set register
382 LDI #0x7006, R1 ; FLASH Memory Wait Timing Reg.
383 LDI #FLASHMWT2, R2 ; wait settings
384 STB R2, @R1 ; set register
388 ;=========================================================================================
390 ;=========================================================================================
391 ;=========================================================================================
392 ; 7.6.1 Set Voltage Regulator Settings
393 ;=========================================================================================
394 ; Start restriction; No regulator settings
395 #if DEVICE != MB91461R
397 LDI #0x04CF, R0 ; REGCTR
398 LDI #REGULATORCTRL, R1
401 LDI #0x04CE, R0 ; REGSEL
402 LDI #REGULATORSEL, R1
406 ;=========================================================================================
407 ; 7.6.2 Power on Clock Modulator - Clock Modulator Part I
408 ;=========================================================================================
410 LDI #0x04BB, R0 ; Clock Modulator Control Reg
411 LDI #0x11, R1 ; Load value to Power on CM
412 ORB R1, @R0 ; Power on clock modulaor
415 ;=========================================================================================
416 ; 7.6.3 Set CLKR Register w/o Clock Mode
417 ;=========================================================================================
418 ; Set Clock source (Base Clock) for the three clock tree selections
419 ; This select Base clock is used to select afterwards the 3
420 ; Clocks for the diffenrent internal trees.
421 ; When PLL is used, first pll multiplication ratio is set and PLL is
422 ; enabled. After waiting the PLL stabilisation time via timebase
423 ; timer, PLL clock is selected as clock source.
424 LDI #0x048C, R0 ; PLL Cntl Reg. PLLDIVM/N
428 LDI #0x048E, R0 ; PLL Cntl Reg. PLLDIVG
432 LDI #0x048F, R0 ; PLL Cntl Reg. PLLMULG
436 ;=========================================================================================
438 ;=========================================================================================
439 #if ( ( CLOCKSOURCE == MAINPLLCLOCK ) || ( PSCLOCKSOURCE == PSCLOCK_PLL ) )
440 LDI #0x0484, R0 ; Clock source control reg CLKR
441 LDI #0x04, R1 ; Use PLL x1, enable PLL
442 ORB R1, @R0 ; store data to CLKR register
445 ;=========================================================================================
446 ; 7.6.5 Wait for PLL oscillation stabilisation
447 ;=========================================================================================
448 #if ((CLOCKSOURCE==MAINPLLCLOCK)||(PSCLOCKSOURCE==PSCLOCK_PLL))
449 LDI #0x0482, R12 ; TimeBaseTimer TBCR
450 LDI #0x00, R1 ; set 1024 us @ 2 MHz
453 BANDH #7, @R12 ; clear interrupt flag
455 LDI #0x0483, R0 ; clearTimeBaseTimer CTBR
461 BANDH #7, @R12 ; clear interrupt flag
462 BORH #8, @R12 ; set interrupt flag for simulator
465 ClearRCwatchdog ; clear harware watchdog
470 ;=========================================================================================
472 ;=========================================================================================
473 ;=========================================================================================
474 ; 7.6.6.1 Set CPU and peripheral clock
475 ;=========================================================================================
476 ; CPU and peripheral clock are set in one register
477 LDI #0x0486, R2 ; Set DIVR0 (CPU-clock (CLKB)
478 LDI #((CPUCLOCK << 4) + PERCLOCK), R3 ; Load CPU clock setting
480 ;=========================================================================================
481 ; 7.6.6.2 Set External Bus interface clock
482 ;=========================================================================================
483 ; set External Bus clock
484 ; Be aware to do smooth clock setting, to avoid wrong clock setting
485 ; Take care, always write 0 to the lower 4 bits of DIVR1 register
486 LDI #0x0487, R2 ; Set DIVR1
487 LDI #(EXTBUSCLOCK << 4), R3 ; Load Peripheral clock setting
490 ;=========================================================================================
491 ; 7.6.6.3 Set CAN clock prescaler
492 ;=========================================================================================
493 ; Set CAN Prescaler, only clock relevant parameter
494 LDI #0x04C0, R0 ; Set CAN ClockParameter Register
495 LDI #(PSCLOCKSOURCE + PSDVC), R1 ; Load Divider
496 STB R1, @R0 ; Set Divider
498 LDI #0x04c1, R0 ; Set CAN Clock enable Register
499 LDI #CANCLOCK, R1 ; Load CANCLOCK
500 STB R1, @R0 ; set CANCLOCK
502 ;=========================================================================================
503 ; 7.6.7 Switch to PLL Mode
504 ;=========================================================================================
505 #if ( (CLOCKSOURCE == MAINPLLCLOCK) )
508 LDI #0x0490, R0 ; PLL Ctrl Register
510 STB R1, @R0 ; Clear Flag
512 STB R1, @R0 ; Set Flag for Simulator; no Effekt on
515 LDI #0x0484, R3 ; Clock source control reg CLKR
516 BORL #0x2, @R3 ; enable PLL as clock source
520 ClearRCwatchdog ; clear harware watchdog
521 LDUB @R0, R2 ; LOAD PLLCTR to R2
522 AND R1, R2 ; GRUP, counter reach 0
526 STB R1, @R0 ; Clear Gear-Up Flag
531 ;=========================================================================================
532 ; 7.6.8 Enable Frequncy Modulation - Clock Modulator Part II
533 ;=========================================================================================
534 #if CLOMO == ON ; Only applicable if Modulator is on
535 LDI #0x04B8, R0 ; Clock Modulation Parameter Reg
536 LDI #CMPR, R1 ; Load CMP value
537 STH R1, @R0 ; Store CMP value in CMPR
539 LDI #0x04BB, R0 ; Clock Modulator Control Reg
540 LDI #0x13, R1 ; Load value to FM on CM
549 ;=========================================================================================
550 ; 7.14 call main routine
551 ;=========================================================================================
552 ClearRCwatchdog ; clear harware watchdog
553 LDI:8 #0, r4 ; Set the 1st parameter for main to 0.
555 LDI:8 #0, r5 ; Set the 2nd parameter for main to 0.
556 ;=========================================================================================
557 ; 7.15 Return from main function
558 ;=========================================================================================