1 /* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
2 /* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
3 /* ELIGIBILITY FOR ANY PURPOSES. */
4 /* (C) Fujitsu Microelectronics Europe GmbH */
5 ;=========================================================================================
7 ;=========================================================================================
14 ; 4.1 Controller device
15 ; 4.2 Boot / flash security
16 ; 4.3 Stack type and stack size
17 ; 4.4 Copy code from flash to I-RAM
19 ; 4.6 Low-level library interface
20 ; 4.7 Clock Configuration
21 ; 4.7.1 Clock selection
22 ; 4.7.2 Select Clock Modulator
23 ; 4.8 External bus interface
24 ; 4.8.1 Select chipselect
25 ; 4.8.2 Set memory addressing for chipselects
26 ; 4.8.3 Configure chipselect area
27 ; 4.8.4 Set wait cycles for chipselects
28 ; 4.8.5 Configure chipselects SDRAM memory only
29 ; 4.8.6 Referesh control register RCR
30 ; 4.8.7 Terminal and timing control register
31 ; 4.8.8 Enable / disable I-cache
32 ; 4.8.9 Enable CACHE for chipselect
33 ; 4.8.10 Select external bus mode (data lines)
34 ; 4.8.11 Select external bus mode (address lines)
35 ; 4.8.12 Select external bus mode (control signals)
37 ; 5 Definitions of Configurations
39 ; 6 Section and data declaration
40 ; 6.1 Define stack size
44 ; 7.1 Initialise stack pointer and table base register
45 ; 7.2 Check for CSV reset and set CSV
46 ; 7.3 Check clock condition
47 ; 7.4 Restore default settings after reset
48 ; 7.4.1 Disable clock modulator
49 ; 7.4.2 Check if running on sub clock, change to main clock
50 ; 7.4.3 Disable sub clock
51 ; 7.4.4 Check if running on PLL, gear down PLL
53 ; 7.4.6 Set to main clock
54 ; 7.5 Set memory controller
56 ; 7.6.1 Set Voltage Regulator Settings
57 ; 7.6.2 Power on clock modulator - clock modulator part I
58 ; 7.6.3 Set CLKR register w/o clock mode
60 ; 7.6.5 Wait for PLL oscillation stabilisation
62 ; 7.6.6.1 Set CPU and peripheral clock
63 ; 7.6.6.2 Set external bus interface clock
64 ; 7.6.6.3 Set CAN clock prescaler
65 ; 7.6.6.4 Switch main clock mode
66 ; 7.6.6.5 Switch sub clock mode
67 ; 7.6.6.6 Switch to PLL mode
68 ; 7.6.7 Enable frequncy modulation - clock modulator part II
69 ; 7.7 Set BusInterface
70 ; 7.7.1 Disable all CS
71 ; 7.7.2 Clear TCR register
80 ; 7.7.11 Set special SDRAM config register
81 ; 7.7.12 set Port function register
82 ; 7.7.13 Set TCR register
83 ; 7.7.14 Enable cache for selected CS
84 ; 7.7.15 Set SDRAM referesh control register
85 ; 7.7.16 Enable used CS
86 ; 7.7.17 I-cache on/off
87 ; 7.7.18 Set port function register to general as I/O-port
88 ; 7.8 Copy code from flash to I-RAM
91 ; 7.11 Copy Init section from ROM to RAM
92 ; 7.12 C library initialization
93 ; 7.13 Call C++ constructors
94 ; 7.14 Call main routine
95 ; 7.15 Return from main function
97 ;=========================================================================================
99 ;=========================================================================================
100 ; Fujitsu Microelectronics Europe GmbH
101 ; http://emea.fujitsu.com/microelectronics
103 ; The following software is for demonstration purposes only. It is not fully
104 ; tested, nor validated in order to fullfill its task under all circumstances.
105 ; Therefore, this software or any part of it must only be used in an evaluation
106 ; laboratory environment.
107 ; This software is subject to the rules of our standard DISCLAIMER, that is
108 ; delivered with our SW-tools on the Fujitsu Microcontrollers CD/DVD (V3.4 or
109 ; higher "\START.HTM") or on our Internet Pages:
110 ; http://www.fme.gsdc.de/gsdc.htm
111 ; http://emea.fujitsu.com/microelectronics
113 ;=========================================================================================
115 ;=========================================================================================
117 ;=========================================================================================
118 ; MB914xx (FR60 CORE ONLY) Series C Compiler's
120 ; Startup file for memory and basic controller initialisation
121 ;=========================================================================================
124 ; 2005-04-18 V1.0 UMa Release first version
125 ; 2005-06-17 V1.1 UMa Added bus interface, modified c++ startup
126 ; 2005-06-28 V1.2 UMa minor changes
127 ; 2005-07-27 V1.3 UMa default values changed
128 ; 2005-10-04 V1.4 UMa changed code 'Call main Routine'
129 ; Added secutiy section for MB91F467D
130 ; Added Flash Access Read Timing setting section;
131 ; 2005-10-04 V1.5 UMa Added Flash Controller Section
132 ; 2005-10-28 V1.6 UMa Check for CSV reset
133 ; 2005-11.16 V1.7 UMa Monitor Debugger support added: Copy of intvect Table
134 ; Ext. Int 0 as abort function
135 ; Changed PLL-Startup, Reset HWWD added
136 ; 2005-11-16 V1.7 UMa Examples for MUL_G changed
137 ; 2006-02-14 V1.8 UMa mb91464a added
138 ; Settings for Clock Spervisor added
139 ; Name of Section SECURITY changed to SECURITY_VECTORS
140 ; Example values for gear-up changed
141 ; 2006-03-17 V1.9 UMa Changed Startup for Monitor Debugger
142 ; 2006-04-24 v2.0 UMa Added MB91465K and MB91469G
143 ; 2006-05-03 v2.1 UMa Added MB91461R; removed MB91V460A
144 ; Added settings for the external bus-interface
145 ; 2006-07-28 v2.2 UMa Added I-RAM copy function (ROM -> IRAM)
146 ; Added default settings for FLASH Access Read Timing
148 ; Changed default settings for FLASH cache configuration
150 ; Changed check for clock startup
151 ; 2006-08-16 v2.3 MVo Corrected Boot Security Sector Addresses for MB91469G
152 ; 2006-10-06 v2.4 UMa Added new devices
153 ; Corrected typo in I_RAM to flash copy function
154 ; Changed default settings for flash cache configuration
155 ; Changed comments for SDRAM bus interface configuration
156 ; Changed comments and default setting of CAN Prescaler
158 ; Added Settings for REGSEL Register
159 ; 2007-02-13 v2.5 UMa Introduction of default configurations
160 ; Changed I_RAM to flash copy function
163 ;=========================================================================================
165 ;=========================================================================================
167 ; CHECK ALL OPTIONS WHETHER THEY FIT TO THE APPLICATION;
169 ; Configure this startup file in the "Settings" section. Search for
170 ; comments with leading "; <<<". This points to the items to be set.
171 ;=========================================================================================
178 ;=========================================================================================
179 ; 4.1 Controller Device
180 ;=========================================================================================
181 #set MB91464A 2 ; MB91460 series
183 #set MB91467B 10 ; MB91460 series
185 #set MB91467C 11 ; MB91460 series
187 #set MB91467D 4 ; MB91460 series
189 #set MB91469G 6 ; MB91460 series
191 #set MB91465K 3 ; MB91460 series
193 #set MB91463N 8 ; MB91460 series
195 #set MB91461R 1 ; MB91460 series
196 #set MB91467R 5 ; MB91460 series
198 #set MB91465X 9 ; MB91460 series
200 #set others 7 ; MB91460 series
204 #set DEVICE MB91465K ; <<< select device
206 ;=========================================================================================
207 ; 4.2 Boot / Flash Security
208 ;=========================================================================================
210 #set BOOT_FLASH_SEC OFF ; <<< BOOT and Flash Security Vector
212 ; The flash devices have two flash and two boot security vectors. It is important to set
213 ; the four vectors correctly. Otherwise it might be possible, that the flash device is
214 ; not accessible any more via the bootrom. Please read carefully the hardware manual.
216 ; OFF: The security feature is switch off. The section SECURITY_VECTORS is reserved and
217 ; the vectors are set.
218 ; ON: IMPORTANT! The security vectors are not set. But the section SECURITY_VECTORS
221 ; Note: This feature is not supported by every device. Please check the data sheet. This
222 ; feature is not available on MB91461R.
224 ;=========================================================================================
225 ; 4.3 Stack Type and Stack Size
226 ;=========================================================================================
228 #set USRSTACK 0 ; user stack: for main program
229 #set SYSSTACK 1 ; system stack: for main program and
233 #set STACKUSE SYSSTACK ; <<< set active stack
235 #set STACK_RESERVE ON ; <<< reserve stack area in
237 #set STACK_SYS_SIZE 0x400-4 ; <<< byte size of System stack
238 #set STACK_USR_SIZE 0x2 ; <<< byte size of User stack
240 #set STACK_FILL OFF ; <<< fills the stack area with pattern
241 #set STACK_PATTERN 0x55AA6699 ; <<< the pattern to write to stack
243 ; - If the active stack is set to SYSSTACK, it is used for main program and interrupts.
244 ; In this case, the user stack could be set to a dummy size. If the active stack is
245 ; set to user stack, it is used for the main program but the system stack is
246 ; automatically activated, if an interrupt is serviced. Both stack areas must have a
248 ; - If STACK_RESERVE is ON, the sections USTACK and SSTACK are reserved in this module.
249 ; Otherwise, they have to be reserved in other modules. If STACK_RESERVE is OFF, the
250 ; size definitions STACK_SYS_SIZE and STACK_USR_SIZE have no meaning.
251 ; - Even if they are reverved in other modules, they are still initialised in this
254 ; Note: Several library functions require quite a big stack (due to ANSI).
255 ; Check the stack information files (*.stk) in the LIB\911 directory.
257 ;=========================================================================================
258 ; 4.4 Copy code from Flash to I-RAM
259 ;=========================================================================================
261 #set I_RAM ON ; <<< select if code in section IRAM
264 ; If this option is activated code located in the section IRAM is copied during startup
265 ; from ROM to the instruction-RAM. The code is linked for the instruction-RAM.
267 ;=========================================================================================
268 ; 4.5 Low-Level Library Interface
269 ;=========================================================================================
271 #set CLIBINIT OFF ; <<< select ext. libray usage
273 ; This option has only to be set, if stream-IO/standard-IO function of the C-libraray
274 ; have to be used (printf(), fopen()...). This also requires low-level functions to be
275 ; defined by the application software.
276 ; For other library functions like (e.g. sprintf()) all this is not necessary. However,
277 ; several functions consume a large amount of stack.
279 ;=========================================================================================
281 ;=========================================================================================
283 #set CPLUSPLUS OFF ; <<< activate if c++ files are used
285 ; In the C++ specifications, when external or static objects are used, a constructor
286 ; must be called followed by the main function. Because four-byte pointers to the main
287 ; function are stored in the EXT_CTOR_DTOR section, call a constructor sequentially from
288 ; the lower address of the four addresses in that section. If using C++ sources,
289 ; activate this function to create the section EXT_CTOR_DTOR.
291 ;=========================================================================================
292 ; 4.7 Clock Configuration
293 ;=========================================================================================
294 ;=========================================================================================
295 ; 4.7.1 Clock Selection
296 ;=========================================================================================
301 ; Sub-oscillation input: 32 kHz
302 #set SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ 0x11
304 ; Oscillation input: 4 MHz
305 #set MAIN_4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ 0x21
306 #set PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ 0x22
307 #set PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ 0x23
308 #set PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ 0x24
309 #set PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ 0x25
310 #set PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ 0x26 ;not MB91V460, ...
311 #set PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ 0x27 ;not MB91V460, ...
313 ; MB91461R only: Oscillation input: 10 MHz
314 #set PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ 0x41
316 ; MB91461R only: Oscillation input: 20 MHz
317 #set PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ 0x51
324 #set CLOCKSPEED PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ
325 ; ; <<< Select clock configuration
327 ; There are different default configurations available, where all necessary settings for
328 ; clocks and the related registers are made. Beside this configurations, there is the
329 ; possibility to define a user configuration in the chapter "Definition of
333 ; The clock registers are not set by the start-up file.
335 ; - PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ means:
336 ; Main oszillation = 4 MHz, PLL is activated
337 ; CPU clock (CLKB) = 64 MHZ
338 ; Peripheral clock (CLKP) = 16 MHZ
339 ; Ext. bus clock (CLKT) = 32 MHZ
340 ; CAN clock (CLKCAN) = 16 MHz, using PLLx
343 ; The user configuration definded in the chapter "Definition of Configurations" is set.
345 ; Note: Not all frequencies are supported by every device. Please see the hardware
348 ;=========================================================================================
349 ; 4.7.2 Select Clock Modulator
350 ;=========================================================================================
352 #set CLOMO OFF ; <<< Enable /disable clock modulator
354 #set CMPR 0x026F ; <<< Ref. to the data sheet, CMPR
356 ; Please refer to the data sheet of the device if you enable clock modulation. The
357 ; register CMPR dependant on the PLL-Clock.
359 ; Note: If the CLKCAN source is set either to main oscillator or to PLL output then the
360 ; clock for the CAN is not influenced by the clock modulation. If the CLKCAN
361 ; source is set CPU clock (CLKB) then the clock for the CAN is also modulated (if
362 ; the clock modulator is enabled).
364 ; Note: If the clock modulator is enabled, the wait states of the internal flash wait
365 ; states must be adapted to maximum frequency. Please check the wait states
368 ; Note: This feature is not supported by every device, e.g. MB91461. Please check the
371 ;=========================================================================================
372 ; 4.8 External Bus Interface
374 ; The rest of the configuration is only applicable for devices with an external bus
377 ; If the device does not offer an external bus interface, the configuration can be
378 ; stoped at this point.
380 ;=========================================================================================
382 #set EXTBUS DEFAULT ; <<< Ext. Bus on/off
384 ; ON - The ext. bus interface is enabled and is configured as
387 ; OFF - The ext. bus interface is diabled. The port function
388 ; registers are set to general I/O. The registers of
389 ; ext. bus interface will not be touched by the start-up
391 ; Be aware, that the device might be conifgured in ext.
392 ; bus mode by default after reset.
394 ; DEFAULT - Neither the register nor the respective port function
395 ; registers are touched by the start-up file.
396 ; Be aware, that the device might be conifgured in ext.
397 ; bus mode by default after reset.
400 ; Note: This feature is not supported by every device. Please check the data sheet. The
401 ; following devices for example do not offer an external bus interface: MB91464A,
402 ; MB91467C, MB91465K, MB91463N, MB91465X.
404 ;=========================================================================================
405 ; 4.8.1 Select Chipselect (Only EXTBUS == ON)
406 ;=========================================================================================
408 #set CS0 OFF ; <<< select CS (ON/OFF)
409 #set CS1 OFF ; <<< select CS (ON/OFF)
410 #set CS2 OFF ; <<< select CS (ON/OFF)
411 #set CS3 OFF ; <<< select CS (ON/OFF)
412 #set CS4 OFF ; <<< select CS (ON/OFF)
413 #set CS5 OFF ; <<< select CS (ON/OFF)
414 #set CS6 OFF ; <<< select CS (ON/OFF)
415 #set CS7 OFF ; <<< select CS (ON/OFF)
416 #set SDRAM OFF ; <<< select if a SDRAM is connected
419 #set ENACSX B'00000000 ; <<< set CS, ENACSX
421 ; ||||||||__ CS0 bit, enable/disable CS0 (1/0)
422 ; |||||||___ CS1 bit, enable/disable CS1 (1/0)
423 ; ||||||____ CS2 bit, enable/disable CS2 (1/0)
424 ; |||||_____ CS3 bit, enable/disable CS3 (1/0)
425 ; ||||______ CS4 bit, enable/disable CS4 (1/0)
426 ; |||_______ CS5 bit, enable/disable CS5 (1/0)
427 ; ||________ CS6 bit, enable/disable CS6 (1/0)
428 ; |_________ CS7 bit, enable/disable CS7 (1/0)
430 ; Note: If the SWB Monitor Debugger is used, set the CS1 (external RAM only) or CS0 and
431 ; CS 1 (external RAM and flash) to off.
433 ; Note: Not all Chipselects are supported by the different devices. Please check the
436 ;=========================================================================================
437 ; 4.8.2 Set memory addressing for Chipselects (only EXTBUS == ON)
438 ;=========================================================================================
440 #set AREASEL0 0x0000 ; <<< set start add. for CS0, ASR0
441 #set AREASEL1 0x0000 ; <<< set start add. for CS1, ASR1
442 #set AREASEL2 0x0000 ; <<< set start add. for CS2, ASR2
443 #set AREASEL3 0x0000 ; <<< set start add. for CS3, ASR3
444 #set AREASEL4 0x0000 ; <<< set start add. for CS4, ASR4
445 #set AREASEL5 0x0000 ; <<< set start add. for CS5, ASR5
446 #set AREASEL6 0x0000 ; <<< set start add. for CS6, ASR6
447 #set AREASEL7 0x0000 ; <<< set start add. for CS7, ASR7
449 ; Configure the starting address of each used Chipselect. Chipselects which are not used
450 ; (not set to ON in "Select Chipselect") need not be set (setting ignored).
452 ; NOTE: Just the upper 16-bit of the start address must be set, e.g. when using start
453 ; address 0x00080000 set 0x0008.
455 ;=========================================================================================
456 ; 4.8.3 Configure Chipselect Area (only EXTBUS == ON)
457 ;=========================================================================================
459 #set CONFIGCS0 B'0000000000000000 ; <<< Config. CS0, ACR0
460 #set CONFIGCS1 B'0000000000000000 ; <<< Config. CS1, ACR1
461 #set CONFIGCS2 B'0000000000000000 ; <<< Config. CS2, ACR2
462 #set CONFIGCS3 B'0000000000000000 ; <<< Config. CS3, ACR3
463 #set CONFIGCS4 B'0000000000000000 ; <<< Config. CS4, ACR4
464 #set CONFIGCS5 B'0000000000000000 ; <<< Config. CS5, ACR5
465 #set CONFIGCS6 B'0000000000000000 ; <<< Config. CS6, ACR6
466 #set CONFIGCS7 B'0000000000000000 ; <<< Config. CS7, ACR7
468 ; ||||||||||||||||__ TYP0 bit, TYP0-4 bits select access type
469 ; |||||||||||||||___ TYP1 bit
470 ; ||||||||||||||____ TYP2 bit
471 ; |||||||||||||_____ TYP3 bit
472 ; ||||||||||||______ LEND bit, select little '1' or big endian '0'
473 ; |||||||||||_______ WREN bit, en-/disable (1/0) Write access
474 ; ||||||||||________ PFEN bit, en-/disable (1/0) pre-fetch
475 ; |||||||||_________ SREN bit, en-/disable (1/0) share of BRQ & BGRNTX
476 ; ||||||||__________ BST0 bit, BSTx bits select burst size
477 ; |||||||___________ BST1 bit
478 ; ||||||____________ DBW0 bit, DBWx select data bus width
479 ; |||||_____________ DBW1 bit
480 ; ||||______________ ASZ0 bit, ASZx bits select address size of CS
481 ; |||_______________ ASZ1 bit
482 ; ||________________ ASZ2 bit
483 ; |_________________ ASZ3 bit
487 ; TYP3 TYP2 TYP1 TYP0 : Select access type of each CS
488 ; 0 0 X X : Normal access (asynchronous SRAM, I/O,
489 ; single/page/busrt-ROM/FLASH)
490 ; 0 1 X X : Address/data multiplexed (8bit / 16bit bus width only)
491 ; 0 X X 0 : WAIT insertion by RDY disabled
492 ; 0 X X 1 : WAIT insertion by RDY enabled
493 ; 0 X 0 X : The WR0X pin to the WR3X pin are used as write strobes
494 ; (WRX is fixed at H-Level)
495 ; 0 X 1 X : The WRX pin is used as write strobe
496 ; 1 0 0 0 : Memory type A: SDRAM/FCRAM (Auto pre-charge used)
497 ; 1 0 0 1 : Memory type B: FCRAM (Auto pre-charge used)
498 ; 1 0 1 0 : setting not allowed
499 ; 1 0 1 1 : setting not allowed
500 ; 1 1 0 0 : setting not allowed
501 ; 1 1 0 1 : setting not allowed
502 ; 1 1 1 0 : setting not allowed
503 ; 1 1 1 1 : mask area setting
505 ; LEND : select BYTE ordering
509 ; WREN : enable or disable write access
513 ; PFEN : Enable or disable the pre-fetch
517 ; SREN : Enable or disable the sharing of BRQ and BGRNTX
519 ; 1 : enabled (CSx pin High-Z)
521 ; BST1 BST0 : set burst size of chip select area
522 ; 0 0 : 1 burst (single access)
523 ; 0 1 : 2 bursts (Address boundary 1 bit)
524 ; 1 0 : 4 bursts (Address boundary 2 bit)
525 ; 1 1 : 8 bursts (Address boundary 3 bit)
527 ; DBW1 DBW0 : Set data bus width
528 ; 0 0 : 8-bit (BYTE access)
529 ; 0 1 : 16-bit (HALF-WORD access)
530 ; 1 0 : 32-bit (WORD access)
533 ; ASZ3 ASZ2 ASZ1 ASZ0 : Select memory size of each chipselect
534 ; 0 0 0 0 : 64 Kbyte (0x01.0000 bytes; use ASR A[31:16] bits)
535 ; 0 0 0 1 : 128 Kbyte (0x02.0000 bytes; use ASR A[31:17] bits)
536 ; 0 0 1 0 : 256 Kbyte (0x04.0000 bytes; use ASR A[31:18] bits)
537 ; 0 0 1 1 : 512 Kbyte (0x08.0000 bytes; use ASR A[31:19] bits)
538 ; 0 1 0 0 : 1 Mbyte (0x10.0000 bytes; use ASR A[31:20] bits)
539 ; 0 1 0 1 : 2 Mbyte (0x20.0000 bytes; use ASR A[31:21] bits)
540 ; 0 1 1 0 : 4 Mbyte (0x40.0000 bytes; use ASR A[31:22] bits)
541 ; 0 1 1 1 : 8 Mbyte (0x80.0000 bytes; use ASR A[31:23] bits)
542 ; 1 0 0 0 : 16 Mbyte (0x100.0000 bytes; use ASR A[31:24] bits)
543 ; 1 0 0 1 : 32 Mbyte (0x200.0000 bytes; use ASR A[31:25] bits)
544 ; 1 0 1 0 : 64 Mbyte (0x400.0000 bytes; use ASR A[31:26] bits)
545 ; 1 0 1 1 : 128 Mbyte (0x800.0000 bytes; use ASR A[31:27] bits)
546 ; 1 1 0 0 : 256 Mbyte (0x1000.0000 bytes; use ASR A[31:28] bits)
547 ; 1 1 0 1 : 512 Mbyte (0x2000.0000 bytes; use ASR A[31:29] bits)
548 ; 1 1 1 0 : 1024 Mbyte(0x4000.0000 bytes; use ASR A[31:30] bits)
549 ; 1 1 1 1 : 2048 Mbyte(0x8000.0000 bytes; use ASR A[31] bit)
551 ;=========================================================================================
552 ; 4.8.4 Set Wait cycles for Chipselects for ordinary businterface (only EXTBUS == ON)
553 ;=========================================================================================
555 ; Ordinary bus interface (w/o SDRAM and FRAM) (ACRx_Type = 0xxx)
557 #set WAITREG0 B'0000000000000000 ; <<< CS0 Waitstates, AWR0
558 #set WAITREG1 B'0000000000000000 ; <<< CS1 Waitstates, AWR1
559 #set WAITREG2 B'0000000000000000 ; <<< CS2 Waitstates, AWR2
560 #set WAITREG3 B'0000000000000000 ; <<< CS3 Waitstates, AWR3
561 #set WAITREG4 B'0000000000000000 ; <<< CS4 Waitstates, AWR4
562 #set WAITREG5 B'0000000000000000 ; <<< CS5 Waitstates, AWR5
564 ; ||||||||||||||||__ W00 bit, RDY/WRY-> CSX hold cycle
565 ; |||||||||||||||___ W01 bit, CSX->RDX/WRX setup extension cycle
566 ; ||||||||||||||____ W02 bit, Address -> CSX Delay selection
567 ; |||||||||||||_____ W03 bit, WR0X to WR3X/WRX outout timing
568 ; ||||||||||||______ W04 bit, W04/W05 Write recovery cycle
569 ; |||||||||||_______ W05 bit
570 ; ||||||||||________ W06 bit, W06/07 Read -> Write idle cycle
571 ; |||||||||_________ W07 bit selection
572 ; ||||||||__________ W08 bit, W08-W11 Intra-page access cycle
573 ; |||||||___________ W09 bit select (0-15 cycles)
574 ; ||||||____________ W10 bit
575 ; |||||_____________ W11 bit
576 ; ||||______________ W12 bit, W12-W15 First access wait cycle
577 ; |||_______________ W13 bit select (0-15 cycles)
578 ; ||________________ W14 bit
579 ; |_________________ W15 bit
582 ; SDRAM and FRAM bus interface (ACRx_Type = 100x)
584 #set WAITREG6 B'0000000000000000 ; <<< CS6 Waitstates, AWR6
585 #set WAITREG7 B'0000000000000000 ; <<< CS7 Waitstates, AWR7
587 ; ||||||||||||||||__ W00 bit, W0-W1 RAS precharge cycles
588 ; |||||||||||||||___ W01 bit
589 ; ||||||||||||||____ W02 bit, W2-W3 RAS active Time
590 ; |||||||||||||_____ W03 bit
591 ; ||||||||||||______ W04 bit, W4-W5 Write recovery cycle
592 ; |||||||||||_______ W05 bit
593 ; ||||||||||________ W06 bit, W6-W7 Read->Write idle cycle
594 ; |||||||||_________ W07 bit
595 ; ||||||||__________ W08 bit, W8-W10 CAS latency
596 ; |||||||___________ W09 bit
597 ; ||||||____________ W10 bit
598 ; |||||_____________ W11 bit, reserved
599 ; ||||______________ W12 bit, W12-W16 RAS-CAS delay
600 ; |||_______________ W13 bit
601 ; ||________________ W14 bit
602 ; |_________________ W15 bit, reserved
605 ; The bit meaning depends on the configured bus interface type. The bus interface can be
606 ; configured for different memory types. Depending on the memory type, the wait register
607 ; bits have a differnt meaning. CS0-5 should be configurable as ordinary bus interface
608 ; (w/o SDRAM and FRAM) and CS6-7 should be configurable as SDRAM and FRAM. It is also
609 ; possible and for some devices neccessary to configure other two chip selects as SDRAM
610 ; or FRAM interface. In such a case be aware of the bit meanings.
613 ; Ordinary bus interface (w/o SDRAM and FRAM) (ACRx_Type = 0xxx)
614 ; --------------------------------------------------------------
618 ; W00 : RDY/WRX -> CSX hold extension cycle
622 ; W01 : CSX -> RDX/WRX setup extention cycle
626 ; W02 : Address -> CSX Delay selection
627 ; 0 : no delay selected
630 ; W03 : WR0X to WR3X/WRX outout timing selection
631 ; 0 : MCLK synchronous write output enable (ASX=L)
632 ; 1 : Asynchronous write strobe output (norma operation)
634 ; W05 W04 : select Write recovery cycle
640 ; W07 W06 : Read -> Write idle cycle selection
646 ; W11 W10 W09 W08 : Intra-page access cycle select (0-15 cycles)
647 ; 0 0 0 0 : 0 Wait state
648 ; 0 0 0 1 : 1 Auto-wait cycle
649 ; 0 0 1 0 : 2 Auto-wait cycle
651 ; 1 1 1 1 : 15 Auto wait cycles
653 ; W15 W14 W13 W12 : First access wait cycle can be set (0-15 cycles)
654 ; 0 0 0 0 : 0 Wait state
655 ; 0 0 0 1 : 1 Auto-wait cycle
656 ; 0 0 1 0 : 2 Auto-wait cycle
658 ; 1 1 1 1 : 15 Auto wait cycles
662 ; SDRAM and FRAM bus interface (ACRx_Type = 100x)
663 ; -----------------------------------------------
667 ; W01 W00 : RAS precharge cycles.
673 ; W03 W02 : RAS active Time
679 ; W05 W04 : set Write recovery cycle (1 - 4 cycles)
685 ; W07 W06 : set Read -> Write idle Cycle (1 - 4 cycles)
691 ; W10 W09 W08 : set CAS latency (1 - 8 cycles)
697 ; W11 : RESERVED, ALWAYS WRITE 0 !
699 ; W14 W13 W12 : set RAS-CAS delay (1 - 8 cycles)
705 ; W15 : RESERVED, ALWAYS WRITE 0 !
708 ; The bit meaning depends on the configured bus interface type
710 ;=========================================================================================
711 ; 4.8.5 Configure Chipselects for SDRAM memory only (only EXTBUS == ON and SDRAM)
712 ;=========================================================================================
714 #set MEMCON B'00000111 ; <<< set special SDRAM register, MCRA
716 ; ||||||||__ ABS0 bit, set max. active banks (ABS1,0)
717 ; |||||||___ ABS1 bit
718 ; ||||||____ BANK bit, set number of banks connected to CS
719 ; |||||_____ WBST bit, Write burst enable/disable
720 ; ||||______ PSZ0 bit, Set page size (PSZ2-0)
721 ; |||_______ PSZ1 bit
722 ; ||________ PSZ2 bit
723 ; |_________ reserved, always write 0
725 ; When connecting SDRAM/FCRAM TYP3-0=1000 in ACRx register the following register must
730 ; ABS1 ABS0 : Set maximum number of bank, active at same time
736 ; BANK : Set number of connected SDRAM banks
740 ; WBST : Write burst enable
744 ; PSZ2 PSZ1 PS0 : Select page size of connected memory
745 ; 0 0 0 : 8-bit column address = A0 to A7
746 ; 0 0 1 : 9-bit column address = A0 to A8
747 ; 0 1 0 : 10-bit column address = A0 to A9
748 ; 0 1 1 : 11-bit column address = A0 to A9, A11
749 ; 1 X X : setting disabled
752 ;=========================================================================================
753 ; 4.8.6 Referesh Control Register RCR (only EXTBUS == ON and SDRAM)
754 ;=========================================================================================
756 #set REFRESH B'1110001001000111 ; <<< set Refresh Control Register, RCR
758 ; ||||||||||||||||__ TRC0 bit, set refresh cycle (TRC2-0)
759 ; |||||||||||||||___ TRC1 bit
760 ; ||||||||||||||____ TRC2 bit
761 ; |||||||||||||_____ PON bit, set power-on control
762 ; ||||||||||||______ RFC0 bit, set refresh count (RFC2-0)
763 ; |||||||||||_______ RFC1 bit
764 ; ||||||||||________ RFC2 bit
765 ; |||||||||_________ BRST bit, set burst refresh control
766 ; ||||||||__________ RFINT0 bit, set auto refresh interval
767 ; |||||||___________ RFINT1 bit, (RFINT5-0)
768 ; ||||||____________ RFINT2 bit
769 ; |||||_____________ RFINT3 bit
770 ; ||||______________ RFINT4 bit
771 ; |||_______________ RFINT5 bit
772 ; ||________________ RRLD bit, counter refresh strat control
773 ; |_________________ SELF bit, self refresh control
776 ; This register sets various SDRAM refresh controls. When SDRAM control is not set for
777 ; any area, the setting of this register is meaningless, but do not change the register
778 ; value at initial state. When a read is performed using a read-modify-write
779 ; instruction, 0 always returns from the SELF, RRLD, and PON bits.
784 ; TRC2 TRC1 TRC0 : Refresh Cycle
794 ; PON : Power-on control
796 ; 1 : power-on sequence started
798 ; RFC2 RFC1 RFC0 : Refresh Count
805 ; 1 1 0 : Setting disabled
806 ; 1 1 1 : Refresh disabled
808 ; BRST : Burst refresh control
809 ; 0 : Decentralised refresh
812 ; RFINT[5-0] : auto refresh interval
814 ; RRLD : Refresh counter Activation Control
816 ; 1 : Autorefresh performed once, then value of RFINT reloaded
818 ; SELF : Self refresh control
819 ; 0 : auto refresh or power down
820 ; 1 : Transitions to self-refresch mode
822 ; NOTE: PON bit is set after the above setting. Do not set PON bit to 1 in the
823 ; above setting. Otherwise the settings are not correct set.
825 ;=========================================================================================
826 ; 4.8.7 Terminal and Timing Control Register (only EXTBUS == ON)
827 ;=========================================================================================
829 #set TIMECONTR B'00000000 ; <<< set TCR register, TCR
831 ; ||||||||__ RDW0 bit, set wait cycle reduction (RDW0,1)
832 ; |||||||___ RDW1 bit
833 ; ||||||____ OHT0 bit, set output hold delay (OHT1,0)
834 ; |||||_____ OHT1 bit
835 ; ||||______ reserved, always write 0
836 ; |||_______ PCLR bit, prefetch buffer clear
837 ; ||________ PSUS bit, prefetch suspend
838 ; |_________ BREN bit, BRQ input enable
840 ; This register controls the general functions of the external bus interface controller
841 ; such as the common-pin function setting and timing control.
845 ; RDW1 RDW0 : Wait cycle reduction
846 ; 0 0 : Normal Wait (AWR0 - 7 setting)
847 ; 0 1 : 1/2 of AWR0 - 7 setting value
848 ; 1 0 : 1/4 of AWR0 - 7 setting value
849 ; 1 1 : 1/8 of AWR0 - 7 setting value
851 ; OHT1 OHT0 : Output hold selection bit
852 ; 0 0 : Output performed at falling edge of SYSCLK/MCLK
853 ; 0 1 : Output performed about 3ns after falling edge of SYSCLK/MCLK
854 ; 1 0 : Output performed about 4ns after falling edge of SYSCLK/MCLK
855 ; 1 1 : Output performed about 5ns after falling edge of SYSCLK/MCLK
857 ; PCLR : Prefetch buffer all clear
859 ; 1 : Prefetch buffer cleared
861 ; PSUS : prefetch suspension bit
862 ; 0 : Prefetch enabled
863 ; 1 : Prefetch disabled
865 ; BREN : BRQ input enable
867 ; 1 : enabled, Bus sharing of BRQ/BGRNTX performed
869 ; Note: This function is used to prevent an excessive access cycle wait while operating
870 ; at a low-speed clock (such as while base clock operating at low speed or
871 ; high frequency division rate for external bus clock).
873 ;=========================================================================================
874 ; 4.8.8 Enable/Disable I-CACHE (only EXTBUS == ON)
875 ;=========================================================================================
877 #set C1024 1 ; CACHE Size: 1024 BYTE
878 #set C2048 2 ; CACHE Size: 2048 BYTE
879 #set C4096 3 ; CACHE Size: 4096 BYTE
882 #set CACHE OFF ; <<< Select use of cache
883 #set CACHE_SIZE C4096 ; <<< Select size of cache, ISIZE
885 ; It is possible to use cache functionality on the I-Bus on several devices. Please
886 ; check the corresponidng data sheet if this feature is available on a certain device
887 ; and for the size of the cache. This is the general cache configuration. It is possible
888 ; to configure for each CS area, if the cache should be used.
890 ; Note: This feature is not supported by every device. Please check the data sheet. The
891 ; feature is for example supported by MB91461R, MB91469G.
893 ;=========================================================================================
894 ; 4.8.9 Enable CACHE for chipselect (only EXTBUS == ON)
895 ;=========================================================================================
897 #set CHEENA B'11111111 ; <<< en-/disable cache, CHER
899 ; ||||||||__ CHE0 bit, CS0 area
900 ; |||||||___ CHE1 bit, CS1 area
901 ; ||||||____ CHE2 bit, CS2 area
902 ; |||||_____ CHE3 bit, CS3 area
903 ; ||||______ CHE4 bit, CS4 area
904 ; |||_______ CHE5 bit, CS5 area
905 ; ||________ CHE6 bit, CS6 area
906 ; |_________ CHE7 bit, CS7 area
908 ; Additional to the general cache enable setting, select which CS area should be used
909 ; with cache functionality.
911 ; Note: Not all Chipselects are supported by the different devices. Please check the
914 ; Note: This feature is not supported by every device. Please check the data sheet. The
915 ; Feature is supported by MB91461R, MB91469G.
917 ;=========================================================================================
918 ; 4.8.10 Select External bus mode (Data lines) (only EXTBUS == ON)
919 ;=========================================================================================
921 #set PFUNC0 B'11111111 ;<<< Data lines or GIO, PFR00
923 ; ||||||||__ D24 / P00_0
924 ; |||||||___ D25 / P00_1
925 ; ||||||____ D26 / P00_2
926 ; |||||_____ D27 / P00_3
927 ; ||||______ D28 / P00_4
928 ; |||_______ D29 / P00_5
929 ; ||________ D30 / P00_6
930 ; |_________ D31 / P00_7
932 #set PFUNC1 B'11111111 ;<<< Data lines or GIO, PFR01
934 ; ||||||||__ D16 / P01_0
935 ; |||||||___ D17 / P01_1
936 ; ||||||____ D18 / P01_2
937 ; |||||_____ D19 / P01_3
938 ; ||||______ D20 / P01_4
939 ; |||_______ D21 / P01_5
940 ; ||________ D22 / P01_6
941 ; |_________ D23 / P01_7
943 #set PFUNC2 B'11111111 ;<<< Data lines or GIO, PFR02
945 ; ||||||||__ D8 / P02_0
946 ; |||||||___ D9 / P02_1
947 ; ||||||____ D10 / P02_2
948 ; |||||_____ D11 / P02_3
949 ; ||||______ D12 / P02_4
950 ; |||_______ D13 / P02_5
951 ; ||________ D14 / P02_6
952 ; |_________ D15 / P02_7
954 #set PFUNC3 B'11111111 ;<<< Data lines or GIO, PFR03
956 ; ||||||||__ D0 / P03_0
957 ; |||||||___ D1 / P03_1
958 ; ||||||____ D2 / P03_2
959 ; |||||_____ D3 / P03_3
960 ; ||||______ D4 / P03_4
961 ; |||_______ D5 / P03_5
962 ; ||________ D6 / P03_6
963 ; |_________ D7 / P03_7
965 ; Select if the ports are set to
966 ; 1 : External bus mode, I/O for data lines or
967 ; 0 : General I/O port (GIO)
969 ; Note: Not all data-lines are supported by the different devices. Please check the data
972 ;=========================================================================================
973 ; 4.8.11 Select External bus mode (Address lines) (only EXTBUS == ON)
974 ;=========================================================================================
976 #set PFUNC4 B'11111111 ;<<< Address lines or GIO, PFR04
978 ; ||||||||__ A24 / P04_0
979 ; |||||||___ A25 / P04_1
980 ; ||||||____ A26 / P04_2
981 ; |||||_____ A27 / P04_3
982 ; ||||______ A28 / P04_4
983 ; |||_______ A29 / P04_5
984 ; ||________ A30 / P04_6
985 ; |_________ A31 / P04_7
987 #set PFUNC5 B'11111111 ;<<< Address lines or GIO, PFR05
989 ; ||||||||__ A16 / P05_0
990 ; |||||||___ A17 / P05_1
991 ; ||||||____ A18 / P05_2
992 ; |||||_____ A19 / P05_3
993 ; ||||______ A20 / P05_4
994 ; |||_______ A21 / P05_5
995 ; ||________ A22 / P05_6
996 ; |_________ A23 / P05_7
998 #set PFUNC6 B'11111111 ;<<< Address lines or GIO, PFR06
1000 ; ||||||||__ A8 / P06_0
1001 ; |||||||___ A9 / P06_1
1002 ; ||||||____ A10 / P06_2
1003 ; |||||_____ A11 / P06_3
1004 ; ||||______ A12 / P06_4
1005 ; |||_______ A13 / P06_5
1006 ; ||________ A14 / P06_6
1007 ; |_________ A15 / P06_7
1009 #set PFUNC7 B'11111111 ;<<< Address lines or GIO, PFR07
1011 ; ||||||||__ A0 / P07_0
1012 ; |||||||___ A1 / P07_1
1013 ; ||||||____ A2 / P07_2
1014 ; |||||_____ A3 / P07_3
1015 ; ||||______ A4 / P07_4
1016 ; |||_______ A5 / P07_5
1017 ; ||________ A6 / P07_6
1018 ; |_________ A7 / P07_7
1020 ; Select if the ports are set to
1021 ; 1 : External bus mode, I/O for address lines or
1022 ; 0 : General I/O port (GIO)
1024 ; Note: Not all address-lines are supported by the different devices. Please check the
1027 ;=========================================================================================
1028 ; 4.8.12 Select External bus mode (Control signals) (only EXTBUS == ON)
1029 ;=========================================================================================
1031 #set PFUNC8 B'11111111 ;<<< Control signals or GIO, PFR08
1033 ; ||||||||__ WRX0 / P08_0
1034 ; |||||||___ WRX1 / P08_1
1035 ; ||||||____ WRX2 / P08_2
1036 ; |||||_____ WRX3 / P08_3
1037 ; ||||______ RDX / P08_4
1038 ; |||_______ BGRNTX / P08_5
1039 ; ||________ BRQ / P08_6
1040 ; |_________ RDY / P08_7
1042 #set PFUNC9 B'11111111 ;<<< Control signals or GIO, PFR09
1044 ; ||||||||__ CSX0 / P09_0
1045 ; |||||||___ CSX1 / P09_1
1046 ; ||||||____ CSX2 / P09_2
1047 ; |||||_____ CSX3 / P09_3
1048 ; ||||______ CSX4 / P09_4
1049 ; |||_______ CSX5 / P09_5
1050 ; ||________ CSX6 / P09_6
1051 ; |_________ CSX7 / P09_7
1053 #set PFUNC10 B'01011111 ;<<< Control signals or GIO, PFR10
1055 ; ||||||||__ SYSCLK or !SYSCLK / P10_0
1056 ; |||||||___ ASX / P10_1
1057 ; ||||||____ BAAX / P10_2
1058 ; |||||_____ WEX / P10_3
1059 ; ||||______ MCLKO or !MCLKO / P10_4
1060 ; |||_______ MCLKI or !MCLKI/ P10_5
1061 ; ||________ MCLKE / P10_6
1064 #set EPFUNC10 B'00000000 ;<<< Control signals or GIO, EPFR10
1066 ; ||||||||__ 0:SYSCLK / 1:!SYSCLK
1070 ; ||||______ 0:MCLKO / 1:!MCLKO
1071 ; |||_______ 0:MCLKI / 1:!MCLKI
1072 ; ||________ 0:MCLKI / 1:!MCLKI
1076 ; Select if the ports are set to
1077 ; 1 : External bus mode, I/O for control lines or
1078 ; 0 : General I/O port (GIO)
1080 ; Note: Not all control-lines are supported by the different devices. Please check the
1083 ;=========================================================================================
1084 ; 5 Definition of Configurations
1085 ;=========================================================================================
1087 #set NOCLOCK 0 ; do not touch CKSCR register
1088 #set MAINCLOCK 1 ; select main clock
1089 ; ; MB91461R : 1/4 of oscillation input
1090 ; ; Others: 1/2 of oscillation input
1091 #set MAINPLLCLOCK 2 ; select main clock with PLL
1092 #set SUBCLOCK 3 ; select subclock (if available)
1094 #set PSCLOCK_CLKB 0x00 ; select core clock (initial)
1095 #set PSCLOCK_PLL 0x10 ; select PLL output (x)
1096 #set PSCLOCK_MAIN 0x30 ; select Main Oscillation
1098 ;=========================================================================================
1099 ; 5.1 CLOCKSPEED == CLOCK_USER <<<
1100 ;=========================================================================================
1101 ; Must be configured only in the case of CLOCKSPEED is set to CLOCK_USER. Please see the
1102 ; corresponding application note.
1104 #if (CLOCKSPEED == CLOCK_USER )
1105 #set CLOCKSOURCE MAINPLLCLOCK ; <<< Clocksource
1106 #set ENABLE_SUBCLOCK OFF ; <<< Subclock: ON/OFF
1107 #set PLLSPEED 0x010F ; <<< 0x48Ch, 0x48Dh: PLLDIVM/N ; 64 MHz
1108 #set DIV_G 0x0F ; <<< 0x48Eh: PLLDIVG;
1109 #set MUL_G 0x0F ; <<< 0x48Fh: PLLMULG;
1111 #set CPUCLOCK 0x00 ; <<< 0x486h: DIV0R_B; => /1 ; 64 MHz
1112 #set PERCLOCK 0x03 ; <<< 0x486h: DIV0R_P; => /4 ; 16 MHz
1113 #set EXTBUSCLOCK 0x01 ; <<< 0x487h: DIV1R_T; => /2 ; 32 MHz
1115 #set PSCLOCKSOURCE PSCLOCK_PLL ; <<< 0x4C0h: CANPRE; => PLLx;128 MHz
1116 #set PSDVC 0x07 ; <<< 0x4C0h: CANPRE_DVC;=> /8 ; 16 MHz
1117 #set CANCLOCK 0x00 ; <<< 0x4C1h: CANCKD;
1119 #set REGULATORSEL 0x06 ; <<< 0x4CEh: REGSEL;
1120 #set REGULATORCTRL 0x00 ; <<< 0x4CFh: REGCTR;
1122 #set FLASHCONTROL 0x032 ; <<< 0x7002h: FCHCR;
1123 #set FLASHREADT 0xC413 ; <<< 0x7004h: FMWT;
1124 #set FLASHMWT2 0x10 ; <<< 0x7006h: FMWT2;
1127 ;=========================================================================================
1128 ; 5.2 CLOCKSPEED == NO_CLOCK
1129 ;=========================================================================================
1131 #if (CLOCKSPEED == NO_CLOCK )
1132 #set CLOCKSOURCE NOCLOCK
1135 ;=========================================================================================
1136 ; 5.2 CLOCKSPEED == SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ
1137 ;=========================================================================================
1139 #if (CLOCKSPEED == SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ )
1141 ; Start restriction; Maximum frequency
1142 #if (DEVICE == MB91463N) || (DEVICE == MB91461R)
1143 #error: Frequency is not supported by this device.
1147 #set CLOCKSOURCE SUBCLOCK ; Clocksource
1148 #set ENABLE_SUBCLOCK ON ; Subclock: ON/OFF
1149 #set PLLSPEED 0x010F ; 0x48Ch, 0x48Dh: PLLDIVM/N ; n. a.
1150 #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
1151 #set MUL_G 0x0F ; 0x48Fh: PLLMULG;
1153 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 32 KHz
1154 #set PERCLOCK 0x00 ; 0x486h: DIV0R_P; => /1 ; 32 KHz
1155 #set EXTBUSCLOCK 0x00 ; 0x487h: DIV1R_T; => /1 ; 32 KHz
1157 #set PSCLOCKSOURCE PSCLOCK_MAIN ; 0x4C0h: CANPRE; => MAIN ; 4 MHz
1158 #set PSDVC 0x01 ; 0x4C0h: CANPRE_DVC; => /2 ; 2 MHz
1159 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
1161 #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
1162 #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
1164 #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
1165 #set FLASHREADT 0xC100 ; 0x7004h: FMWT;
1166 #set FLASHMWT2 0x00 ; 0x7006h: FMWT2;
1169 ;=========================================================================================
1170 ; 5.3 CLOCKSPEED == MAIN__4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ
1171 ;=========================================================================================
1173 #if (CLOCKSPEED == MAIN_4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ )
1175 ; Start restriction; Maximum frequency
1176 #if (DEVICE == MB91461R)
1177 #error: Frequency is not supported by this device.
1181 #set CLOCKSOURCE MAINCLOCK ; Clocksource
1182 #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
1183 #set PLLSPEED 0x010F ; 0x48Ch, 0x48Dh: PLLDIVM/N ; n. a.
1184 #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
1185 #set MUL_G 0x0F ; 0x48Fh: PLLMULG;
1187 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 2 MHz
1188 #set PERCLOCK 0x01 ; 0x486h: DIV0R_P; => /2 ; 1 MHz
1189 #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 1 MHz
1191 #set PSCLOCKSOURCE PSCLOCK_MAIN ; 0x4C0h: CANPRE; => PLLx ; 4 MHz
1192 #set PSDVC 0x01 ; 0x4C0h: CANPRE_DVC; => /2 ; 2 MHz
1193 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
1195 #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
1196 #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
1198 #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
1199 #set FLASHREADT 0xC100 ; 0x7004h: FMWT;
1200 #set FLASHMWT2 0x00 ; 0x7006h: FMWT2;
1203 ;=========================================================================================
1204 ; 5.4 CLOCKSPEED == PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ
1205 ;=========================================================================================
1207 #if (CLOCKSPEED == PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ )
1209 ; Start restriction; Maximum frequency
1210 #if (DEVICE == MB91461R)
1211 #error: Frequency is not supported by this device.
1215 #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
1216 #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
1217 #set PLLSPEED 0x010B ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 48 MHz
1218 #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
1219 #set MUL_G 0x0B ; 0x48Fh: PLLMULG;
1221 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 48 MHz
1222 #set PERCLOCK 0x02 ; 0x486h: DIV0R_P; => /3 ; 16 MHz
1223 #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 24 MHz
1225 #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 96 MHz
1226 #set PSDVC 0x05 ; 0x4C0h: CANPRE_DVC; => /6 ; 16 MHz
1227 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
1229 #if (DEVICE == MB91469G)
1230 #set REGULATORSEL 0x36 ; 0x4CEh: REGSEL;
1232 #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
1234 #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
1236 #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
1237 #set FLASHREADT 0xC201 ; 0x7004h: FMWT;
1238 #set FLASHMWT2 0x00 ; 0x7006h: FMWT2;
1241 ;=========================================================================================
1242 ; 5.5 CLOCKSPEED == PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ
1243 ;=========================================================================================
1245 #if (CLOCKSPEED == PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ )
1247 ; Start restriction; Maximum frequency
1248 #if (DEVICE == MB91461R)
1249 #error: Frequency is not supported by this device.
1253 #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
1254 #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
1255 #set PLLSPEED 0x010F ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 64 MHz
1256 #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
1257 #set MUL_G 0x0F ; 0x48Fh: PLLMULG;
1259 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 64 MHz
1260 #set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 16 MHz
1261 #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 32 MHz
1263 #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 128 MHz
1264 #set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 16 MHz
1265 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
1267 #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
1268 #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
1270 #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
1271 #set FLASHREADT 0xC413 ; 0x7004h: FMWT;
1272 #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;
1275 ;=========================================================================================
1276 ; 5.6 CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ
1277 ;=========================================================================================
1279 #if (CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ )
1281 ; Start restriction; Maximum frequency
1282 #if (DEVICE == MB91461R)
1283 #error: Frequency is not supported by this device.
1287 #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
1288 #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
1289 #set PLLSPEED 0x0113 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 80 MHz
1290 #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
1291 #set MUL_G 0x13 ; 0x48Fh: PLLMULG;
1293 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 80 MHz
1294 #set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 20 MHz
1295 #set EXTBUSCLOCK 0x02 ; 0x487h: DIV1R_T; => /3 ; 27 MHz
1297 #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 160 MHz
1298 #set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 8 MHz
1299 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
1301 #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
1302 #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
1304 #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
1305 #set FLASHREADT 0xC413 ; 0x7004h: FMWT;
1306 #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;
1309 ;=========================================================================================
1310 ; 5.7 CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ
1311 ;=========================================================================================
1313 #if (CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ )
1315 ; Start restriction; Maximum frequency
1316 #if (DEVICE == MB91461R)
1317 #error: Frequency is not supported by this device.
1321 #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
1322 #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
1323 #set PLLSPEED 0x0113 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 80 MHz
1324 #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
1325 #set MUL_G 0x13 ; 0x48Fh: PLLMULG;
1327 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 80 MHz
1328 #set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 20 MHz
1329 #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 40 MHz
1331 #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 160 MHz
1332 #set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 8 MHz
1333 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
1335 #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
1336 #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
1338 #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
1339 #set FLASHREADT 0xC413 ; 0x7004h: FMWT;
1340 #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;
1343 ;=========================================================================================
1344 ; 5.8 CLOCKSPEED == PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ
1345 ;=========================================================================================
1347 #if (CLOCKSPEED == PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ )
1349 ; Start restriction; Maximum frequency
1350 #if (DEVICE == MB91464A) || (DEVICE == MB91465K) || (DEVICE == MB91463N) ||\
1351 (DEVICE == MB91461R) || (DEVICE == MB91467R)
1352 #error: Frequency is not supported by this device.
1356 #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
1357 #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
1358 #set PLLSPEED 0x0117 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 96 MHz
1359 #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
1360 #set MUL_G 0x17 ; 0x48Fh: PLLMULG;
1362 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 64 MHz
1363 #set PERCLOCK 0x05 ; 0x486h: DIV0R_P; => /6 ; 16 MHz
1364 #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 32 MHz
1366 #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 192 MHz
1367 #set PSDVC 0x0B ; 0x4C0h: CANPRE_DVC; => /12 ; 16 MHz
1368 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
1370 #if (DEVICE == MB91469G)
1371 #set REGULATORSEL 0x36 ; 0x4CEh: REGSEL;
1373 #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
1375 #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
1377 #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
1378 #set FLASHREADT 0xC413 ; 0x7004h: FMWT;
1379 #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;
1382 ;=========================================================================================
1383 ; 5.9 CLOCKSPEED == PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ
1384 ;=========================================================================================
1386 #if (CLOCKSPEED == PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ )
1388 ; Start restriction; Maximum frequency
1389 #if (DEVICE == MB91464A) || (DEVICE == MB91465K) || (DEVICE == MB91463N) ||\
1390 (DEVICE == MB91461R) || (DEVICE == MB91467R) || (DEVICE == MB91467D)
1391 #error: Frequency is not supported by this device.
1395 #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
1396 #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
1397 #set PLLSPEED 0x0118 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 100 MHz
1398 #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
1399 #set MUL_G 0x17 ; 0x48Fh: PLLMULG;
1401 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 100 MHz
1402 #set PERCLOCK 0x04 ; 0x486h: DIV0R_P; => /5 ; 20 MHz
1403 #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 50 MHz
1405 #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 200 MHz
1406 #set PSDVC 0x09 ; 0x4C0h: CANPRE_DVC; => /10 ; 20 MHz
1407 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
1409 #if (DEVICE == MB91469G)
1410 #set REGULATORSEL 0x36 ; 0x4CEh: REGSEL;
1412 #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
1414 #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
1416 #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
1417 #set FLASHREADT 0xC413 ; 0x7004h: FMWT;
1418 #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;
1421 ;=========================================================================================
1422 ; 5.10 CLOCKSPEED == PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ
1423 ;=========================================================================================
1425 #if (CLOCKSPEED == PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ )
1427 ; Start restriction; Maximum frequency
1428 #if (DEVICE == MB91464A) || (DEVICE == MB91467B) || (DEVICE == MB91467C) ||\
1429 (DEVICE == MB91467D) || (DEVICE == MB91469G) || (DEVICE == MB91465K) ||\
1430 (DEVICE == MB91463N) || (DEVICE == MB91467R) || (DEVICE == MB91465X)
1431 #error: Frequency is not supported by this device.
1435 #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
1436 #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
1437 #set PLLSPEED 0x0105 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 60 MHz
1438 #set DIV_G 0x0B ; 0x48Eh: PLLDIVG;
1439 #set MUL_G 0x1F ; 0x48Fh: PLLMULG;
1441 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 60 MHz
1442 #set PERCLOCK 0x02 ; 0x486h: DIV0R_P; => /3 ; 20 MHz
1443 #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 30 MHz
1445 #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 120 MHz
1446 #set PSDVC 0x05 ; 0x4C0h: CANPRE_DVC; => /6 ; 20 MHz
1447 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
1454 ;=========================================================================================
1455 ; 5.11 CLOCKSPEED == PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ
1456 ;=========================================================================================
1458 #if (CLOCKSPEED == PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ )
1460 ; Start restriction; Maximum frequency
1461 #if (DEVICE == MB91464A) || (DEVICE == MB91467B) || (DEVICE == MB91467C) ||\
1462 (DEVICE == MB91467D) || (DEVICE == MB91469G) || (DEVICE == MB91465K) ||\
1463 (DEVICE == MB91463N) || (DEVICE == MB91467R) || (DEVICE == MB91465X)
1464 #error: Frequency is not supported by this device.
1468 #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
1469 #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
1470 #set PLLSPEED 0x0102 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 60 MHz
1471 #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
1472 #set MUL_G 0x1F ; 0x48Fh: PLLMULG;
1474 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 60 MHz
1475 #set PERCLOCK 0x02 ; 0x486h: DIV0R_P; => /3 ; 20 MHz
1476 #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 30 MHz
1478 #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 120 MHz
1479 #set PSDVC 0x05 ; 0x4C0h: CANPRE_DVC; => /6 ; 20 MHz
1480 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
1487 ;=========================================================================================
1488 ; 6 Section and Data Declaration
1489 ;=========================================================================================
1499 .import __stream_init
1504 .import ___call_dtors
1507 ;=========================================================================================
1508 ; 6.1 Define Stack Size
1509 ;=========================================================================================
1510 .SECTION SSTACK, STACK, ALIGN=4
1511 #if STACK_RESERVE == ON
1512 .EXPORT __systemstack, __systemstack_top
1514 .RES.B STACK_SYS_SIZE
1518 .SECTION USTACK, STACK, ALIGN=4
1519 #if STACK_RESERVE == ON
1520 .EXPORT __userstack, __userstack_top
1522 .RES.B STACK_USR_SIZE
1526 ;=========================================================================================
1527 ; 6.2 Define Sections
1528 ;=========================================================================================
1529 .section DATA, data, align=4
1530 .section INIT, data, align=4
1531 .section IRAM, code, align=4
1532 .section CONST, const, align=4
1533 .section INTVECT, const, align=4
1540 #if (DEVICE != MB91461R)
1541 #if (DEVICE == MB91469G)
1542 .section SECURITY_VECTORS, code, locate = 0x248000
1544 .section SECURITY_VECTORS, code, locate = 0x148000
1547 #if (BOOT_FLASH_SEC == OFF)
1558 .section EXT_CTOR_DTOR, const, align=4 ; C++ constructors
1561 ;-----------------------------------------------------------------------------------------
1562 ; MACRO Clear RC Watchdog
1563 ;-----------------------------------------------------------------------------------------
1564 #macro ClearRCwatchdog
1565 LDI #0x4C7,R7 ; clear RC watchdog
1568 ;-----------------------------------------------------------------------------------------
1570 ;-----------------------------------------------------------------------------------------
1571 #macro wait_loop loop_number
1573 LDI #loop_number, R0
1578 .section CODE, code, align=4
1579 .section CODE_START, code, align=4
1580 #pragma section CODE=IRAM,attr=CODE
1583 ;=========================================================================================
1585 ;=========================================================================================
1586 __start: ; start point
1590 ANDCCR #0xEF ; disable interrupts
1591 STILM #LOW_PRIOR ; set interrupt level to low prior
1592 ClearRCwatchdog ; clear harware watchdog
1594 ;=========================================================================================
1595 ; 7.1 Initialise Stack Pointer and Table Base Register
1596 ;=========================================================================================
1597 #if STACKUSE == SYSSTACK
1599 LDI #__userstack_top, SP ; initialize SP
1601 LDI #__systemstack_top, SP ; initialize SP
1604 #if STACKUSE == USRSTACK
1606 LDI #__systemstack_top, SP ; initialize SP
1608 LDI #__userstack_top, SP ; initialize SP
1611 LDI #INTVECT, R0 ; set Table Base
1615 #if (CLOCKSOURCE != NOCLOCK)
1616 ;=========================================================================================
1617 ; 7.2 Check for CSV reset and set CSV
1618 ;=========================================================================================
1619 ; Start restriction; No clock supervisor (CSV)
1620 #if (DEVICE != MB91461R) && (DEVICE != MB91467R) && (DEVICE != MB91463N)
1622 LDI:20 #0x04AD, R0 ; CSVCR
1623 BORL #0x8, @R0 ; Enable Main Osc CSV
1624 BTSTH #0x4, @R0 ; Check for Main Osc missing
1625 BEQ NoMAINCSVreset ; Main osc available -> branch
1627 BANDL #0x7, @R0 ; Disable Main Osc CSV
1629 LDI #noClockStartup, R0 ; Main Clock missing -> no
1630 JMP @R0 ; clock startup
1635 BORL #0x4, @R0 ; Enable Sub Osc CSV
1636 BTSTH #0x2, @R0 ; Check for Sub Osc missing
1637 BEQ NoSUBCSVreset ; Sub osc available -> branch
1639 BANDL #0xB, @R0 ; Disable Sub Osc SCSV
1640 #if (CLOCKSOURCE == SUBCLOCK)
1641 LDI #noClockStartup, R0 ; Sub Clock missing -> no
1642 JMP @R0 ; clock startup
1646 ;=========================================================================================
1647 ; 7.3 Check Clock Condition
1648 ;=========================================================================================
1649 LDI #0x484, R0 ; Check for Default Values
1654 ;=========================================================================================
1655 ; 7.4 Restore Default Settings after Reset
1656 ;=========================================================================================
1657 ;=========================================================================================
1658 ; 7.4.1 Disable Clock Modulator
1659 ;=========================================================================================
1660 LDI #0x04BB, R0 ; Clock Modulator Control Reg
1661 BANDL #0xD, @R0 ; Disable Frequency modulation
1663 BTSTL #8, @R0 ; Wait until Frequency modulation
1664 BNE FMODwait ; is disabled
1666 BANDL #0xE, @R0 ; Power down clock modulator
1668 ;=========================================================================================
1669 ; 7.4.2 Check if running on Sub Clock, change to Main Clock
1670 ;=========================================================================================
1671 LDI:20 #0x0484,R12 ; Check if running on sub clock
1678 LDI:20 #0x04CC,R12 ; Check if Main Clock is stopped
1682 BANDL #0xE, @R12 ; Start Main Oscillation
1684 LDI #0x4C8, R0 ; Main Stabilisation Wait Time
1685 LDI #0x04, R1 ; 32.7 ms
1689 mainStabTime: ; Wait for stabilisation time
1690 ClearRCwatchdog ; clear harware watchdog
1697 LDI:20 #0x0484, R12 ; disable sub clock as source
1698 BANDL #0xD, @R12 ; Clock source = 0x01 (Main/2)
1701 ;=========================================================================================
1702 ; 7.4.3 Disable Sub Clock
1703 ;=========================================================================================
1704 #if ENABLE_SUBCLOCK != ON
1705 LDI #0x0484, R0 ; Clock source control reg CLKR
1706 BANDL #0x7, @R0 ; Disable PLL
1709 ;=========================================================================================
1710 ; 7.4.4 Check if running on PLL, Gear Down PLL
1711 ;=========================================================================================
1712 LDI:20 #0x0484,R12 ; Check if running on PLL
1719 LDI:20 #0x0490, R11 ; clear flags
1723 STB R1, @R11 ; Set Flag for Simulator; no Effekt on
1726 BANDL #0xC, @R12 ; disable PLL as clock source
1727 ; Clock Source = 0x00 (Main/2)
1729 LDI:20 #0x048E,R12 ; check if DivG != 0
1736 ClearRCwatchdog ; clear harware watchdog
1737 BTSTL #4, @R11 ; Gear Down
1740 LDI #0x00,R1 ; Clear Flags
1744 ;=========================================================================================
1746 ;=========================================================================================
1747 LDI #0x0484, R0 ; Clock source control reg CLKR
1748 BANDL #0xB, @R0 ; Disable PLL
1750 ;=========================================================================================
1751 ; 7.4.6 Set to Main Clock
1752 ;=========================================================================================
1753 LDI:20 #0x0484,R12 ; Check if running on PLL
1754 BANDL #0xC, @R12 ; disable PLL as clock source
1755 ; Clock Source = 0x00 (Main/2)
1758 ;=========================================================================================
1759 ; 7.5 Set Memory Controller
1760 ;=========================================================================================
1761 ; Start restriction; No embedded flash
1762 #if DEVICE != MB91461R
1764 LDI #0x7002, R1 ; FLASH Controller Reg.
1765 LDI #FLASHCONTROL, R2 ; Flash Controller Settings
1766 STH R2, @R1 ; set register
1767 LDI #0x7004, R1 ; FLASH Memory Wait Timing Reg.
1768 LDI #FLASHREADT, R2 ; wait settings
1769 STH R2, @R1 ; set register
1770 LDI #0x7006, R1 ; FLASH Memory Wait Timing Reg.
1771 LDI #FLASHMWT2, R2 ; wait settings
1772 STB R2, @R1 ; set register
1776 ;=========================================================================================
1778 ;=========================================================================================
1779 ;=========================================================================================
1780 ; 7.6.1 Set Voltage Regulator Settings
1781 ;=========================================================================================
1782 ; Start restriction; No regulator settings
1783 #if DEVICE != MB91461R
1785 LDI #0x04CF, R0 ; REGCTR
1786 LDI #REGULATORCTRL, R1
1789 LDI #0x04CE, R0 ; REGSEL
1790 LDI #REGULATORSEL, R1
1794 ;=========================================================================================
1795 ; 7.6.2 Power on Clock Modulator - Clock Modulator Part I
1796 ;=========================================================================================
1798 LDI #0x04BB, R0 ; Clock Modulator Control Reg
1799 LDI #0x11, R1 ; Load value to Power on CM
1800 ORB R1, @R0 ; Power on clock modulaor
1803 ;=========================================================================================
1804 ; 7.6.3 Set CLKR Register w/o Clock Mode
1805 ;=========================================================================================
1806 ; Set Clock source (Base Clock) for the three clock tree selections
1807 ; This select Base clock is used to select afterwards the 3
1808 ; Clocks for the diffenrent internal trees.
1809 ; When PLL is used, first pll multiplication ratio is set and PLL is
1810 ; enabled. After waiting the PLL stabilisation time via timebase
1811 ; timer, PLL clock is selected as clock source.
1812 LDI #0x048C, R0 ; PLL Cntl Reg. PLLDIVM/N
1813 LDI:20 #PLLSPEED, R1
1816 LDI #0x048E, R0 ; PLL Cntl Reg. PLLDIVG
1820 LDI #0x048F, R0 ; PLL Cntl Reg. PLLMULG
1824 ;=========================================================================================
1826 ;=========================================================================================
1827 #if ( ( CLOCKSOURCE == MAINPLLCLOCK ) || ( PSCLOCKSOURCE == PSCLOCK_PLL ) )
1828 LDI #0x0484, R0 ; Clock source control reg CLKR
1829 LDI #0x04, R1 ; Use PLL x1, enable PLL
1830 ORB R1, @R0 ; store data to CLKR register
1834 #if ENABLE_SUBCLOCK == ON
1835 LDI #0x0484, R0 ; Clock source control reg CLKR
1836 LDI #0x08, R1 ; enable subclock operation
1837 ORB R1, @R0 ; store data to CLKR register
1838 LDI #0x4CA, R0 ; Sub Clock oszilation
1839 LDI #0x00, R1 ; stabilitsation time = 32 ms
1844 ;=========================================================================================
1845 ; 7.6.5 Wait for PLL oscillation stabilisation
1846 ;=========================================================================================
1847 #if ((CLOCKSOURCE==MAINPLLCLOCK)||(PSCLOCKSOURCE==PSCLOCK_PLL))
1848 LDI #0x0482, R12 ; TimeBaseTimer TBCR
1849 LDI #0x00, R1 ; set 1024 us @ 2 MHz
1852 BANDH #7, @R12 ; clear interrupt flag
1854 LDI #0x0483, R0 ; clearTimeBaseTimer CTBR
1860 BANDH #7, @R12 ; clear interrupt flag
1861 BORH #8, @R12 ; set interrupt flag for simulator
1864 ClearRCwatchdog ; clear harware watchdog
1869 ;=========================================================================================
1871 ;=========================================================================================
1872 ;=========================================================================================
1873 ; 7.6.6.1 Set CPU and peripheral clock
1874 ;=========================================================================================
1875 ; CPU and peripheral clock are set in one register
1876 LDI #0x0486, R2 ; Set DIVR0 (CPU-clock (CLKB)
1877 LDI #((CPUCLOCK << 4) + PERCLOCK), R3 ; Load CPU clock setting
1879 ;=========================================================================================
1880 ; 7.6.6.2 Set External Bus interface clock
1881 ;=========================================================================================
1882 ; set External Bus clock
1883 ; Be aware to do smooth clock setting, to avoid wrong clock setting
1884 ; Take care, always write 0 to the lower 4 bits of DIVR1 register
1885 LDI #0x0487, R2 ; Set DIVR1
1886 LDI #(EXTBUSCLOCK << 4), R3 ; Load Peripheral clock setting
1889 ;=========================================================================================
1890 ; 7.6.6.3 Set CAN clock prescaler
1891 ;=========================================================================================
1892 ; Set CAN Prescaler, only clock relevant parameter
1893 LDI #0x04C0, R0 ; Set CAN ClockParameter Register
1894 LDI #(PSCLOCKSOURCE + PSDVC), R1 ; Load Divider
1895 STB R1, @R0 ; Set Divider
1897 LDI #0x04c1, R0 ; Set CAN Clock enable Register
1898 LDI #CANCLOCK, R1 ; Load CANCLOCK
1899 STB R1, @R0 ; set CANCLOCK
1901 ;=========================================================================================
1902 ; 7.6.6.4 Switch Main Clock Mode
1903 ;=========================================================================================
1904 #if CLOCKSOURCE == MAINCLOCK
1906 ;=========================================================================================
1907 ; 7.6.6.5 Switch Subclock Mode
1908 ;=========================================================================================
1909 #elif ( (CLOCKSOURCE == SUBCLOCK) )
1910 #if ENABLE_SUBCLOCK == ON
1913 ClearRCwatchdog ; clear harware watchdog
1914 BTSTH #8, @R12 ; wait until sub clock stabilisation
1915 BEQ subStabTime ; time is over
1919 LDI #0x0484, R0 ; Clock source control reg CLKR
1920 LDI #0x01, R1 ; load value to select main clock
1921 ORB R1, @R0 ; enable main clock (1/2 external)
1922 LDI #0x03, R1 ; load value to select subclock
1923 ORB R1, @R0 ; enable subclock as clock source
1925 #error: Wrong setting! The clock source is subclock, but the subclock is disabled.
1928 ;=========================================================================================
1929 ; 7.6.7 Switch to PLL Mode
1930 ;=========================================================================================
1931 #elif ( (CLOCKSOURCE == MAINPLLCLOCK) )
1934 LDI #0x0490, R0 ; PLL Ctrl Register
1936 STB R1, @R0 ; Clear Flag
1938 STB R1, @R0 ; Set Flag for Simulator; no Effekt on
1941 LDI #0x0484, R3 ; Clock source control reg CLKR
1942 BORL #0x2, @R3 ; enable PLL as clock source
1946 ClearRCwatchdog ; clear harware watchdog
1947 LDUB @R0, R2 ; LOAD PLLCTR to R2
1948 AND R1, R2 ; GRUP, counter reach 0
1952 STB R1, @R0 ; Clear Gear-Up Flag
1957 ;=========================================================================================
1958 ; 7.6.8 Enable Frequncy Modulation - Clock Modulator Part II
1959 ;=========================================================================================
1960 #if CLOMO == ON ; Only applicable if Modulator is on
1961 LDI #0x04B8, R0 ; Clock Modulation Parameter Reg
1962 LDI #CMPR, R1 ; Load CMP value
1963 STH R1, @R0 ; Store CMP value in CMPR
1965 LDI #0x04BB, R0 ; Clock Modulator Control Reg
1966 LDI #0x13, R1 ; Load value to FM on CM
1973 ;=========================================================================================
1974 ; 7.7 Set BusInterface
1975 ;=========================================================================================
1976 ; Start restriction; No ext. bus interface
1977 #if (DEVICE != MB91464A) && (DEVICE != MB91467C) && (DEVICE != MB91465K) && \
1978 (DEVICE != MB91463N) && (DEVICE != MB91465X)
1981 ;=========================================================================================
1982 ; 7.7.1 Disable all CS
1983 ;=========================================================================================
1984 ; Start restriction; Flashless device
1985 #if(DEVICE != MB91461R)
1987 LDI #0x0680, R3 ; chip select enable register CSER
1988 LDI #(0x00), R2 ; load disable settings
1990 ANDB R2, @R3 ; set register
1993 ;=========================================================================================
1994 ; 7.7.2 Clear TCR Register
1995 ;=========================================================================================
1996 LDI #0x0683, R1 ; Pin/Timing Control Register TCR
1997 BORH #0x6,@R1 ; load timing settings
1999 ;=========================================================================================
2001 ;=========================================================================================
2003 LDI #0x0640, R1 ; area select reg ASR0, ACR0
2004 LDI #(AREASEL0<<16)+CONFIGCS0, R0 ; load settings
2005 ST R0, @R1 ; set registers
2007 LDI #0x660, R1 ; area wait register awr0
2008 LDI #WAITREG0, R2 ; wait settings
2009 STH R2, @R1 ; set register
2012 ;=========================================================================================
2014 ;=========================================================================================
2016 LDI #0x0644, R1 ; area select reg ASR1, ACR1
2017 LDI #(AREASEL1<<16)+CONFIGCS1, R0 ; load settings
2018 ST R0, @R1 ; set registers
2020 LDI #0x662, R1 ; area wait register awr1
2021 LDI #WAITREG1, R2 ; wait settings
2022 STH R2, @R1 ; set register
2025 ;=========================================================================================
2027 ;=========================================================================================
2029 LDI #0x0648, R1 ; area select reg ASR2, ACR2
2030 LDI #(AREASEL2<<16)+CONFIGCS2, R0 ; load settings
2031 ST R0, @R1 ; set registers
2032 LDI #0x664, R1 ; area wait register awr2
2033 LDI #WAITREG2, R2 ; wait settings
2034 STH R2, @R1 ; set register
2036 ;=========================================================================================
2038 ;=========================================================================================
2040 LDI #0x064C, R1 ; area select reg ASR3, ACR3
2041 LDI #(AREASEL3<<16)+CONFIGCS3, R0 ; load settings
2042 ST R0, @R1 ; set registers
2043 LDI #0x666, R1 ; area wait register awr3
2044 LDI #WAITREG3, R2 ; wait settings
2045 STH R2, @R1 ; set register
2047 ;=========================================================================================
2049 ;=========================================================================================
2051 LDI #0x0650, R1 ; area select reg ASR4, ACR4
2052 LDI #(AREASEL4<<16)+CONFIGCS4, R0 ; load settings
2053 ST R0, @R1 ; set registers
2054 LDI #0x668, R1 ; area wait register awr4
2055 LDI #WAITREG4, R2 ; wait settings
2056 STH R2, @R1 ; set register
2058 ;=========================================================================================
2060 ;=========================================================================================
2062 LDI #0x0654, R1 ; area select reg ASR5, ACR5
2063 LDI #(AREASEL5<<16)+CONFIGCS5, R0 ; load settings
2064 ST R0, @R1 ; set registers
2065 LDI #0x66A, R1 ; area wait register awr5
2066 LDI #WAITREG5, R2 ; wait settings
2067 STH R2, @R1 ; set register
2069 ;=========================================================================================
2071 ;=========================================================================================
2073 LDI #0x0658, R1 ; area select reg ASR6, ACR6
2074 LDI #(AREASEL6<<16)+CONFIGCS6, R0 ; load settings
2075 ST R0, @R1 ; set registers
2076 LDI #0x66C, R1 ; area wait register awr6
2077 LDI #WAITREG6, R2 ; wait settings
2078 STH R2, @R1 ; set register
2080 ;=========================================================================================
2082 ;=========================================================================================
2084 LDI #0x065C, R1 ; area select reg ASR7, ACR7
2085 LDI #(AREASEL7<<16)+CONFIGCS7, R0 ; load settings
2086 ST R0, @R1 ; set registers
2087 LDI #0x66E, R1 ; area wait register awr7
2088 LDI #WAITREG7, R2 ; wait settings
2089 STH R2, @R1 ; set register
2091 ;=========================================================================================
2092 ; 7.7.11 Set special SDRAM config register
2093 ;=========================================================================================
2095 LDI #0x670, R1 ; SDRAM memory config register
2096 LDI #MEMCON, R2 ; wait settings
2097 STB R2, @R1 ; set register
2100 ;=========================================================================================
2101 ; 7.7.12 set Port Function Register
2102 ;=========================================================================================
2103 ;=========================================================================================
2104 ; 7.7.12.1 set PFR00 Register. External bus mode (D[24-31]) or General purpose port
2105 ;=========================================================================================
2106 LDI #0x0D80, R1 ; Port Function Register 0, (PFR00)
2107 LDI #PFUNC0, R0 ; load port settings
2108 STB R0, @R1 ; set register
2109 ;=========================================================================================
2110 ; 7.7.12.2 set PFR01 Register. External bus mode (D[16-23]) or General purpose port
2111 ;=========================================================================================
2112 LDI #0x0D81, R1 ; Port Function Register 1, (PFR01)
2113 LDI #PFUNC1, R0 ; load port settings
2114 STB R0, @R1 ; set register
2115 ;=========================================================================================
2116 ; 7.7.12.3 set PFR02 Register. External bus mode (D[8-15]) or General purpose port
2117 ;=========================================================================================
2118 LDI #0x0D82, R1 ; Port Function Register 2, (PFR02)
2119 LDI #PFUNC2, R0 ; load port settings
2120 STB R0, @R1 ; set register
2121 ;=========================================================================================
2122 ; 7.7.12.4 set PFR03 Register. External bus mode (D[0-7]) or General purpose port
2123 ;=========================================================================================
2124 LDI #0x0D83, R1 ; Port Function Register 3, (PFR03)
2125 LDI #PFUNC3, R0 ; load port settings
2126 STB R0, @R1 ; set register
2127 ;=========================================================================================
2128 ; 7.7.12.5 set PFR04 Register. External bus mode (Adr[24-31]) or General purpose port
2129 ;=========================================================================================
2130 LDI #0x0D84, R1 ; Port Function Register 4, (PFR04)
2131 LDI #PFUNC4, R0 ; load port settings
2132 STB R0, @R1 ; set register
2133 ;=========================================================================================
2134 ; 7.7.12.6 set PFR05 Register. External bus mode (Adr[16-23]) or General purpose port
2135 ;=========================================================================================
2136 LDI #0x0D85, R1 ; Port Function Register 5, (PFR05)
2137 LDI #PFUNC5, R0 ; load port settings
2138 STB R0, @R1 ; set register
2139 ;=========================================================================================
2140 ; 7.7.12.7 set PFR06 Register. External bus mode (Adr[8-15]) or General purpose port
2141 ;=========================================================================================
2142 LDI #0x0D86, R1 ; Port Function Register 6, (PFR06)
2143 LDI #PFUNC6, R0 ; load port settings
2144 STB R0, @R1 ; set register
2145 ;=========================================================================================
2146 ; 7.7.12.8 set PFR07 Register. External bus mode (Adr[0-7]) or General purpose port
2147 ;=========================================================================================
2148 LDI #0x0D87, R1 ; Port Function Register 7, (PFR07)
2149 LDI #PFUNC7, R0 ; load port settings
2150 STB R0, @R1 ; set register
2151 ;=========================================================================================
2152 ; 7.7.12.9 set PFR08 Register. External bus mode (Control Signals) or GIO port
2153 ;=========================================================================================
2154 LDI #0x0D88, R1 ; Port Function Register 8, (PFR08)
2155 LDI #PFUNC8, R0 ; load port settings
2156 STB R0, @R1 ; set register
2157 ;=========================================================================================
2158 ; 7.7.12.10 set PFR09 Register. External bus mode (Control Signals) or GIO port
2159 ;=========================================================================================
2160 LDI #0x0D89, R1 ; Port Function Register 9, (PFR09)
2161 LDI #PFUNC9, R0 ; load port settings
2162 STB R0, @R1 ; set register
2163 ;=========================================================================================
2164 ; 7.7.12.11 set PFR10 Register. External bus mode (Control Signals) or GIO port
2165 ;=========================================================================================
2166 LDI #0x0D8A, R1 ; Port Function Register 10, (PFR10)
2167 LDI #PFUNC10, R0 ; load port settings
2168 STB R0, @R1 ; set register
2169 ;=========================================================================================
2170 ; 7.7.12.12 set EPFR10 Register. External bus mode (Control Signals) or GIO port
2171 ;=========================================================================================
2172 LDI #0x0DCA, R1 ; Extended PFR 10, (EPFR10)
2173 LDI #EPFUNC10, R0 ; load port settings
2174 STB R0, @R1 ; set register
2175 ;=========================================================================================
2176 ; 7.7.13 Set TCR Register
2177 ;=========================================================================================
2178 LDI #0x0683, R1 ; Pin/Timing Control Register TCR
2179 LDI #TIMECONTR, R0 ; load timing settings
2180 STB R0, @R1 ; set register
2181 ;=========================================================================================
2182 ; 7.7.14 Enable CACHE for selected CS
2183 ;=========================================================================================
2184 LDI #0x0681, R3 ; chip select enable register CSER
2187 ;=========================================================================================
2188 ; 7.7.15 set SDRAM Referesh Control Register
2189 ;=========================================================================================
2191 LDI #0x0684, R1 ; Refresh Control Register RCR
2192 LDI #REFRESH, R0 ; load refresh settings
2193 STH R0, @R1 ; set register
2195 OR R2, R0 ; Set PON bit to 1
2196 STH R0, @R1 ; set register
2198 ;=========================================================================================
2199 ; 7.7.16 Enable used CS
2200 ;=========================================================================================
2201 LDI #0x0680, R3 ; chip select enable register CSER
2203 ; Start restriction; Flashless device
2204 #if (DEVICE == MB91461R)
2206 emu_sram_cs_mb91461r:
2207 ANDB R2, @R3 ; set register
2211 ;=========================================================================================
2212 ; 7.7.17 I-cache on/off
2213 ;=========================================================================================
2214 ; Start restriction; No cache
2215 #if (DEVICE == MB91461R) || (DEVICE == MB91469G) || (DEVICE == others)
2218 #if CACHE_SIZE == C1024
2219 LDI #0x03C7, R1 ; Cache size register ISIZE
2222 LDI #0x03E7, R1 ; Cache control reg ICHCR
2223 LDI #0x07, R2 ; Release entry locks, flush and enable
2225 #elif CACHE_SIZE == C2048
2226 LDI #0x03C7, R1 ; Cache size register ISIZE
2229 LDI #0x03E7, R1 ; Cache control reg ICHCR
2230 LDI #0x07, R2 ; Release entry locks, flush and enable
2232 #elif CACHE_SIZE == C4096
2233 LDI #0x03C7, R1 ; Cache size register ISIZE
2236 LDI #0x03E7, R1 ; Cache control reg ICHCR
2237 LDI #0x07, R2 ; Release entry locks, flush and enable
2240 #error: Wrong Cache size selected!
2243 LDI #0x03E7, R1 ; Cache control reg ICHCR
2244 LDI #0x06, R2 ; Release entry locks, flush and disable
2248 #elif (EXTBUS == OFF)
2249 ;=========================================================================================
2250 ; 7.7.18 set Port Function Register to general as I/O-Port
2251 ;=========================================================================================
2252 ;=========================================================================================
2253 ; 7.7.18.1 set PFR00 Register. External bus mode as General purpose port
2254 ;=========================================================================================
2255 LDI #0x0D80, R1 ; Port Function Register 0, (PFR00)
2256 LDI #0x00, R0 ; load port settings
2257 STB R0, @R1 ; set register
2258 ;=========================================================================================
2259 ; 7.7.18.2 set PFR01 Register. External bus mode as General purpose port
2260 ;=========================================================================================
2261 LDI #0x0D81, R1 ; Port Function Register 1, (PFR01)
2262 LDI #0x00, R0 ; load port settings
2263 STB R0, @R1 ; set register
2264 ;=========================================================================================
2265 ; 7.7.18.3 set PFR02 Register. External bus mode as General purpose port
2266 ;=========================================================================================
2267 LDI #0x0D82, R1 ; Port Function Register 2, (PFR02)
2268 LDI #0x00, R0 ; load port settings
2269 STB R0, @R1 ; set register
2270 ;=========================================================================================
2271 ; 7.7.18.4 set PFR03 Register. External bus mode as General purpose port
2272 ;=========================================================================================
2273 LDI #0x0D83, R1 ; Port Function Register 3, (PFR03)
2274 LDI #0x00, R0 ; load port settings
2275 STB R0, @R1 ; set register
2276 ;=========================================================================================
2277 ; 7.7.18.5 set PFR04 Register. External bus mode as General purpose port
2278 ;=========================================================================================
2279 LDI #0x0D84, R1 ; Port Function Register 4, (PFR04)
2280 LDI #0x00, R0 ; load port settings
2281 STB R0, @R1 ; set register
2282 ;=========================================================================================
2283 ; 7.7.18.6 set PFR05 Register. External bus mode as General purpose port
2284 ;=========================================================================================
2285 LDI #0x0D85, R1 ; Port Function Register 5, (PFR05)
2286 LDI #0x00, R0 ; load port settings
2287 STB R0, @R1 ; set register
2288 ;=========================================================================================
2289 ; 7.7.18.7 set PFR06 Register. External bus mode as General purpose port
2290 ;=========================================================================================
2291 LDI #0x0D86, R1 ; Port Function Register 6, (PFR06)
2292 LDI #0x00, R0 ; load port settings
2293 STB R0, @R1 ; set register
2294 ;=========================================================================================
2295 ; 7.7.18.8 set PFR07 Register. External bus mode as General purpose port
2296 ;=========================================================================================
2297 LDI #0x0D87, R1 ; Port Function Register 7, (PFR07)
2298 LDI #0x00, R0 ; load port settings
2299 STB R0, @R1 ; set register
2300 ;=========================================================================================
2301 ; 7.7.18.9 set PFR08 Register. External bus mode as General purpose port
2302 ;=========================================================================================
2303 LDI #0x0D88, R1 ; Port Function Register 8, (PFR08)
2304 LDI #0x00, R0 ; load port settings
2305 STB R0, @R1 ; set register
2306 ;=========================================================================================
2307 ; 7.7.18.10 set PFR09 Register. External bus mode as General purpose port
2308 ;=========================================================================================
2309 LDI #0x0D89, R1 ; Port Function Register 9, (PFR09)
2310 LDI #0x00, R0 ; load port settings
2311 STB R0, @R1 ; set register
2312 ;=========================================================================================
2313 ; 7.7.18.11 set PFR10 Register. External bus mode as General purpose port
2314 ;=========================================================================================
2315 LDI #0x0D8A, R1 ; Port Function Register 10, (PFR10)
2316 LDI #0x00, R0 ; load port settings
2317 STB R0, @R1 ; set register
2318 ;=========================================================================================
2319 ; 7.7.18.12 set EPFR10 Register. External bus mode as General purpose port
2320 ;=========================================================================================
2321 LDI #0x0DCA, R1 ; Extended PFR10, (EPFR10)
2322 LDI #0x00, R0 ; load port settings
2323 STB R0, @R1 ; set register
2324 ;=========================================================================================
2326 #elif (EXTBUS == DEFAULT)
2329 emu_sram_cs_mb91461r:
2331 #endif ; #endif (EXTBUS)
2332 #endif ; #endif (excl. devices)
2335 ;=========================================================================================
2336 ; 7.8 Copy code from Flash to I-RAM
2337 ;=========================================================================================
2341 LDI #sizeof(IRAM), R13
2346 LDUB @(R13, R1), R12
2353 ;=========================================================================================
2355 ;=========================================================================================
2356 #if STACK_FILL == ON
2357 LDI #STACK_PATTERN, R0
2359 LDI #sizeof(SSTACK), R2
2361 BEQ:D fill_sstack_end
2371 LDI #STACK_PATTERN, R5
2381 BEQ:D fill_sstack_end
2388 LDI #STACK_PATTERN, R0
2390 LDI #sizeof(USTACK), R2
2392 BEQ:D fill_ustack_end
2402 LDI #STACK_PATTERN, R5
2412 BEQ:D fill_ustack_end
2421 ;=========================================================================================
2422 ; Standard C startup
2423 ;=========================================================================================
2424 ;=========================================================================================
2426 ;=========================================================================================
2427 ; clear DATA section
2428 ; According to ANSI, the DATA section must be cleared during start-up
2430 LDI #sizeof DATA &~0x3, R1
2439 LDI:8 #sizeof DATA & 0x3, R1
2440 LDI #DATA + (sizeof DATA & ~0x3), R13
2451 ;=========================================================================================
2452 ; 7.11 Copy Init section from ROM to RAM
2453 ;=========================================================================================
2455 ; All initialised data's (e.g. int i=1) must be stored in ROM/FLASH area.
2457 ; The Application must copy the Section (Init) into the RAM area.
2460 LDI #sizeof(INIT), R2
2471 LDUB @(R13, R1), R12
2485 ;=========================================================================================
2486 ; 7.12 C library initialization
2487 ;=========================================================================================
2489 CALL32 __stream_init, r12 ; initialise library
2491 ;=========================================================================================
2492 ; 7.13 call C++ constructors
2493 ;=========================================================================================
2495 LDI #___call_dtors, r4
2498 LDI #EXT_CTOR_DTOR, r8
2499 LDI #EXT_CTOR_DTOR + sizeof(EXT_CTOR_DTOR), r9
2512 ;=========================================================================================
2513 ; 7.14 call main routine
2514 ;=========================================================================================
2515 ClearRCwatchdog ; clear harware watchdog
2516 LDI:8 #0, r4 ; Set the 1st parameter for main to 0.
2518 LDI:8 #0, r5 ; Set the 2nd parameter for main to 0.
2528 ;=========================================================================================
2529 ; 7.15 Return from main function
2530 ;=========================================================================================