4 ;=========================================================================================
5 ; 4.1 Controller Device
6 ;=========================================================================================
7 #set MB91464A 2 ; MB91460 series
9 #set MB91467B 10 ; MB91460 series
11 #set MB91467C 11 ; MB91460 series
13 #set MB91467D 4 ; MB91460 series
15 #set MB91469G 6 ; MB91460 series
17 #set MB91465K 3 ; MB91460 series
19 #set MB91463N 8 ; MB91460 series
21 #set MB91461R 1 ; MB91460 series
22 #set MB91467R 5 ; MB91460 series
24 #set MB91465X 9 ; MB91460 series
26 #set others 7 ; MB91460 series
29 #set DEVICE MB91465K ; <<< select device
30 ;=========================================================================================
31 ; 4.3 Stack Type and Stack Size
32 ;=========================================================================================
34 #set USRSTACK 0 ; user stack: for main program
35 #set SYSSTACK 1 ; system stack: for main program and
38 #set STACKUSE SYSSTACK ; <<< set active stack
40 #set STACK_RESERVE ON ; <<< reserve stack area in
42 #set STACK_SYS_SIZE 0x400-4 ; <<< byte size of System stack
43 #set STACK_USR_SIZE 0x2 ; <<< byte size of User stack
45 ; - If the active stack is set to SYSSTACK, it is used for main program and interrupts.
46 ; In this case, the user stack could be set to a dummy size. If the active stack is
47 ; set to user stack, it is used for the main program but the system stack is
48 ; automatically activated, if an interrupt is serviced. Both stack areas must have a
50 ; - If STACK_RESERVE is ON, the sections USTACK and SSTACK are reserved in this module.
51 ; Otherwise, they have to be reserved in other modules. If STACK_RESERVE is OFF, the
52 ; size definitions STACK_SYS_SIZE and STACK_USR_SIZE have no meaning.
53 ; - Even if they are reverved in other modules, they are still initialised in this
56 ; Note: Several library functions require quite a big stack (due to ANSI).
57 ; Check the stack information files (*.stk) in the LIB\911 directory.
59 ;=========================================================================================
60 ; 4.4 Copy code from Flash to I-RAM
61 ;=========================================================================================
63 #set I_RAM ON ; <<< select if code in section IRAM
65 ; If this option is activated code located in the section IRAM is copied during startup
66 ; from ROM to the instruction-RAM. The code is linked for the instruction-RAM.
68 ;=========================================================================================
69 ; 4.7 Clock Configuration
70 ;=========================================================================================
71 ;=========================================================================================
72 ; 4.7.1 Clock Selection
73 ;=========================================================================================
78 ; Sub-oscillation input: 32 kHz
79 #set SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ 0x11
81 ; Oscillation input: 4 MHz
82 #set PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ 0x23
84 ; MB91461R only: Oscillation input: 10 MHz
85 #set PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ 0x41
87 ; MB91461R only: Oscillation input: 20 MHz
88 #set PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ 0x51
95 #set CLOCKSPEED PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ
96 ; ; <<< Select clock configuration
98 ;=========================================================================================
99 ; 4.7.2 Select Clock Modulator
100 ;=========================================================================================
102 #set CLOMO OFF ; <<< Enable /disable clock modulator
104 #set CMPR 0x026F ; <<< Ref. to the data sheet, CMPR
106 ; Please refer to the data sheet of the device if you enable clock modulation. The
107 ; register CMPR dependant on the PLL-Clock.
109 ; Note: If the CLKCAN source is set either to main oscillator or to PLL output then the
110 ; clock for the CAN is not influenced by the clock modulation. If the CLKCAN
111 ; source is set CPU clock (CLKB) then the clock for the CAN is also modulated (if
112 ; the clock modulator is enabled).
114 ; Note: If the clock modulator is enabled, the wait states of the internal flash wait
115 ; states must be adapted to maximum frequency. Please check the wait states
118 ; Note: This feature is not supported by every device, e.g. MB91461. Please check the
121 ;=========================================================================================
122 ; 4.8 External Bus Interface
124 ; The rest of the configuration is only applicable for devices with an external bus
127 ; If the device does not offer an external bus interface, the configuration can be
128 ; stoped at this point.
130 ;=========================================================================================
131 ; 5 Definition of Configurations
132 ;=========================================================================================
134 #set NOCLOCK 0 ; do not touch CKSCR register
135 #set MAINCLOCK 1 ; select main clock
136 ; ; MB91461R : 1/4 of oscillation input
137 ; ; Others: 1/2 of oscillation input
138 #set MAINPLLCLOCK 2 ; select main clock with PLL
139 #set SUBCLOCK 3 ; select subclock (if available)
141 #set PSCLOCK_CLKB 0x00 ; select core clock (initial)
142 #set PSCLOCK_PLL 0x10 ; select PLL output (x)
143 #set PSCLOCK_MAIN 0x30 ; select Main Oscillation
145 ;=========================================================================================
146 ; 5.2 CLOCKSPEED == NO_CLOCK
147 ;=========================================================================================
149 #if (CLOCKSPEED == NO_CLOCK )
150 #set CLOCKSOURCE NOCLOCK
152 ;=========================================================================================
153 ; 5.5 CLOCKSPEED == PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ
154 ;=========================================================================================
156 #if (CLOCKSPEED == PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ )
158 ; Start restriction; Maximum frequency
159 #if (DEVICE == MB91461R)
160 #error: Frequency is not supported by this device.
164 #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
165 #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
166 #set PLLSPEED 0x010F ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 64 MHz
167 #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
168 #set MUL_G 0x0F ; 0x48Fh: PLLMULG;
170 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 64 MHz
171 #set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 16 MHz
172 #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 32 MHz
174 #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 128 MHz
175 #set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 16 MHz
176 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
178 #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
179 #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
181 #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
182 #set FLASHREADT 0xC413 ; 0x7004h: FMWT;
183 #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;
186 ;=========================================================================================
187 ; 6 Section and Data Declaration
188 ;=========================================================================================
193 ;=========================================================================================
194 ; 6.1 Define Stack Size
195 ;=========================================================================================
196 .SECTION SSTACK, STACK, ALIGN=4
197 #if STACK_RESERVE == ON
198 .EXPORT __systemstack, __systemstack_top
200 .RES.B STACK_SYS_SIZE
204 .SECTION USTACK, STACK, ALIGN=4
205 #if STACK_RESERVE == ON
206 .EXPORT __userstack, __userstack_top
208 .RES.B STACK_USR_SIZE
212 ;=========================================================================================
213 ; 6.2 Define Sections
214 ;=========================================================================================
215 .section DATA, data, align=4
216 .section INIT, data, align=4
217 .section IRAM, code, align=4
224 ;-----------------------------------------------------------------------------------------
225 ; MACRO Clear RC Watchdog
226 ;-----------------------------------------------------------------------------------------
227 #macro ClearRCwatchdog
228 LDI #0x4C7,R7 ; clear RC watchdog
231 .section CODE, code, align=4
232 .section CODE_START, code, align=4
233 #pragma section CODE=IRAM,attr=CODE
235 ;=========================================================================================
237 ;=========================================================================================
238 __start: ; start point
242 ANDCCR #0xEF ; disable interrupts
243 STILM #31 ; set interrupt level to low prior
244 ClearRCwatchdog ; clear harware watchdog
246 ;=========================================================================================
247 ; 7.1 Initialise Stack Pointer and Table Base Register
248 ;=========================================================================================
249 #if STACKUSE == SYSSTACK
251 LDI #__userstack_top, SP ; initialize SP
253 LDI #__systemstack_top, SP ; initialize SP
256 #if STACKUSE == USRSTACK
258 LDI #__systemstack_top, SP ; initialize SP
260 LDI #__userstack_top, SP ; initialize SP
266 #if (CLOCKSOURCE != NOCLOCK)
267 ;=========================================================================================
268 ; 7.2 Check for CSV reset and set CSV
269 ;=========================================================================================
270 ; Start restriction; No clock supervisor (CSV)
271 #if (DEVICE != MB91461R) && (DEVICE != MB91467R) && (DEVICE != MB91463N)
273 LDI:20 #0x04AD, R0 ; CSVCR
274 BORL #0x8, @R0 ; Enable Main Osc CSV
275 BTSTH #0x4, @R0 ; Check for Main Osc missing
276 BEQ NoMAINCSVreset ; Main osc available -> branch
278 BANDL #0x7, @R0 ; Disable Main Osc CSV
280 LDI #noClockStartup, R0 ; Main Clock missing -> no
281 JMP @R0 ; clock startup
286 BORL #0x4, @R0 ; Enable Sub Osc CSV
287 BTSTH #0x2, @R0 ; Check for Sub Osc missing
288 BEQ NoSUBCSVreset ; Sub osc available -> branch
290 BANDL #0xB, @R0 ; Disable Sub Osc SCSV
291 #if (CLOCKSOURCE == SUBCLOCK)
292 LDI #noClockStartup, R0 ; Sub Clock missing -> no
293 JMP @R0 ; clock startup
297 ;=========================================================================================
298 ; 7.3 Check Clock Condition
299 ;=========================================================================================
300 LDI #0x484, R0 ; Check for Default Values
305 ;=========================================================================================
306 ; 7.4 Restore Default Settings after Reset
307 ;=========================================================================================
308 ;=========================================================================================
309 ; 7.4.1 Disable Clock Modulator
310 ;=========================================================================================
311 LDI #0x04BB, R0 ; Clock Modulator Control Reg
312 BANDL #0xD, @R0 ; Disable Frequency modulation
314 BTSTL #8, @R0 ; Wait until Frequency modulation
315 BNE FMODwait ; is disabled
317 BANDL #0xE, @R0 ; Power down clock modulator
319 ;=========================================================================================
320 ; 7.4.2 Check if running on Sub Clock, change to Main Clock
321 ;=========================================================================================
322 LDI:20 #0x0484,R12 ; Check if running on sub clock
329 LDI:20 #0x04CC,R12 ; Check if Main Clock is stopped
333 BANDL #0xE, @R12 ; Start Main Oscillation
335 LDI #0x4C8, R0 ; Main Stabilisation Wait Time
336 LDI #0x04, R1 ; 32.7 ms
340 mainStabTime: ; Wait for stabilisation time
341 ClearRCwatchdog ; clear harware watchdog
348 LDI:20 #0x0484, R12 ; disable sub clock as source
349 BANDL #0xD, @R12 ; Clock source = 0x01 (Main/2)
352 ;=========================================================================================
353 ; 7.4.3 Disable Sub Clock
354 ;=========================================================================================
355 #if ENABLE_SUBCLOCK != ON
356 LDI #0x0484, R0 ; Clock source control reg CLKR
357 BANDL #0x7, @R0 ; Disable PLL
360 ;=========================================================================================
361 ; 7.4.4 Check if running on PLL, Gear Down PLL
362 ;=========================================================================================
363 LDI:20 #0x0484,R12 ; Check if running on PLL
370 LDI:20 #0x0490, R11 ; clear flags
374 STB R1, @R11 ; Set Flag for Simulator; no Effekt on
377 BANDL #0xC, @R12 ; disable PLL as clock source
378 ; Clock Source = 0x00 (Main/2)
380 LDI:20 #0x048E,R12 ; check if DivG != 0
387 ClearRCwatchdog ; clear harware watchdog
388 BTSTL #4, @R11 ; Gear Down
391 LDI #0x00,R1 ; Clear Flags
395 ;=========================================================================================
397 ;=========================================================================================
398 LDI #0x0484, R0 ; Clock source control reg CLKR
399 BANDL #0xB, @R0 ; Disable PLL
401 ;=========================================================================================
402 ; 7.4.6 Set to Main Clock
403 ;=========================================================================================
404 LDI:20 #0x0484,R12 ; Check if running on PLL
405 BANDL #0xC, @R12 ; disable PLL as clock source
406 ; Clock Source = 0x00 (Main/2)
409 ;=========================================================================================
410 ; 7.5 Set Memory Controller
411 ;=========================================================================================
412 ; Start restriction; No embedded flash
413 #if DEVICE != MB91461R
415 LDI #0x7002, R1 ; FLASH Controller Reg.
416 LDI #FLASHCONTROL, R2 ; Flash Controller Settings
417 STH R2, @R1 ; set register
418 LDI #0x7004, R1 ; FLASH Memory Wait Timing Reg.
419 LDI #FLASHREADT, R2 ; wait settings
420 STH R2, @R1 ; set register
421 LDI #0x7006, R1 ; FLASH Memory Wait Timing Reg.
422 LDI #FLASHMWT2, R2 ; wait settings
423 STB R2, @R1 ; set register
427 ;=========================================================================================
429 ;=========================================================================================
430 ;=========================================================================================
431 ; 7.6.1 Set Voltage Regulator Settings
432 ;=========================================================================================
433 ; Start restriction; No regulator settings
434 #if DEVICE != MB91461R
436 LDI #0x04CF, R0 ; REGCTR
437 LDI #REGULATORCTRL, R1
440 LDI #0x04CE, R0 ; REGSEL
441 LDI #REGULATORSEL, R1
445 ;=========================================================================================
446 ; 7.6.2 Power on Clock Modulator - Clock Modulator Part I
447 ;=========================================================================================
449 LDI #0x04BB, R0 ; Clock Modulator Control Reg
450 LDI #0x11, R1 ; Load value to Power on CM
451 ORB R1, @R0 ; Power on clock modulaor
454 ;=========================================================================================
455 ; 7.6.3 Set CLKR Register w/o Clock Mode
456 ;=========================================================================================
457 ; Set Clock source (Base Clock) for the three clock tree selections
458 ; This select Base clock is used to select afterwards the 3
459 ; Clocks for the diffenrent internal trees.
460 ; When PLL is used, first pll multiplication ratio is set and PLL is
461 ; enabled. After waiting the PLL stabilisation time via timebase
462 ; timer, PLL clock is selected as clock source.
463 LDI #0x048C, R0 ; PLL Cntl Reg. PLLDIVM/N
467 LDI #0x048E, R0 ; PLL Cntl Reg. PLLDIVG
471 LDI #0x048F, R0 ; PLL Cntl Reg. PLLMULG
475 ;=========================================================================================
477 ;=========================================================================================
478 #if ( ( CLOCKSOURCE == MAINPLLCLOCK ) || ( PSCLOCKSOURCE == PSCLOCK_PLL ) )
479 LDI #0x0484, R0 ; Clock source control reg CLKR
480 LDI #0x04, R1 ; Use PLL x1, enable PLL
481 ORB R1, @R0 ; store data to CLKR register
484 ;=========================================================================================
485 ; 7.6.5 Wait for PLL oscillation stabilisation
486 ;=========================================================================================
487 #if ((CLOCKSOURCE==MAINPLLCLOCK)||(PSCLOCKSOURCE==PSCLOCK_PLL))
488 LDI #0x0482, R12 ; TimeBaseTimer TBCR
489 LDI #0x00, R1 ; set 1024 us @ 2 MHz
492 BANDH #7, @R12 ; clear interrupt flag
494 LDI #0x0483, R0 ; clearTimeBaseTimer CTBR
500 BANDH #7, @R12 ; clear interrupt flag
501 BORH #8, @R12 ; set interrupt flag for simulator
504 ClearRCwatchdog ; clear harware watchdog
509 ;=========================================================================================
511 ;=========================================================================================
512 ;=========================================================================================
513 ; 7.6.6.1 Set CPU and peripheral clock
514 ;=========================================================================================
515 ; CPU and peripheral clock are set in one register
516 LDI #0x0486, R2 ; Set DIVR0 (CPU-clock (CLKB)
517 LDI #((CPUCLOCK << 4) + PERCLOCK), R3 ; Load CPU clock setting
519 ;=========================================================================================
520 ; 7.6.6.2 Set External Bus interface clock
521 ;=========================================================================================
522 ; set External Bus clock
523 ; Be aware to do smooth clock setting, to avoid wrong clock setting
524 ; Take care, always write 0 to the lower 4 bits of DIVR1 register
525 LDI #0x0487, R2 ; Set DIVR1
526 LDI #(EXTBUSCLOCK << 4), R3 ; Load Peripheral clock setting
529 ;=========================================================================================
530 ; 7.6.6.3 Set CAN clock prescaler
531 ;=========================================================================================
532 ; Set CAN Prescaler, only clock relevant parameter
533 LDI #0x04C0, R0 ; Set CAN ClockParameter Register
534 LDI #(PSCLOCKSOURCE + PSDVC), R1 ; Load Divider
535 STB R1, @R0 ; Set Divider
537 LDI #0x04c1, R0 ; Set CAN Clock enable Register
538 LDI #CANCLOCK, R1 ; Load CANCLOCK
539 STB R1, @R0 ; set CANCLOCK
541 ;=========================================================================================
542 ; 7.6.7 Switch to PLL Mode
543 ;=========================================================================================
544 #if ( (CLOCKSOURCE == MAINPLLCLOCK) )
547 LDI #0x0490, R0 ; PLL Ctrl Register
549 STB R1, @R0 ; Clear Flag
551 STB R1, @R0 ; Set Flag for Simulator; no Effekt on
554 LDI #0x0484, R3 ; Clock source control reg CLKR
555 BORL #0x2, @R3 ; enable PLL as clock source
559 ClearRCwatchdog ; clear harware watchdog
560 LDUB @R0, R2 ; LOAD PLLCTR to R2
561 AND R1, R2 ; GRUP, counter reach 0
565 STB R1, @R0 ; Clear Gear-Up Flag
570 ;=========================================================================================
571 ; 7.6.8 Enable Frequncy Modulation - Clock Modulator Part II
572 ;=========================================================================================
573 #if CLOMO == ON ; Only applicable if Modulator is on
574 LDI #0x04B8, R0 ; Clock Modulation Parameter Reg
575 LDI #CMPR, R1 ; Load CMP value
576 STH R1, @R0 ; Store CMP value in CMPR
578 LDI #0x04BB, R0 ; Clock Modulator Control Reg
579 LDI #0x13, R1 ; Load value to FM on CM
587 ;=========================================================================================
588 ; 7.8 Copy code from Flash to I-RAM
589 ;=========================================================================================
593 LDI #sizeof(IRAM), R13
605 ;=========================================================================================
607 ;=========================================================================================
608 ;=========================================================================================
610 ;=========================================================================================
612 ; According to ANSI, the DATA section must be cleared during start-up
614 LDI #sizeof DATA &~0x3, R1
623 LDI:8 #sizeof DATA & 0x3, R1
624 LDI #DATA + (sizeof DATA & ~0x3), R13
635 ;=========================================================================================
636 ; 7.11 Copy Init section from ROM to RAM
637 ;=========================================================================================
639 ; All initialised data's (e.g. int i=1) must be stored in ROM/FLASH area.
641 ; The Application must copy the Section (Init) into the RAM area.
644 LDI #sizeof(INIT), R2
670 ;=========================================================================================
671 ; 7.14 call main routine
672 ;=========================================================================================
673 ClearRCwatchdog ; clear harware watchdog
674 LDI:8 #0, r4 ; Set the 1st parameter for main to 0.
676 LDI:8 #0, r5 ; Set the 2nd parameter for main to 0.
677 ;=========================================================================================
678 ; 7.15 Return from main function
679 ;=========================================================================================