#include "host.h"
#include "../usbspec/usb11spec.h"
-// macro for accessing u32 variables that need to be in little endian byte order;
-// whenever you read or write from an u32 field that the ohci host controller
-// will read or write from too, use this macro for access!
-#define ACCESS_LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
+/* activate control_quirk */
+#define _USE_C_Q
+
+/* macro for accessing u32 variables that need to be in little endian byte order;
+ *
+ * whenever you read or write from an u32 field that the ohci host controller
+ * will read or write from too, use this macro for access!
+ */
+#define LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
(((dword) & 0x00FF0000) >> 8) | \
(((dword) & 0x0000FF00) << 8) | \
(((dword) & 0x000000FF) << 24) )
-static struct endpoint_descriptor *allocate_endpoint();
-static struct general_td *allocate_general_td(size_t);
-static void control_quirk();
-static void dbg_op_state();
-static void dbg_td_flag(u32 flag);
-static void configure_ports(u8 from_init);
-static void setup_port(u32 reg, u8 from_init);
+static struct general_td *allocate_general_td();
+static void dbg_op_state(u32 reg);
+static void configure_ports(u8 from_init, u32 reg);
+static void setup_port(u32 ohci, u32 reg, u8 from_init);
static struct ohci_hcca hcca_oh0;
+static struct ohci_hcca hcca_oh1;
-static struct endpoint_descriptor *allocate_endpoint()
-{
- struct endpoint_descriptor *ep;
- ep = (struct endpoint_descriptor *)memalign(16, sizeof(struct endpoint_descriptor));
- ep->flags = ACCESS_LE(OHCI_ENDPOINT_GENERAL_FORMAT);
- ep->headp = ep->tailp = ep->nexted = ACCESS_LE(0);
- return ep;
-}
-
-static struct general_td *allocate_general_td(size_t bsize)
+static struct general_td *allocate_general_td()
{
struct general_td *td;
td = (struct general_td *)memalign(16, sizeof(struct general_td));
- td->flags = ACCESS_LE(0);
- td->nexttd = ACCESS_LE(0);
- td->cbp = td->be = ACCESS_LE(0);
+ memset(td, 0, sizeof(struct general_td));
+ td->flags = LE(0);
+ td->nexttd = LE(0);
+ td->cbp = td->be = LE(0);
return td;
}
-static void control_quirk()
-{
- static struct endpoint_descriptor *ed = 0; /* empty ED */
- static struct general_td *td = 0; /* dummy TD */
- u32 head;
- u32 current;
- u32 status;
-
- /*
- * One time only.
- * Allocate and keep a special empty ED with just a dummy TD.
- */
- if (!ed) {
- ed = allocate_endpoint();
- if (!ed)
- return;
-
- td = allocate_general_td(0);
- if (!td) {
- free(ed);
- ed = NULL;
- return;
- }
-
-#define ED_MASK ((u32)~0x0f)
- ed->tailp = ed->headp = ACCESS_LE(virt_to_phys((void*) ((u32)td & ED_MASK)));
- ed->flags |= ACCESS_LE(OHCI_ENDPOINT_DIRECTION_OUT);
- }
-
- /*
- * The OHCI USB host controllers on the Nintendo Wii
- * video game console stop working when new TDs are
- * added to a scheduled control ED after a transfer has
- * has taken place on it.
- *
- * Before scheduling any new control TD, we make the
- * controller happy by always loading a special control ED
- * with a single dummy TD and letting the controller attempt
- * the transfer.
- * The controller won't do anything with it, as the special
- * ED has no TDs, but it will keep the controller from failing
- * on the next transfer.
- */
- head = read32(OHCI0_HC_CTRL_HEAD_ED);
- if (head) {
- printf("head: 0x%08X\n", head);
- /*
- * Load the special empty ED and tell the controller to
- * process the control list.
- */
- sync_after_write(ed, 16);
- sync_after_write(td, 16);
- write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed));
-
- status = read32(OHCI0_HC_CONTROL);
- set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
- write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
-
- /* spin until the controller is done with the control list */
- current = read32(OHCI0_HC_CTRL_CURRENT_ED);
- while(!current) {
- udelay(10);
- current = read32(OHCI0_HC_CTRL_CURRENT_ED);
- }
-
- printf("current: 0x%08X\n", current);
-
- /* restore the old control head and control settings */
- write32(OHCI0_HC_CONTROL, status);
- write32(OHCI0_HC_CTRL_HEAD_ED, head);
- } else {
- printf("nohead!\n");
- }
-}
-
-static void dbg_op_state()
+static void dbg_op_state(u32 reg)
{
- switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
+ switch (read32(reg+OHCI_HC_CONTROL) & OHCI_CTRL_HCFS) {
case OHCI_USB_SUSPEND:
printf("ohci-- OHCI_USB_SUSPEND\n");
break;
}
}
+#ifdef _DU_OHCI_F_HALT
static void dbg_td_flag(u32 flag)
{
printf("**************** dbg_td_flag: 0x%08X ***************\n", flag);
printf(" R: %X\n", (flag>>18)&1);
printf("********************************************************\n");
}
+#endif
-static void general_td_fill(struct general_td *dest, const usb_transfer_descriptor *src)
+static void general_td_fill(struct general_td *dest, const struct usb_transfer_descriptor *src)
{
- dest->cbp = ACCESS_LE(virt_to_phys(src->buffer));
- dest->be = ACCESS_LE(ACCESS_LE(dest->cbp) + src->actlen - 1);
- dest->flags &= ACCESS_LE(~OHCI_TD_DIRECTION_PID_MASK);
+ if(src->actlen) {
+ dest->cbp = LE(virt_to_phys(src->buffer));
+ dest->be = LE(LE(dest->cbp) + src->actlen - 1);
+ /* save virtual address here */
+ dest->bufaddr = (u32) src->buffer;
+ }
+ else {
+ dest->cbp = dest->be = LE(0);
+ dest->bufaddr = 0;
+ }
+
+ dest->buflen = src->actlen;
+
+ dest->flags &= LE(~OHCI_TD_DIRECTION_PID_MASK);
switch(src->pid) {
case USB_PID_SETUP:
+#ifdef _DU_OHCI_Q
printf("pid_setup\n");
- dest->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_SETUP);
- dest->flags |= ACCESS_LE(OHCI_TD_TOGGLE_0);
- dest->flags |= ACCESS_LE(OHCI_TD_BUFFER_ROUNDING);
+#endif
+ dest->flags |= LE(OHCI_TD_DIRECTION_PID_SETUP);
+ dest->flags |= LE(OHCI_TD_TOGGLE_0);
+ dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
break;
case USB_PID_OUT:
+#ifdef _DU_OHCI_Q
printf("pid_out\n");
- dest->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_OUT);
- dest->flags |= ACCESS_LE(OHCI_TD_BUFFER_ROUNDING);
+#endif
+ dest->flags |= LE(OHCI_TD_DIRECTION_PID_OUT);
+ dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
/*
- * TODO: just temporary solution!
+ * TODO: just temporary solution! (consider it with len?)
* there can be also regular PID_OUT pakets
*/
- dest->flags |= ACCESS_LE(OHCI_TD_TOGGLE_1);
+ dest->flags |= LE(OHCI_TD_TOGGLE_1);
break;
case USB_PID_IN:
+#ifdef _DU_OHCI_Q
printf("pid_in\n");
- dest->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_IN);
- dest->flags |= ACCESS_LE(OHCI_TD_BUFFER_ROUNDING);
+#endif
+ dest->flags |= LE(OHCI_TD_DIRECTION_PID_IN);
+ if(src->maxp > src->actlen) {
+ dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
+#ifdef _DU_OHCI_Q
+ printf("round buffer!\n");
+#endif
+ }
/*
* let the endpoint do the togglestuff!
* TODO: just temporary solution!
* there can be also inregular PID_IN pakets (@Status Stage)
*/
- dest->flags |= ACCESS_LE(OHCI_TD_TOGGLE_CARRY);
-#if 0
- /* should be done by HC!
- * first pid_in start with DATA0 */
- */
- dummyconfig.headp = ACCESS_LE( src->togl ?
- ACCESS_LE(dummyconfig.headp) | OHCI_ENDPOINT_TOGGLE_CARRY :
- ACCESS_LE(dummyconfig.headp) & ~OHCI_ENDPOINT_TOGGLE_CARRY);
-#endif
+ dest->flags |= LE(OHCI_TD_TOGGLE_CARRY);
break;
}
- dest->flags |= ACCESS_LE(OHCI_TD_SET_DELAY_INTERRUPT(7));
- sync_after_write(dest, sizeof(struct general_td));
- sync_after_write((void*) phys_to_virt(ACCESS_LE(dest->cbp)), src->actlen);
+ dest->flags |= LE(OHCI_TD_SET_DELAY_INTERRUPT(7));
}
+#ifdef _DU_OHCI_F_HALT
static void dump_address(void *addr, u32 size, const char* str)
{
- sync_before_read(addr, size);
- printf("%s hexdump @ 0x%08X:\n", str, addr);
+ printf("%s hexdump (%d) @ 0x%08X:\n", str, size, addr);
hexdump(addr, size);
}
+#endif
-/**
- * Enqueue a transfer descriptor.
- */
-u8 first = 0;
-u8 hcdi_enqueue(const usb_transfer_descriptor *td) {
- static struct general_td *tSetup,*tData;
- static u32 tSetupbuffer, tDatabuffer, tStatusbuffer;
- static u32 tSetupblen, tDatablen, tStatusblen;
-
- if(first == 0) {
- printf("step 0\n");
- tSetup = allocate_general_td(td->actlen);
- general_td_fill(tSetup, td);
- tSetupbuffer = (u32) phys_to_virt(ACCESS_LE(tSetup->cbp));
- tSetupblen = td->actlen;
- first++;
- return 0;
- }
- if(first == 1) {
- printf("step 1\n");
- tData = allocate_general_td(td->actlen);
- general_td_fill(tData, td);
- tDatabuffer = (u32) phys_to_virt(ACCESS_LE(tData->cbp));
- tDatablen = td->actlen;
- first++;
- return 0;
+static struct endpoint_descriptor _edhead;
+struct endpoint_descriptor *edhead = 0;
+void hcdi_fire(u32 reg)
+{
+#ifdef _DU_OHCI_F
+ printf("<^> <^> <^> hcdi_fire(start)\n");
+#endif
+
+ if(edhead == 0)
+ return;
+
+#ifdef _USE_C_Q
+ /* quirk... 11ms seems to be a minimum :O */
+ udelay(11000);
+#endif
+
+ write32(reg+OHCI_HC_CTRL_HEAD_ED, virt_to_phys(edhead));
+
+ /* sync it all */
+ sync_after_write(edhead, sizeof(struct endpoint_descriptor));
+#ifdef _DU_OHCI_F
+ dump_address(edhead, sizeof(struct endpoint_descriptor), "edhead(before)");
+#endif
+
+ struct general_td *x = phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
+ while(virt_to_phys(x)) {
+ sync_after_write(x, sizeof(struct general_td));
+#ifdef _DU_OHCI_F
+ dump_address(x, sizeof(struct general_td), "x(before)");
+#endif
+
+ if(x->buflen > 0) {
+ sync_after_write((void*) phys_to_virt(LE(x->cbp)), x->buflen);
+#ifdef _DU_OHCI_F
+ dump_address((void*) phys_to_virt(LE(x->cbp)), x->buflen, "x->cbp(before)");
+#endif
+ }
+ x = phys_to_virt(LE(x->nexttd));
}
- first = 0;
- struct general_td *tStatus = allocate_general_td(td->actlen);
- general_td_fill(tStatus, td);
- tStatusbuffer = (u32) phys_to_virt(ACCESS_LE(tStatus->cbp));
- tStatusblen = td->actlen;
-
- printf( "===========================\n"
- "===========================\n");
- control_quirk(); //required? YES! :O ... erm... or no? :/ ... in fact I have no idea
-
- struct endpoint_descriptor *dummyconfig = allocate_endpoint();
- dummyconfig->flags = ACCESS_LE(OHCI_ENDPOINT_GENERAL_FORMAT);
- dummyconfig->headp = dummyconfig->tailp = dummyconfig->nexted = ACCESS_LE(0);
- dummyconfig->flags |= ACCESS_LE(OHCI_ENDPOINT_LOW_SPEED |
- OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
- OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
- OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
- write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(dummyconfig));
-
-#define ED_MASK ((u32)~0x0f)
- dummyconfig->headp |= ACCESS_LE(virt_to_phys((void*) ((u32)tSetup & ED_MASK)));
- tSetup->nexttd = ACCESS_LE(virt_to_phys((void*) ((u32)tData & ED_MASK)));
- tData->nexttd = ACCESS_LE(virt_to_phys((void*) ((u32)tStatus & ED_MASK)));
-
- sync_after_write(dummyconfig, 16);
- sync_after_write(tSetup, sizeof(struct general_td));
- sync_after_write(tData, sizeof(struct general_td));
- sync_after_write(tStatus, sizeof(struct general_td));
-
- dump_address(tSetup, sizeof(struct general_td), "tSetup(before)");
- dump_address((void*) phys_to_virt(ACCESS_LE(tSetup->cbp)), tSetupblen, "tSetup->cbp(before)");
-
- dump_address(tData, sizeof(struct general_td), "tData(before)");
- dump_address((void*) phys_to_virt(ACCESS_LE(tData->cbp)), tDatablen, "tData->cbp(before)");
-
- dump_address(tStatus, sizeof(struct general_td), "tStatus(before)");
- dump_address((void*) phys_to_virt(ACCESS_LE(tStatus->cbp)), tStatusblen, "tStatus->cbp(before)");
-
- dump_address(dummyconfig, sizeof(struct endpoint_descriptor), "dummyconfig(before)");
-
- printf("ctrl head: 0x%08X\n", read32(OHCI0_HC_CTRL_HEAD_ED));
+
/* trigger control list */
- set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
- write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
+ set32(reg+OHCI_HC_CONTROL, OHCI_CTRL_CLE);
+ write32(reg+OHCI_HC_COMMAND_STATUS, OHCI_CLF);
+
+ struct general_td *n=0, *prev = 0, *next = 0;
+ /* poll until edhead->headp is null */
+ do {
+ sync_before_read(edhead, sizeof(struct endpoint_descriptor));
+#ifdef _DU_OHCI_F
+ printf("edhead->headp: 0x%08X\n", LE(edhead->headp));
+ udelay(10000);
+#endif
+
+ /* if halted, debug output plz. will break the transfer */
+ if((LE(edhead->headp) & OHCI_ENDPOINT_HALTED)) {
+ n = phys_to_virt(LE(edhead->headp)&~0xf);
+ prev = phys_to_virt((u32)prev);
+#ifdef _DU_OHCI_F_HALT
+ printf("halted!\n");
+#endif
+
+ sync_before_read((void*) n, sizeof(struct general_td));
+#ifdef _DU_OHCI_F_HALT
+ printf("n: 0x%08X\n", n);
+ dump_address(n, sizeof(struct general_td), "n(after)");
+#endif
+ if(n->buflen > 0) {
+ sync_before_read((void*) n->bufaddr, n->buflen);
+#ifdef _DU_OHCI_F_HALT
+ dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
+#endif
+ }
+#ifdef _DU_OHCI_F_HALT
+ dbg_td_flag(LE(n->flags));
+#endif
+
+ sync_before_read((void*) prev, sizeof(struct general_td));
+#ifdef _DU_OHCI_F_HALT
+ printf("prev: 0x%08X\n", prev);
+ dump_address(prev, sizeof(struct general_td), "prev(after)");
+#endif
+ if(prev->buflen >0) {
+ sync_before_read((void*) prev->bufaddr, prev->buflen);
+#ifdef _DU_OHCI_F_HALT
+ dump_address((void*) prev->bufaddr, prev->buflen, "prev->bufaddr(after)");
+#endif
+ }
+#ifdef _DU_OHCI_F_HALT
+ dbg_td_flag(LE(prev->flags));
+ printf("halted end!\n");
+#endif
+ return;
+ }
+ prev = (struct general_td*) (LE(edhead->headp)&~0xf);
+ } while(LE(edhead->headp)&~0xf);
+
+ n = phys_to_virt(read32(reg+OHCI_HC_DONE_HEAD) & ~1);
+#ifdef _DU_OHCI_F
+ printf("hc_done_head: 0x%08X\n", read32(reg+OHCI_HC_DONE_HEAD));
+#endif
- //don't use this quirk stuff here!
-#if 1
- while(!read32(OHCI0_HC_CTRL_CURRENT_ED)) {
+ prev = 0; next = 0;
+ /* reverse done queue */
+ while(virt_to_phys(n) && edhead->tdcount) {
+ sync_before_read((void*) n, sizeof(struct general_td));
+#ifdef _DU_OHCI_F
+ printf("n: 0x%08X\n", n);
+ printf("next: 0x%08X\n", next);
+ printf("prev: 0x%08X\n", prev);
+#endif
+
+ next = n;
+ n = (struct general_td*) phys_to_virt(LE(n->nexttd));
+ next->nexttd = (u32) prev;
+ prev = next;
+
+ edhead->tdcount--;
}
+
+ n = next;
+ prev = 0;
+ while(virt_to_phys(n)) {
+#ifdef _DU_OHCI_F
+ dump_address(n, sizeof(struct general_td), "n(after)");
#endif
+ if(n->buflen > 0) {
+ sync_before_read((void*) n->bufaddr, n->buflen);
+#ifdef _DU_OHCI_F
+ dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
+#endif
+ }
+#ifdef _DU_OHCI_F
+ dbg_td_flag(LE(n->flags));
+#endif
+ prev = n;
+ n = (struct general_td*) n->nexttd;
+ free(prev);
+ }
- udelay(100000);
- u32 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
- printf("current: 0x%08X\n", current);
- printf("+++++++++++++++++++++++++++++\n");
- udelay(100000);
+ if(reg == OHCI0_REG_BASE) {
+ hcca_oh0.done_head = 0;
+ sync_after_write(&hcca_oh0, sizeof(hcca_oh0));
+ } else if (reg == OHCI1_REG_BASE) {
+ hcca_oh1.done_head = 0;
+ sync_after_write(&hcca_oh1, sizeof(hcca_oh1));
+ }
- dump_address(tSetup, sizeof(struct general_td), "tSetup(after)");
- dump_address((void*) phys_to_virt(ACCESS_LE(tSetup->cbp)), tSetupblen, "tSetup->cbp(after)");
- dump_address((void*) tSetupbuffer, tSetupblen, "tSetupbuffer");
- dbg_td_flag(ACCESS_LE(tSetup->flags));
+ write32(reg+OHCI_HC_CONTROL, read32(reg+OHCI_HC_CONTROL)&~OHCI_CTRL_CLE);
- dump_address(tData, sizeof(struct general_td), "tData(after)");
- dump_address((void*) phys_to_virt(ACCESS_LE(tData->cbp)), tDatablen, "tData->cbp(after)");
- dump_address((void*) tDatabuffer, tDatablen, "tDatabuffer");
- dbg_td_flag(ACCESS_LE(tData->flags));
+ edhead = 0;
- dump_address(tStatus, sizeof(struct general_td), "tStatus(after)");
- //dump_address((void*) phys_to_virt(ACCESS_LE(tStatus->cbp)), tStatusblen, "tStatus->cbp(after)");
- //dump_address((void*) tStatusbuffer, tStatusblen, "tStatusbuffer");
- dbg_td_flag(ACCESS_LE(tStatus->flags));
+#ifdef _DU_OHCI_F
+ printf("<^> <^> <^> hcdi_fire(end)\n");
+#endif
+}
- dump_address(dummyconfig, sizeof(struct endpoint_descriptor), "dummyconfig(after)");
+/**
+ * Enqueue a transfer descriptor.
+ */
+u8 hcdi_enqueue(const struct usb_transfer_descriptor *td, u32 reg) {
+#ifdef _DU_OHCI_Q
+ printf("*()*()*()*()*()*()*() hcdi_enqueue(start)\n");
+#endif
+ if(!edhead) {
+ edhead = &_edhead;
+ memset(edhead, 0, sizeof(struct endpoint_descriptor));
+ edhead->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
+ edhead->headp = edhead->tailp = edhead->nexted = LE(0);
+ if(td->fullspeed) {
+ edhead->flags |= LE(OHCI_ENDPOINT_FULL_SPEED);
+ } else {
+ edhead->flags |= LE(OHCI_ENDPOINT_LOW_SPEED);
+ }
+ edhead->flags |= LE(OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
+ OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
+ OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
+ edhead->tdcount = 0;
+ }
- /* disable control list */
- write32(OHCI0_HC_CONTROL, read32(OHCI0_HC_CONTROL)&~OHCI_CTRL_CLE);
+ struct general_td *tdhw = allocate_general_td();
+ general_td_fill(tdhw, td);
+ edhead->tdcount ++;
- /* TODO
- * TD should be free'd after taking it from the done queue.
- */
+ if(!edhead->headp) {
+ /* first transfer */
+ edhead->headp = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
+ }
+ else {
+ /* headp in endpoint already exists
+ * => go to list end
+ */
+ struct general_td *n = (struct general_td*) phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
+ while(LE(n->nexttd)) {
+ n = phys_to_virt(LE(n->nexttd));
+ }
+ n->nexttd = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
+#ifdef _DU_OHCI_Q
+ printf("n: 0x%08X\n", n);
+ printf("n->nexttd: 0x%08X\n", phys_to_virt(LE(n->nexttd)));
+#endif
+ }
-#if 1
- free(tSetup);
- free(tData);
- free(tStatus);
- free(dummyconfig);
+#ifdef _DU_OHCI_Q
+ printf("*()*()*()*()*()*()*() hcdi_enqueue(end)\n");
#endif
- printf("hcdi_enqueue, done!\n");
return 0;
}
+
/**
* Remove an transfer descriptor from transfer queue.
*/
-u8 hcdi_dequeue(usb_transfer_descriptor *td) {
+u8 hcdi_dequeue(struct usb_transfer_descriptor *td, u32 reg) {
return 0;
}
-void hcdi_init()
+void hcdi_init(u32 reg)
{
printf("ohci-- init\n");
- dbg_op_state();
+ dbg_op_state(reg);
/* disable hc interrupts */
- set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
+ set32(reg+OHCI_HC_INT_DISABLE, OHCI_INTR_MIE);
/* save fmInterval and calculate FSMPS */
#define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
#define FI 0x2edf /* 12000 bits per frame (-1) */
- u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
+ u32 fmint = read32(reg+OHCI_HC_FM_INTERVAL) & 0x3fff;
if(fmint != FI)
printf("ohci-- fminterval delta: %d\n", fmint - FI);
fmint |= FSMP (fmint) << 16;
set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
/* reset HC */
- write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
+ write32(reg+OHCI_HC_COMMAND_STATUS, OHCI_HCR);
/* wait max. 30us */
u32 ts = 30;
- while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
+ while ((read32(reg+OHCI_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
if(--ts == 0) {
printf("ohci-- FAILED");
return;
/* Tell the controller where the control and bulk lists are
* The lists are empty now. */
- write32(OHCI0_HC_CTRL_HEAD_ED, 0);
- write32(OHCI0_HC_BULK_HEAD_ED, 0);
+ write32(reg+OHCI_HC_CTRL_HEAD_ED, 0);
+ write32(reg+OHCI_HC_BULK_HEAD_ED, 0);
/* set hcca adress */
- sync_after_write(&hcca_oh0, 256);
- write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
+ if(reg == OHCI0_REG_BASE) {
+ sync_after_write(&hcca_oh0, 256);
+ write32(reg+OHCI_HC_HCCA, virt_to_phys(&hcca_oh0));
+ } else {
+ sync_after_write(&hcca_oh1, 256);
+ write32(reg+OHCI_HC_HCCA, virt_to_phys(&hcca_oh1));
+ }
/* set periodicstart */
#define FIT (1<<31)
- u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
- u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
+ u32 fmInterval = read32(reg+OHCI_HC_FM_INTERVAL) &0x3fff;
+ u32 fit = read32(reg+OHCI_HC_FM_INTERVAL) & FIT;
- write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
- write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
+ write32(reg+OHCI_HC_FM_INTERVAL, fmint | (fit ^ FIT));
+ write32(reg+OHCI_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
/* testing bla */
- if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
+ if ((read32(reg+OHCI_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(reg+OHCI_HC_PERIODIC_START)) {
printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
}
/* start HC operations */
- write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
+ write32(reg+OHCI_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
/* wake on ConnectStatusChange, matching external hubs */
- write32(OHCI0_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC);
+ write32(reg+OHCI_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC);
/* Choose the interrupts we care about now, others later on demand */
- write32(OHCI0_HC_INT_STATUS, ~0);
- write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
+ write32(reg+OHCI_HC_INT_STATUS, ~0);
+ write32(reg+OHCI_HC_INT_ENABLE, OHCI_INTR_INIT);
//wtf?
- wait_ms ((read32(OHCI0_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe);
+ wait_ms ((read32(reg+OHCI_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe);
- configure_ports((u8)1);
+ configure_ports((u8)1, reg);
irq_restore(cookie);
- dbg_op_state();
+ dbg_op_state(reg);
}
-static void configure_ports(u8 from_init)
+static void configure_ports(u8 from_init, u32 reg)
{
- printf("OHCI0_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_A));
- printf("OHCI0_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_B));
- printf("OHCI0_HC_RH_STATUS:\t\t0x%08X\n", read32(OHCI0_HC_RH_STATUS));
- printf("OHCI0_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_1));
- printf("OHCI0_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_2));
-
- setup_port(OHCI0_HC_RH_PORT_STATUS_1, from_init);
- setup_port(OHCI0_HC_RH_PORT_STATUS_2, from_init);
+#ifdef _DU_OHCI_RH
+ printf("=== Roothub @ %s ===\n", reg == OHCI0_REG_BASE ? "OHCI0" : "OHCI1");
+ printf("OHCI_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(reg+OHCI_HC_RH_DESCRIPTOR_A));
+ printf("OHCI_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(reg+OHCI_HC_RH_DESCRIPTOR_B));
+ printf("OHCI_HC_RH_STATUS:\t\t0x%08X\n", read32(reg+OHCI_HC_RH_STATUS));
+ printf("OHCI_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(reg+OHCI_HC_RH_PORT_STATUS_1));
+ printf("OHCI_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(reg+OHCI_HC_RH_PORT_STATUS_2));
+#endif
+
+ setup_port(reg, reg+OHCI_HC_RH_PORT_STATUS_1, from_init);
+ setup_port(reg, reg+OHCI_HC_RH_PORT_STATUS_2, from_init);
+#ifdef _DU_OHCI_RH
printf("configure_ports done\n");
+#endif
}
-static void setup_port(u32 reg, u8 from_init)
+static void setup_port(u32 ohci, u32 reg, u8 from_init)
{
u32 port = read32(reg);
if((port & RH_PS_CCS) && ((port & RH_PS_CSC) || from_init)) {
/* clear CSC flag, set PES and start port reset (PRS) */
write32(reg, RH_PS_PES);
while(!(read32(reg) & RH_PS_PES)) {
+#ifdef _DU_OHCI_RH
printf("fu\n");
+#endif
return;
}
/* spin until port reset is complete */
while(!(read32(reg) & RH_PS_PRSC)); // hint: it may stuck here
+#ifdef _DU_OHCI_RH
printf("loop done\n");
+#endif
- wait_ms(20);
-
- (void) usb_add_device();
+ /* returns usb_device struct */
+ (void) usb_add_device((read32(reg) & RH_PS_LSDA) >> 8, ohci);
}
}
-void hcdi_irq()
+void hcdi_irq(u32 reg)
{
/* read interrupt status */
- u32 flags = read32(OHCI0_HC_INT_STATUS);
+ u32 flags = read32(reg+OHCI_HC_INT_STATUS);
/* when all bits are set to 1 some problem occured */
if (flags == 0xffffffff) {
}
/* only care about interrupts that are enabled */
- flags &= read32(OHCI0_HC_INT_ENABLE);
+ flags &= read32(reg+OHCI_HC_INT_ENABLE);
/* nothing to do? */
if (flags == 0) {
if (flags & OHCI_INTR_RHSC) {
printf("RootHubStatusChange\n");
/* TODO: set some next_statechange variable... */
- configure_ports(0);
- write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
+ configure_ports(0, reg);
+ write32(reg+OHCI_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
}
/* ResumeDetected */
else if (flags & OHCI_INTR_RD) {
printf("ResumeDetected\n");
- write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
+ write32(reg+OHCI_HC_INT_STATUS, OHCI_INTR_RD);
/* TODO: figure out what the linux kernel does here... */
}
#define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
if (HC_IS_RUNNING()) {
- write32(OHCI0_HC_INT_STATUS, flags);
- write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);
+ write32(reg+OHCI_HC_INT_STATUS, flags);
+ write32(reg+OHCI_HC_INT_ENABLE, OHCI_INTR_MIE);
}
}
-void show_frame_no()
+void show_frame_no(u32 reg)
{
- sync_before_read(&hcca_oh0, 256);
- printf("***** frame_no: %d *****\n", ACCESS_LE(hcca_oh0.frame_no));
+ if(reg == OHCI0_REG_BASE) {
+ sync_before_read(&hcca_oh0, 256);
+ printf("***** frame_no: %d *****\n", LE(hcca_oh0.frame_no));
+ } else if (reg == OHCI1_REG_BASE) {
+ sync_before_read(&hcca_oh1, 256);
+ printf("***** frame_no: %d *****\n", LE(hcca_oh1.frame_no));
+ }
}
projects / ppcskel.git / blobdiff