usb/host/ohci.c

   1 /*
   2        ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
   3        ohci hardware support
   4
   5 Copyright (C) 2009     Bernhard Urban <lewurm@gmx.net>
   6 Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
   7
   8 # This code is licensed to you under the terms of the GNU GPL, version 2;
   9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
  10 */
  11
  12 #include "../../bootmii_ppc.h"
  13 #include "../../hollywood.h"
  14 #include "../../irq.h"
  15 #include "../../string.h"
  16 #include "../../malloc.h"
  17 #include "ohci.h"
  18 #include "host.h"
  19 #include "../usbspec/usb11spec.h"
  20
  21 /* macro for accessing u32 variables that need to be in little endian byte order;
  22  *
  23  * whenever you read or write from an u32 field that the ohci host controller
  24  * will read or write from too, use this macro for access!
  25  */
  26 #define LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
  27                            (((dword) & 0x00FF0000) >> 8)  | \
  28                            (((dword) & 0x0000FF00) << 8)  | \
  29                            (((dword) & 0x000000FF) << 24) )
  30
  31 static struct endpoint_descriptor *allocate_endpoint();
  32 static struct general_td *allocate_general_td();
  33 static void control_quirk();
  34 static void dbg_op_state();
  35 //static void dbg_td_flag(u32 flag);
  36 static void configure_ports(u8 from_init);
  37 static void setup_port(u32 reg, u8 from_init);
  38
  39 static struct ohci_hcca hcca_oh0;
  40
  41
  42 static struct endpoint_descriptor *allocate_endpoint()
  43 {
  44         struct endpoint_descriptor *ep;
  45         ep = (struct endpoint_descriptor *)memalign(16, sizeof(struct endpoint_descriptor));
  46         memset(ep, 0, sizeof(struct endpoint_descriptor));
  47         ep->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
  48         ep->headp = ep->tailp = ep->nexted = LE(0);
  49         return ep;
  50 }
  51
  52 static struct general_td *allocate_general_td()
  53 {
  54         struct general_td *td;
  55         td = (struct general_td *)memalign(16, sizeof(struct general_td));
  56         memset(td, 0, sizeof(struct general_td));
  57         td->flags = LE(0);
  58         td->nexttd = LE(0);
  59         td->cbp = td->be = LE(0);
  60         return td;
  61 }
  62
  63 static void control_quirk()
  64 {
  65         static struct endpoint_descriptor *ed = 0; /* empty ED */
  66         static struct general_td *td = 0; /* dummy TD */
  67         u32 head;
  68         u32 current;
  69         u32 status;
  70
  71         /*
  72          * One time only.
  73          * Allocate and keep a special empty ED with just a dummy TD.
  74          */
  75         if (!ed) {
  76                 ed = allocate_endpoint();
  77                 if (!ed)
  78                         return;
  79
  80                 td = allocate_general_td(0);
  81                 if (!td) {
  82                         free(ed);
  83                         ed = NULL;
  84                         return;
  85                 }
  86
  87                 ed->tailp = ed->headp = LE(virt_to_phys((void*) ((u32)td & OHCI_ENDPOINT_HEAD_MASK)));
  88                 ed->flags |= LE(OHCI_ENDPOINT_DIRECTION_OUT);
  89         }
  90
  91         /*
  92          * The OHCI USB host controllers on the Nintendo Wii
  93          * video game console stop working when new TDs are
  94          * added to a scheduled control ED after a transfer has
  95          * has taken place on it.
  96          *
  97          * Before scheduling any new control TD, we make the
  98          * controller happy by always loading a special control ED
  99          * with a single dummy TD and letting the controller attempt
 100          * the transfer.
 101          * The controller won't do anything with it, as the special
 102          * ED has no TDs, but it will keep the controller from failing
 103          * on the next transfer.
 104          */
 105         head = read32(OHCI0_HC_CTRL_HEAD_ED);
 106         if (head) {
 107                 printf("head: 0x%08X\n", head);
 108                 /*
 109                  * Load the special empty ED and tell the controller to
 110                  * process the control list.
 111                  */
 112                 sync_after_write(ed, 16);
 113                 sync_after_write(td, 16);
 114                 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed));
 115
 116                 status = read32(OHCI0_HC_CONTROL);
 117                 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 118                 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 119
 120                 /* spin until the controller is done with the control list */
 121                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 122                 while(!current) {
 123                         udelay(10);
 124                         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 125                 }
 126
 127                 printf("current: 0x%08X\n", current);
 128
 129                 /* restore the old control head and control settings */
 130                 write32(OHCI0_HC_CONTROL, status);
 131                 write32(OHCI0_HC_CTRL_HEAD_ED, head);
 132         } else {
 133                 printf("nohead!\n");
 134         }
 135 }
 136
 137
 138 static void dbg_op_state()
 139 {
 140         switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
 141                 case OHCI_USB_SUSPEND:
 142                         printf("ohci-- OHCI_USB_SUSPEND\n");
 143                         break;
 144                 case OHCI_USB_RESET:
 145                         printf("ohci-- OHCI_USB_RESET\n");
 146                         break;
 147                 case OHCI_USB_OPER:
 148                         printf("ohci-- OHCI_USB_OPER\n");
 149                         break;
 150                 case OHCI_USB_RESUME:
 151                         printf("ohci-- OHCI_USB_RESUME\n");
 152                         break;
 153         }
 154 }
 155
 156 static void dbg_td_flag(u32 flag)
 157 {
 158         printf("**************** dbg_td_flag: 0x%08X ***************\n", flag);
 159         printf("CC: %X\tshould be 0, see page 32 (ohci spec)\n", (flag>>28)&0xf);
 160         printf("EC: %X\tsee page 20 (ohci spec)\n", (flag>>26)&3);
 161         printf(" T: %X\n", (flag>>24)&3);
 162         printf("DI: %X\n", (flag>>21)&7);
 163         printf("DP: %X\n", (flag>>19)&3);
 164         printf(" R: %X\n", (flag>>18)&1);
 165         printf("********************************************************\n");
 166 }
 167
 168 static void general_td_fill(struct general_td *dest, const usb_transfer_descriptor *src)
 169 {
 170         if(src->actlen) {
 171                 dest->cbp = LE(virt_to_phys(src->buffer));
 172                 dest->be = LE(LE(dest->cbp) + src->actlen - 1);
 173                 /* save virtual address here */
 174                 dest->bufaddr = (u32) src->buffer;
 175         }
 176         else {
 177                 dest->cbp = dest->be = LE(0);
 178                 dest->bufaddr = 0;
 179         }
 180
 181         dest->buflen = src->actlen;
 182
 183         dest->flags &= LE(~OHCI_TD_DIRECTION_PID_MASK);
 184         switch(src->pid) {
 185                 case USB_PID_SETUP:
 186                         printf("pid_setup\n");
 187                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_SETUP);
 188                         dest->flags |= LE(OHCI_TD_TOGGLE_0);
 189                         dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 190                         break;
 191                 case USB_PID_OUT:
 192                         printf("pid_out\n");
 193                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_OUT);
 194                         dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 195
 196                         /*
 197                          * TODO: just temporary solution! (consider it with len?)
 198                          * there can be also regular PID_OUT pakets
 199                          */
 200                         dest->flags |= LE(OHCI_TD_TOGGLE_1);
 201                         break;
 202                 case USB_PID_IN:
 203                         printf("pid_in\n");
 204                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_IN);
 205                         if(src->maxp > src->actlen) {
 206                                 printf("round buffer!");
 207                                 dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 208                         }
 209                         /*
 210                          * let the endpoint do the togglestuff!
 211                          * TODO: just temporary solution!
 212                          * there can be also inregular PID_IN pakets (@Status Stage)
 213                          */
 214                         dest->flags |= LE(OHCI_TD_TOGGLE_CARRY);
 215 #if 0
 216                         /* should be done by HC!
 217                          * first pid_in start with DATA0 */
 218                          */
 219                         dummyconfig.headp = LE( src->togl ?
 220                                         LE(dummyconfig.headp) | OHCI_ENDPOINT_TOGGLE_CARRY :
 221                                         LE(dummyconfig.headp) & ~OHCI_ENDPOINT_TOGGLE_CARRY);
 222 #endif
 223                         break;
 224         }
 225         dest->flags |= LE(OHCI_TD_SET_DELAY_INTERRUPT(7));
 226 }
 227
 228 static void dump_address(void *addr, u32 size, const char* str)
 229 {
 230         printf("%s hexdump (%d) @ 0x%08X:\n", str, size, addr);
 231         hexdump(addr, size);
 232 }
 233
 234 static struct endpoint_descriptor _edhead;
 235 struct endpoint_descriptor *edhead = 0;
 236 void hcdi_fire()
 237 {
 238         printf("<^>  <^>  <^> hcdi_fire(start)\n");
 239
 240         if(edhead == 0)
 241                 return;
 242
 243         control_quirk(); //required? YES! :O ... erm... or no? :/ ... in fact I have no idea
 244         write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(edhead));
 245
 246         /* sync it all */
 247         sync_after_write(edhead, sizeof(struct endpoint_descriptor));
 248         dump_address(edhead, sizeof(struct endpoint_descriptor), "edhead(before)");
 249
 250         struct general_td *x = phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
 251         printf("STRUCT LEN: %d\n", sizeof(struct general_td));
 252         while(virt_to_phys(x)) {
 253                 sync_after_write(x, sizeof(struct general_td));
 254                 dump_address(x, sizeof(struct general_td), "x(before)");
 255
 256                 if(x->buflen > 0) {
 257                         sync_after_write((void*) phys_to_virt(LE(x->cbp)), x->buflen);
 258                         dump_address((void*) phys_to_virt(LE(x->cbp)), x->buflen, "x->cbp(before)");
 259                 }
 260                 x = phys_to_virt(LE(x->nexttd));
 261         }
 262
 263         /* trigger control list */
 264         set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 265         write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 266
 267         struct general_td *n=0, *prev = 0, *next = 0;
 268         /* poll until edhead->headp is null */
 269         do {
 270                 sync_before_read(edhead, sizeof(struct endpoint_descriptor));
 271                 printf("edhead->headp: 0x%08X\n", LE(edhead->headp));
 272
 273                 /* if halted, debug output plz. will break the transfer */
 274                 if((LE(edhead->headp) & OHCI_ENDPOINT_HALTED)) {
 275                         n = phys_to_virt(LE(edhead->headp)&~0xf);
 276                         prev = phys_to_virt((u32)prev);
 277                         printf("halted!\n");
 278
 279                         sync_before_read((void*) n, sizeof(struct general_td));
 280                         printf("n: 0x%08X\n", n);
 281                         dump_address(n, sizeof(struct general_td), "n(after)");
 282                         if(n->buflen > 0) {
 283                                 sync_before_read((void*) n->bufaddr, n->buflen);
 284                                 dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
 285                         }
 286                         dbg_td_flag(LE(n->flags));
 287
 288                         sync_before_read((void*) prev, sizeof(struct general_td));
 289                         printf("prev: 0x%08X\n", prev);
 290                         dump_address(prev, sizeof(struct general_td), "prev(after)");
 291                         if(prev->buflen >0) {
 292                                 sync_before_read((void*) prev->bufaddr, prev->buflen);
 293                                 dump_address((void*) prev->bufaddr, prev->buflen, "prev->bufaddr(after)");
 294                         }
 295                         dbg_td_flag(LE(prev->flags));
 296
 297                         printf("halted end!\n");
 298                         return;
 299                 }
 300                 prev = (struct general_td*) (LE(edhead->headp)&~0xf);
 301         } while(LE(edhead->headp)&~0xf);
 302
 303         n = phys_to_virt(read32(OHCI0_HC_DONE_HEAD) & ~1);
 304         printf("hc_done_head: 0x%08X\n", read32(OHCI0_HC_DONE_HEAD));
 305
 306         prev = 0; next = 0;
 307         /* reverse done queue */
 308         while(virt_to_phys(n) && edhead->tdcount) {
 309                 sync_before_read((void*) n, sizeof(struct general_td));
 310                 printf("n: 0x%08X\n", n);
 311                 printf("next: 0x%08X\n", next);
 312                 printf("prev: 0x%08X\n", prev);
 313
 314                 next = n;
 315                 n = (struct general_td*) phys_to_virt(LE(n->nexttd));
 316                 next->nexttd = (u32) prev;
 317                 prev = next;
 318
 319                 edhead->tdcount--;
 320         }
 321
 322         n = next;
 323         prev = 0;
 324         while(virt_to_phys(n)) {
 325                 dump_address(n, sizeof(struct general_td), "n(after)");
 326
 327                 if(n->buflen > 0) {
 328                         sync_before_read((void*) n->bufaddr, n->buflen);
 329                         dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
 330                 }
 331                 dbg_td_flag(LE(n->flags));
 332                 prev = n;
 333                 n = (struct general_td*) n->nexttd;
 334                 free(prev);
 335         }
 336
 337         hcca_oh0.done_head = 0;
 338         sync_after_write(&hcca_oh0, sizeof(hcca_oh0));
 339
 340         write32(OHCI0_HC_CONTROL, read32(OHCI0_HC_CONTROL)&~OHCI_CTRL_CLE);
 341
 342         edhead = 0;
 343
 344         printf("<^>  <^>  <^> hcdi_fire(end)\n");
 345 }
 346
 347 /**
 348  * Enqueue a transfer descriptor.
 349  */
 350 u8 hcdi_enqueue(const usb_transfer_descriptor *td) {
 351         printf("*()*()*()*()*()*()*() hcdi_enqueue(start)\n");
 352         if(!edhead) {
 353                 edhead = &_edhead;
 354                 memset(edhead, 0, sizeof(struct endpoint_descriptor));
 355                 edhead->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
 356                 edhead->headp = edhead->tailp = edhead->nexted = LE(0);
 357                 edhead->flags |= LE(OHCI_ENDPOINT_LOW_SPEED |
 358                                 OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
 359                                 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
 360                                 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
 361                 edhead->tdcount = 0;
 362         }
 363
 364         struct general_td *tdhw = allocate_general_td();
 365         general_td_fill(tdhw, td);
 366         edhead->tdcount ++;
 367
 368         if(!edhead->headp) {
 369                 /* first transfer */
 370                 edhead->headp = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
 371         }
 372         else {
 373                 /* headp in endpoint already exists
 374                  * => go to list end
 375                  */
 376                 struct general_td *n = (struct general_td*) phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
 377                 while(LE(n->nexttd)) {
 378                         n = phys_to_virt(LE(n->nexttd));
 379                 }
 380                 n->nexttd = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
 381                 printf("n: 0x%08X\n", n);
 382                 printf("n->nexttd: 0x%08X\n", phys_to_virt(LE(n->nexttd)));
 383         }
 384
 385         printf("*()*()*()*()*()*()*() hcdi_enqueue(end)\n");
 386         return 0;
 387 }
 388
 389
 390 /**
 391  * Remove an transfer descriptor from transfer queue.
 392  */
 393 u8 hcdi_dequeue(usb_transfer_descriptor *td) {
 394         return 0;
 395 }
 396
 397 void hcdi_init()
 398 {
 399         printf("ohci-- init\n");
 400         dbg_op_state();
 401
 402         /* disable hc interrupts */
 403         set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
 404
 405         /* save fmInterval and calculate FSMPS */
 406 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
 407 #define FI 0x2edf /* 12000 bits per frame (-1) */
 408         u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
 409         if(fmint != FI)
 410                 printf("ohci-- fminterval delta: %d\n", fmint - FI);
 411         fmint |= FSMP (fmint) << 16;
 412
 413         /* enable interrupts of both usb host controllers */
 414         set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
 415
 416         /* reset HC */
 417         write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
 418
 419         /* wait max. 30us */
 420         u32 ts = 30;
 421         while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
 422                  if(--ts == 0) {
 423                         printf("ohci-- FAILED");
 424                         return;
 425                  }
 426                  udelay(1);
 427         }
 428
 429         /* disable interrupts; 2ms timelimit here!
 430            now we're in the SUSPEND state ... must go OPERATIONAL
 431            within 2msec else HC enters RESUME */
 432
 433         u32 cookie = irq_kill();
 434
 435         /* Tell the controller where the control and bulk lists are
 436          * The lists are empty now. */
 437         write32(OHCI0_HC_CTRL_HEAD_ED, 0);
 438         write32(OHCI0_HC_BULK_HEAD_ED, 0);
 439
 440         /* set hcca adress */
 441         sync_after_write(&hcca_oh0, 256);
 442         write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
 443
 444         /* set periodicstart */
 445 #define FIT (1<<31)
 446         u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
 447         u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
 448
 449         write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
 450         write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
 451
 452         /* testing bla */
 453         if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
 454                 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
 455         }
 456
 457         /* start HC operations */
 458         write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
 459
 460         /* wake on ConnectStatusChange, matching external hubs */
 461         write32(OHCI0_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC);
 462
 463         /* Choose the interrupts we care about now, others later on demand */
 464         write32(OHCI0_HC_INT_STATUS, ~0);
 465         write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
 466
 467         //wtf?
 468         wait_ms ((read32(OHCI0_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe);
 469
 470         configure_ports((u8)1);
 471         irq_restore(cookie);
 472
 473         dbg_op_state();
 474 }
 475
 476 static void configure_ports(u8 from_init)
 477 {
 478         printf("OHCI0_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_A));
 479         printf("OHCI0_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_B));
 480         printf("OHCI0_HC_RH_STATUS:\t\t0x%08X\n", read32(OHCI0_HC_RH_STATUS));
 481         printf("OHCI0_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_1));
 482         printf("OHCI0_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_2));
 483
 484         setup_port(OHCI0_HC_RH_PORT_STATUS_1, from_init);
 485         setup_port(OHCI0_HC_RH_PORT_STATUS_2, from_init);
 486         printf("configure_ports done\n");
 487 }
 488
 489 static void setup_port(u32 reg, u8 from_init)
 490 {
 491         u32 port = read32(reg);
 492         if((port & RH_PS_CCS) && ((port & RH_PS_CSC) || from_init)) {
 493                 write32(reg, RH_PS_CSC);
 494
 495                 wait_ms(120);
 496
 497                 /* clear CSC flag, set PES and start port reset (PRS) */
 498                 write32(reg, RH_PS_PES);
 499                 while(!(read32(reg) & RH_PS_PES)) {
 500                         printf("fu\n");
 501                         return;
 502                 }
 503
 504                 write32(reg, RH_PS_PRS);
 505
 506                 /* spin until port reset is complete */
 507                 while(!(read32(reg) & RH_PS_PRSC)); // hint: it may stuck here
 508                 printf("loop done\n");
 509
 510                 (void) usb_add_device();
 511         }
 512 }
 513
 514 void hcdi_irq()
 515 {
 516         /* read interrupt status */
 517         u32 flags = read32(OHCI0_HC_INT_STATUS);
 518
 519         /* when all bits are set to 1 some problem occured */
 520         if (flags == 0xffffffff) {
 521                 printf("ohci-- Houston, we have a serious problem! :(\n");
 522                 return;
 523         }
 524
 525         /* only care about interrupts that are enabled */
 526         flags &= read32(OHCI0_HC_INT_ENABLE);
 527
 528         /* nothing to do? */
 529         if (flags == 0) {
 530                 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
 531                 return;
 532         }
 533
 534         printf("OHCI Interrupt occured: ");
 535         /* UnrecoverableError */
 536         if (flags & OHCI_INTR_UE) {
 537                 printf("UnrecoverableError\n");
 538                 /* TODO: well, I don't know... nothing,
 539                  *       because it won't happen anyway? ;-) */
 540         }
 541
 542         /* RootHubStatusChange */
 543         if (flags & OHCI_INTR_RHSC) {
 544                 printf("RootHubStatusChange\n");
 545                 /* TODO: set some next_statechange variable... */
 546                 configure_ports(0);
 547                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
 548         }
 549         /* ResumeDetected */
 550         else if (flags & OHCI_INTR_RD) {
 551                 printf("ResumeDetected\n");
 552                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
 553                 /* TODO: figure out what the linux kernel does here... */
 554         }
 555
 556         /* WritebackDoneHead */
 557         if (flags & OHCI_INTR_WDH) {
 558                 printf("WritebackDoneHead\n");
 559                 /* basically the linux irq handler reverse TDs to their urbs
 560                  * and set done_head to null.
 561                  * since we are polling atm, just should do the latter task.
 562                  * however, this won't work for now (i don't know why...)
 563                  * TODO!
 564                  */
 565 #if 0
 566                 sync_before_read(&hcca_oh0, 256);
 567                 hcca_oh0.done_head = 0;
 568                 sync_after_write(&hcca_oh0, 256);
 569 #endif
 570         }
 571
 572         /* TODO: handle any pending URB/ED unlinks... */
 573
 574 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
 575         if (HC_IS_RUNNING()) {
 576                 write32(OHCI0_HC_INT_STATUS, flags);
 577                 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);
 578         }
 579 }
 580
 581 void show_frame_no()
 582 {
 583         sync_before_read(&hcca_oh0, 256);
 584         printf("***** frame_no: %d *****\n", LE(hcca_oh0.frame_no));
 585 }