usb/host/ohci.c

   1 /*
   2        ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
   3        ohci hardware support
   4
   5 Copyright (C) 2009     Bernhard Urban <lewurm@gmx.net>
   6 Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
   7
   8 # This code is licensed to you under the terms of the GNU GPL, version 2;
   9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
  10 */
  11
  12 #include "../../bootmii_ppc.h"
  13 #include "../../hollywood.h"
  14 #include "../../irq.h"
  15 #include "../../string.h"
  16 #include "../../malloc.h"
  17 #include "ohci.h"
  18 #include "host.h"
  19 #include "../usbspec/usb11spec.h"
  20
  21 /* activate control_quirk */
  22 #define _USE_C_Q
  23
  24 /* macro for accessing u32 variables that need to be in little endian byte order;
  25  *
  26  * whenever you read or write from an u32 field that the ohci host controller
  27  * will read or write from too, use this macro for access!
  28  */
  29 #define LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
  30                            (((dword) & 0x00FF0000) >> 8)  | \
  31                            (((dword) & 0x0000FF00) << 8)  | \
  32                            (((dword) & 0x000000FF) << 24) )
  33
  34 static struct general_td *allocate_general_td();
  35 static void dbg_op_state(u32 reg);
  36 static void configure_ports(u8 from_init, u32 reg);
  37 static void setup_port(u32 ohci, u32 reg, u8 from_init);
  38 static void set_target_hcca(u32 reg);
  39
  40 static struct ohci_hcca hcca_oh0;
  41 static struct ohci_hcca hcca_oh1;
  42 struct ohci_hcca *hcca;
  43
  44 static struct general_td *allocate_general_td()
  45 {
  46         struct general_td *td;
  47         td = (struct general_td *)memalign(16, sizeof(struct general_td));
  48         memset(td, 0, sizeof(struct general_td));
  49         td->flags = LE(0);
  50         td->nexttd = LE(0);
  51         td->cbp = td->be = LE(0);
  52         return td;
  53 }
  54
  55
  56 static void dbg_op_state(u32 reg)
  57 {
  58         switch (read32(reg+OHCI_HC_CONTROL) & OHCI_CTRL_HCFS) {
  59                 case OHCI_USB_SUSPEND:
  60                         printf("ohci-- OHCI_USB_SUSPEND\n");
  61                         break;
  62                 case OHCI_USB_RESET:
  63                         printf("ohci-- OHCI_USB_RESET\n");
  64                         break;
  65                 case OHCI_USB_OPER:
  66                         printf("ohci-- OHCI_USB_OPER\n");
  67                         break;
  68                 case OHCI_USB_RESUME:
  69                         printf("ohci-- OHCI_USB_RESUME\n");
  70                         break;
  71         }
  72 }
  73
  74 #ifdef _DU_OHCI_F_HALT
  75 static void dbg_td_flag(u32 flag)
  76 {
  77         printf("**************** dbg_td_flag: 0x%08X ***************\n", flag);
  78         printf("CC: %X\tshould be 0, see page 32 (ohci spec)\n", (flag>>28)&0xf);
  79         printf("EC: %X\tsee page 20 (ohci spec)\n", (flag>>26)&3);
  80         printf(" T: %X\n", (flag>>24)&3);
  81         printf("DI: %X\n", (flag>>21)&7);
  82         printf("DP: %X\n", (flag>>19)&3);
  83         printf(" R: %X\n", (flag>>18)&1);
  84         printf("********************************************************\n");
  85 }
  86 #endif
  87
  88 static void general_td_fill(struct general_td *dest, const struct usb_transfer_descriptor *src)
  89 {
  90         if(src->actlen) {
  91                 dest->cbp = LE(virt_to_phys(src->buffer));
  92                 dest->be = LE(LE(dest->cbp) + src->actlen - 1);
  93                 /* save virtual address here */
  94                 dest->bufaddr = (u32) src->buffer;
  95         }
  96         else {
  97                 dest->cbp = dest->be = LE(0);
  98                 dest->bufaddr = 0;
  99         }
 100
 101         dest->buflen = src->actlen;
 102
 103         dest->flags &= LE(~OHCI_TD_DIRECTION_PID_MASK);
 104         switch(src->pid) {
 105                 case USB_PID_SETUP:
 106 #ifdef _DU_OHCI_Q
 107                         printf("pid_setup\n");
 108 #endif
 109                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_SETUP);
 110                         dest->flags |= LE(OHCI_TD_TOGGLE_0);
 111                         dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 112                         break;
 113                 case USB_PID_OUT:
 114 #ifdef _DU_OHCI_Q
 115                         printf("pid_out\n");
 116 #endif
 117                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_OUT);
 118                         dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 119
 120                         dest->flags |= src->togl ? LE(OHCI_TD_TOGGLE_1) : LE(OHCI_TD_TOGGLE_0);
 121                         break;
 122                 case USB_PID_IN:
 123 #ifdef _DU_OHCI_Q
 124                         printf("pid_in\n");
 125 #endif
 126                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_IN);
 127                         if(src->maxp > src->actlen) {
 128                                 dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 129 #ifdef _DU_OHCI_Q
 130                                 printf("round buffer!\n");
 131 #endif
 132                         }
 133                         dest->flags |= src->togl ? LE(OHCI_TD_TOGGLE_1) : LE(OHCI_TD_TOGGLE_0);
 134                         break;
 135         }
 136         dest->flags |= LE(OHCI_TD_SET_DELAY_INTERRUPT(7));
 137 }
 138
 139 #ifdef _DU_OHCI_F_HALT
 140 static void dump_address(void *addr, u32 size, const char* str)
 141 {
 142         printf("%s hexdump (%d) @ 0x%08X:\n", str, size, addr);
 143         hexdump(addr, size);
 144 }
 145 #endif
 146
 147 static struct endpoint_descriptor _edhead;
 148 struct endpoint_descriptor *edhead = 0;
 149 void hcdi_fire(u32 reg)
 150 {
 151 #ifdef _DU_OHCI_F
 152         printf("<^>  <^>  <^> hcdi_fire(start)\n");
 153 #endif
 154
 155         if(edhead == 0)
 156                 return;
 157
 158 #ifdef _USE_C_Q
 159         /* quirk... 11ms seems to be a minimum :O */
 160         udelay(11000);
 161 #endif
 162
 163         write32(reg+OHCI_HC_CTRL_HEAD_ED, virt_to_phys(edhead));
 164
 165         /* sync it all */
 166         sync_after_write(edhead, sizeof(struct endpoint_descriptor));
 167 #ifdef _DU_OHCI_F
 168         dump_address(edhead, sizeof(struct endpoint_descriptor), "edhead(before)");
 169 #endif
 170
 171         struct general_td *x = phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
 172         while(virt_to_phys(x)) {
 173                 sync_after_write(x, sizeof(struct general_td));
 174 #ifdef _DU_OHCI_F
 175                 dump_address(x, sizeof(struct general_td), "x(before)");
 176 #endif
 177
 178                 if(x->buflen > 0) {
 179                         sync_after_write((void*) phys_to_virt(LE(x->cbp)), x->buflen);
 180 #ifdef _DU_OHCI_F
 181                         dump_address((void*) phys_to_virt(LE(x->cbp)), x->buflen, "x->cbp(before)");
 182 #endif
 183                 }
 184                 x = phys_to_virt(LE(x->nexttd));
 185         }
 186
 187         /* trigger control list */
 188         set32(reg+OHCI_HC_CONTROL, OHCI_CTRL_CLE);
 189         write32(reg+OHCI_HC_COMMAND_STATUS, OHCI_CLF);
 190
 191         struct general_td *n=0, *prev = 0, *next = 0;
 192         /* poll until edhead->headp is null */
 193         do {
 194                 sync_before_read(edhead, sizeof(struct endpoint_descriptor));
 195 #ifdef _DU_OHCI_F
 196                 printf("edhead->headp: 0x%08X\n", LE(edhead->headp));
 197 #endif
 198
 199                 /* if halted, debug output plz. will break the transfer */
 200                 if((LE(edhead->headp) & OHCI_ENDPOINT_HALTED)) {
 201                         n = phys_to_virt(LE(edhead->headp)&~0xf);
 202                         prev = phys_to_virt((u32)prev);
 203 #ifdef _DU_OHCI_F_HALT
 204                         printf("halted!\n");
 205 #endif
 206
 207                         sync_before_read((void*) n, sizeof(struct general_td));
 208 #ifdef _DU_OHCI_F_HALT
 209                         printf("n: 0x%08X\n", n);
 210                         dump_address(n, sizeof(struct general_td), "n(after)");
 211 #endif
 212                         if(n->buflen > 0) {
 213                                 sync_before_read((void*) n->bufaddr, n->buflen);
 214 #ifdef _DU_OHCI_F_HALT
 215                                 dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
 216 #endif
 217                         }
 218 #ifdef _DU_OHCI_F_HALT
 219                         dbg_td_flag(LE(n->flags));
 220 #endif
 221
 222                         sync_before_read((void*) prev, sizeof(struct general_td));
 223 #ifdef _DU_OHCI_F_HALT
 224                         printf("prev: 0x%08X\n", prev);
 225                         dump_address(prev, sizeof(struct general_td), "prev(after)");
 226 #endif
 227                         if(prev->buflen >0) {
 228                                 sync_before_read((void*) prev->bufaddr, prev->buflen);
 229 #ifdef _DU_OHCI_F_HALT
 230                                 dump_address((void*) prev->bufaddr, prev->buflen, "prev->bufaddr(after)");
 231 #endif
 232                         }
 233 #ifdef _DU_OHCI_F_HALT
 234                         dbg_td_flag(LE(prev->flags));
 235                         printf("halted end!\n");
 236 #endif
 237                         goto out;
 238                 }
 239                 prev = (struct general_td*) (LE(edhead->headp)&~0xf);
 240         } while(LE(edhead->headp)&~0xf);
 241
 242         n = phys_to_virt(read32(reg+OHCI_HC_DONE_HEAD) & ~1);
 243 #ifdef _DU_OHCI_F
 244         printf("hc_done_head: 0x%08X\n", read32(reg+OHCI_HC_DONE_HEAD));
 245 #endif
 246
 247         prev = 0; next = 0;
 248         /* reverse done queue */
 249         while(virt_to_phys(n) && edhead->tdcount) {
 250                 sync_before_read((void*) n, sizeof(struct general_td));
 251 #ifdef _DU_OHCI_F
 252                 printf("n: 0x%08X\n", n);
 253                 printf("next: 0x%08X\n", next);
 254                 printf("prev: 0x%08X\n", prev);
 255 #endif
 256
 257                 next = n;
 258                 n = (struct general_td*) phys_to_virt(LE(n->nexttd));
 259                 next->nexttd = (u32) prev;
 260                 prev = next;
 261
 262                 edhead->tdcount--;
 263         }
 264
 265         n = next;
 266         prev = 0;
 267         while(virt_to_phys(n)) {
 268 #ifdef _DU_OHCI_F
 269                 dump_address(n, sizeof(struct general_td), "n(after)");
 270 #endif
 271                 if(n->buflen > 0) {
 272                         sync_before_read((void*) n->bufaddr, n->buflen);
 273 #ifdef _DU_OHCI_F
 274                         dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
 275 #endif
 276                 }
 277 #ifdef _DU_OHCI_F
 278                 dbg_td_flag(LE(n->flags));
 279 #endif
 280                 prev = n;
 281                 n = (struct general_td*) n->nexttd;
 282                 free(prev);
 283         }
 284
 285         set_target_hcca(reg);
 286         hcca->done_head = 0;
 287         sync_after_write(hcca, sizeof(*hcca));
 288
 289 out:
 290         write32(reg+OHCI_HC_CONTROL, read32(reg+OHCI_HC_CONTROL)&~OHCI_CTRL_CLE);
 291
 292         edhead = 0;
 293
 294 #ifdef _DU_OHCI_F
 295         printf("<^>  <^>  <^> hcdi_fire(end)\n");
 296 #endif
 297 }
 298
 299 /**
 300  * Enqueue a transfer descriptor.
 301  */
 302 u8 hcdi_enqueue(const struct usb_transfer_descriptor *td, u32 reg) {
 303 #ifdef _DU_OHCI_Q
 304         printf("*()*()*()*()*()*()*() hcdi_enqueue(start)\n");
 305 #endif
 306         if(!edhead) {
 307                 edhead = &_edhead;
 308                 memset(edhead, 0, sizeof(struct endpoint_descriptor));
 309                 edhead->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
 310                 edhead->headp = edhead->tailp = edhead->nexted = LE(0);
 311                 if(td->fullspeed) {
 312                         edhead->flags |= LE(OHCI_ENDPOINT_FULL_SPEED);
 313                 } else {
 314                         edhead->flags |= LE(OHCI_ENDPOINT_LOW_SPEED);
 315                 }
 316                 edhead->flags |= LE(OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
 317                                 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
 318                                 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
 319                 edhead->tdcount = 0;
 320         }
 321
 322         struct general_td *tdhw = allocate_general_td();
 323         general_td_fill(tdhw, td);
 324         edhead->tdcount ++;
 325
 326         if(!edhead->headp) {
 327                 /* first transfer */
 328                 edhead->headp = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
 329         }
 330         else {
 331                 /* headp in endpoint already exists
 332                  * => go to list end
 333                  */
 334                 struct general_td *n = (struct general_td*) phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
 335                 while(LE(n->nexttd)) {
 336                         n = phys_to_virt(LE(n->nexttd));
 337                 }
 338                 n->nexttd = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
 339 #ifdef _DU_OHCI_Q
 340                 printf("n: 0x%08X\n", n);
 341                 printf("n->nexttd: 0x%08X\n", phys_to_virt(LE(n->nexttd)));
 342 #endif
 343         }
 344
 345 #ifdef _DU_OHCI_Q
 346         printf("*()*()*()*()*()*()*() hcdi_enqueue(end)\n");
 347 #endif
 348         return 0;
 349 }
 350
 351
 352 /**
 353  * Remove an transfer descriptor from transfer queue.
 354  */
 355 u8 hcdi_dequeue(struct usb_transfer_descriptor *td, u32 reg) {
 356         return 0;
 357 }
 358
 359 void hcdi_init(u32 reg)
 360 {
 361         printf("ohci-- init\n");
 362         dbg_op_state(reg);
 363
 364         /* disable hc interrupts */
 365         set32(reg+OHCI_HC_INT_DISABLE, OHCI_INTR_MIE);
 366
 367         /* save fmInterval and calculate FSMPS */
 368 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
 369 #define FI 0x2edf /* 12000 bits per frame (-1) */
 370         u32 fmint = read32(reg+OHCI_HC_FM_INTERVAL) & 0x3fff;
 371         if(fmint != FI)
 372                 printf("ohci-- fminterval delta: %d\n", fmint - FI);
 373         fmint |= FSMP (fmint) << 16;
 374
 375         /* enable interrupts of both usb host controllers */
 376         set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
 377
 378         /* reset HC */
 379         write32(reg+OHCI_HC_COMMAND_STATUS, OHCI_HCR);
 380
 381         /* wait max. 30us */
 382         u32 ts = 30;
 383         while ((read32(reg+OHCI_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
 384                  if(--ts == 0) {
 385                         printf("ohci-- FAILED");
 386                         return;
 387                  }
 388                  udelay(1);
 389         }
 390
 391         /* disable interrupts; 2ms timelimit here!
 392            now we're in the SUSPEND state ... must go OPERATIONAL
 393            within 2msec else HC enters RESUME */
 394
 395         u32 cookie = irq_kill();
 396
 397         /* Tell the controller where the control and bulk lists are
 398          * The lists are empty now. */
 399         write32(reg+OHCI_HC_CTRL_HEAD_ED, 0);
 400         write32(reg+OHCI_HC_BULK_HEAD_ED, 0);
 401
 402         /* set hcca adress */
 403         set_target_hcca(reg);
 404         sync_after_write(hcca, 256);
 405         write32(reg+OHCI_HC_HCCA, virt_to_phys(hcca));
 406
 407         /* set periodicstart */
 408 #define FIT (1<<31)
 409         u32 fmInterval = read32(reg+OHCI_HC_FM_INTERVAL) &0x3fff;
 410         u32 fit = read32(reg+OHCI_HC_FM_INTERVAL) & FIT;
 411
 412         write32(reg+OHCI_HC_FM_INTERVAL, fmint | (fit ^ FIT));
 413         write32(reg+OHCI_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
 414
 415         /* testing bla */
 416         if ((read32(reg+OHCI_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(reg+OHCI_HC_PERIODIC_START)) {
 417                 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
 418         }
 419
 420         /* start HC operations */
 421         write32(reg+OHCI_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
 422
 423         /* wake on ConnectStatusChange, matching external hubs */
 424         write32(reg+OHCI_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC);
 425
 426         /* Choose the interrupts we care about now, others later on demand */
 427         write32(reg+OHCI_HC_INT_STATUS, ~0);
 428         write32(reg+OHCI_HC_INT_ENABLE, OHCI_INTR_INIT);
 429
 430         //wtf?
 431         wait_ms ((read32(reg+OHCI_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe);
 432
 433         configure_ports((u8)1, reg);
 434         irq_restore(cookie);
 435
 436         dbg_op_state(reg);
 437 }
 438
 439 static void configure_ports(u8 from_init, u32 reg)
 440 {
 441 #ifdef _DU_OHCI_RH
 442         printf("=== Roothub @ %s ===\n", reg == OHCI0_REG_BASE ? "OHCI0" : "OHCI1");
 443         printf("OHCI_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(reg+OHCI_HC_RH_DESCRIPTOR_A));
 444         printf("OHCI_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(reg+OHCI_HC_RH_DESCRIPTOR_B));
 445         printf("OHCI_HC_RH_STATUS:\t\t0x%08X\n", read32(reg+OHCI_HC_RH_STATUS));
 446         printf("OHCI_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(reg+OHCI_HC_RH_PORT_STATUS_1));
 447         printf("OHCI_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(reg+OHCI_HC_RH_PORT_STATUS_2));
 448 #endif
 449
 450         setup_port(reg, reg+OHCI_HC_RH_PORT_STATUS_1, from_init);
 451         setup_port(reg, reg+OHCI_HC_RH_PORT_STATUS_2, from_init);
 452 #ifdef _DU_OHCI_RH
 453         printf("configure_ports done\n");
 454 #endif
 455 }
 456
 457 static void setup_port(u32 ohci, u32 reg, u8 from_init)
 458 {
 459         u32 port = read32(reg);
 460         if((port & RH_PS_CCS) && ((port & RH_PS_CSC) || from_init)) {
 461                 write32(reg, RH_PS_CSC);
 462
 463                 wait_ms(120);
 464
 465                 /* clear CSC flag, set PES and start port reset (PRS) */
 466                 write32(reg, RH_PS_PES);
 467                 while(!(read32(reg) & RH_PS_PES)) {
 468 #ifdef _DU_OHCI_RH
 469                         printf("fu\n");
 470 #endif
 471                         return;
 472                 }
 473
 474                 write32(reg, RH_PS_PRS);
 475
 476                 /* spin until port reset is complete */
 477                 while(!(read32(reg) & RH_PS_PRSC)); // hint: it may stuck here
 478 #ifdef _DU_OHCI_RH
 479                 printf("loop done\n");
 480 #endif
 481
 482                 /* returns usb_device struct */
 483                 (void) usb_add_device((read32(reg) & RH_PS_LSDA) >> 8, ohci);
 484         }
 485 }
 486
 487 void hcdi_irq(u32 reg)
 488 {
 489         /* read interrupt status */
 490         u32 flags = read32(reg+OHCI_HC_INT_STATUS);
 491
 492         /* when all bits are set to 1 some problem occured */
 493         if (flags == 0xffffffff) {
 494                 printf("ohci-- Houston, we have a serious problem! :(\n");
 495                 return;
 496         }
 497
 498         /* only care about interrupts that are enabled */
 499         flags &= read32(reg+OHCI_HC_INT_ENABLE);
 500
 501         /* nothing to do? */
 502         if (flags == 0) {
 503                 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
 504                 return;
 505         }
 506
 507         printf("OHCI Interrupt occured: ");
 508         /* UnrecoverableError */
 509         if (flags & OHCI_INTR_UE) {
 510                 printf("UnrecoverableError\n");
 511                 /* TODO: well, I don't know... nothing,
 512                  *       because it won't happen anyway? ;-) */
 513         }
 514
 515         /* RootHubStatusChange */
 516         if (flags & OHCI_INTR_RHSC) {
 517                 printf("RootHubStatusChange\n");
 518                 /* TODO: set some next_statechange variable... */
 519                 configure_ports(0, reg);
 520                 write32(reg+OHCI_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
 521         }
 522         /* ResumeDetected */
 523         else if (flags & OHCI_INTR_RD) {
 524                 printf("ResumeDetected\n");
 525                 write32(reg+OHCI_HC_INT_STATUS, OHCI_INTR_RD);
 526                 /* TODO: figure out what the linux kernel does here... */
 527         }
 528
 529         /* WritebackDoneHead */
 530         if (flags & OHCI_INTR_WDH) {
 531                 printf("WritebackDoneHead\n");
 532                 /* basically the linux irq handler reverse TDs to their urbs
 533                  * and set done_head to null.
 534                  * since we are polling atm, just should do the latter task.
 535                  * however, this won't work for now (i don't know why...)
 536                  * TODO!
 537                  */
 538 #if 0
 539                 sync_before_read(&hcca_oh0, 256);
 540                 hcca_oh0.done_head = 0;
 541                 sync_after_write(&hcca_oh0, 256);
 542 #endif
 543         }
 544
 545         /* TODO: handle any pending URB/ED unlinks... */
 546
 547 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
 548         if (HC_IS_RUNNING()) {
 549                 write32(reg+OHCI_HC_INT_STATUS, flags);
 550                 write32(reg+OHCI_HC_INT_ENABLE, OHCI_INTR_MIE);
 551         }
 552 }
 553
 554 /* Before you access the HCCA structure in any way, call this to set the pointer correctly! */
 555 static void set_target_hcca(u32 reg)
 556 {
 557         switch(reg) {
 558         case OHCI0_REG_BASE: hcca = &hcca_oh0; break;
 559         case OHCI1_REG_BASE: hcca = &hcca_oh1; break;
 560         }
 561 }
 562
 563 void show_frame_no(u32 reg)
 564 {
 565         set_target_hcca(reg);
 566         sync_before_read(hcca, 256);
 567         printf("***** frame_no: %d *****\n", LE(hcca->frame_no));
 568 }