usb/host/ohci.c

   1 /*
   2        ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
   3        ohci hardware support
   4
   5 Copyright (C) 2009     Bernhard Urban <lewurm@gmx.net>
   6 Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
   7
   8 # This code is licensed to you under the terms of the GNU GPL, version 2;
   9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
  10 */
  11
  12 #include "../../bootmii_ppc.h"
  13 #include "../../hollywood.h"
  14 #include "../../irq.h"
  15 #include "../../string.h"
  16 #include "../../malloc.h"
  17 #include "ohci.h"
  18 #include "host.h"
  19 #include "../usbspec/usb11spec.h"
  20
  21 // macro for accessing u32 variables that need to be in little endian byte order;
  22 // whenever you read or write from an u32 field that the ohci host controller
  23 // will read or write from too, use this macro for access!
  24 #define ACCESS_LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
  25                            (((dword) & 0x00FF0000) >> 8)  | \
  26                            (((dword) & 0x0000FF00) << 8)  | \
  27                            (((dword) & 0x000000FF) << 24) )
  28
  29 static struct endpoint_descriptor *allocate_endpoint();
  30 static struct general_td *allocate_general_td(size_t);
  31 static void control_quirk();
  32 static void dbg_op_state();
  33 static void dbg_td_flag(u32 flag);
  34 static void configure_ports(u8 from_init);
  35 static void setup_port(u32 reg, u8 from_init);
  36
  37 static struct ohci_hcca hcca_oh0;
  38
  39
  40 static struct endpoint_descriptor *allocate_endpoint()
  41 {
  42         struct endpoint_descriptor *ep;
  43         ep = (struct endpoint_descriptor *)memalign(16, sizeof(struct endpoint_descriptor));
  44         ep->flags = ACCESS_LE(OHCI_ENDPOINT_GENERAL_FORMAT);
  45         ep->headp = ep->tailp = ep->nexted = ACCESS_LE(0);
  46         return ep;
  47 }
  48
  49 static struct general_td *allocate_general_td(size_t bsize)
  50 {
  51         struct general_td *td;
  52         td = (struct general_td *)memalign(16, sizeof(struct general_td));
  53         td->flags = ACCESS_LE(0);
  54         td->nexttd = ACCESS_LE(0);
  55         td->cbp = td->be = ACCESS_LE(0);
  56         return td;
  57 }
  58
  59 static void control_quirk()
  60 {
  61         static struct endpoint_descriptor *ed = 0; /* empty ED */
  62         static struct general_td *td = 0; /* dummy TD */
  63         u32 head;
  64         u32 current;
  65         u32 status;
  66
  67         /*
  68          * One time only.
  69          * Allocate and keep a special empty ED with just a dummy TD.
  70          */
  71         if (!ed) {
  72                 ed = allocate_endpoint();
  73                 if (!ed)
  74                         return;
  75
  76                 td = allocate_general_td(0);
  77                 if (!td) {
  78                         free(ed);
  79                         ed = NULL;
  80                         return;
  81                 }
  82
  83 #define ED_MASK ((u32)~0x0f)
  84                 ed->tailp = ed->headp = ACCESS_LE(virt_to_phys((void*) ((u32)td & ED_MASK)));
  85                 ed->flags |= ACCESS_LE(OHCI_ENDPOINT_DIRECTION_OUT);
  86         }
  87
  88         /*
  89          * The OHCI USB host controllers on the Nintendo Wii
  90          * video game console stop working when new TDs are
  91          * added to a scheduled control ED after a transfer has
  92          * has taken place on it.
  93          *
  94          * Before scheduling any new control TD, we make the
  95          * controller happy by always loading a special control ED
  96          * with a single dummy TD and letting the controller attempt
  97          * the transfer.
  98          * The controller won't do anything with it, as the special
  99          * ED has no TDs, but it will keep the controller from failing
 100          * on the next transfer.
 101          */
 102         head = read32(OHCI0_HC_CTRL_HEAD_ED);
 103         if (head) {
 104                 printf("head: 0x%08X\n", head);
 105                 /*
 106                  * Load the special empty ED and tell the controller to
 107                  * process the control list.
 108                  */
 109                 sync_after_write(ed, 16);
 110                 sync_after_write(td, 16);
 111                 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed));
 112
 113                 status = read32(OHCI0_HC_CONTROL);
 114                 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 115                 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 116
 117                 /* spin until the controller is done with the control list */
 118                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 119                 while(!current) {
 120                         udelay(10);
 121                         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 122                 }
 123
 124                 printf("current: 0x%08X\n", current);
 125
 126                 /* restore the old control head and control settings */
 127                 write32(OHCI0_HC_CONTROL, status);
 128                 write32(OHCI0_HC_CTRL_HEAD_ED, head);
 129         } else {
 130                 printf("nohead!\n");
 131         }
 132 }
 133
 134
 135 static void dbg_op_state()
 136 {
 137         switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
 138                 case OHCI_USB_SUSPEND:
 139                         printf("ohci-- OHCI_USB_SUSPEND\n");
 140                         break;
 141                 case OHCI_USB_RESET:
 142                         printf("ohci-- OHCI_USB_RESET\n");
 143                         break;
 144                 case OHCI_USB_OPER:
 145                         printf("ohci-- OHCI_USB_OPER\n");
 146                         break;
 147                 case OHCI_USB_RESUME:
 148                         printf("ohci-- OHCI_USB_RESUME\n");
 149                         break;
 150         }
 151 }
 152
 153 static void dbg_td_flag(u32 flag)
 154 {
 155         printf("**************** dbg_td_flag: 0x%08X ***************\n", flag);
 156         printf("CC: %X\tshould be 0, see page 32 (ohci spec)\n", (flag>>28)&0xf);
 157         printf("EC: %X\tsee page 20 (ohci spec)\n", (flag>>26)&3);
 158         printf(" T: %X\n", (flag>>24)&3);
 159         printf("DI: %X\n", (flag>>21)&7);
 160         printf("DP: %X\n", (flag>>19)&3);
 161         printf(" R: %X\n", (flag>>18)&1);
 162         printf("********************************************************\n");
 163 }
 164
 165 static void general_td_fill(struct general_td *dest, const usb_transfer_descriptor *src)
 166 {
 167         dest->cbp = ACCESS_LE(virt_to_phys(src->buffer));
 168         dest->be = ACCESS_LE(ACCESS_LE(dest->cbp) + src->actlen - 1);
 169         dest->flags &= ACCESS_LE(~OHCI_TD_DIRECTION_PID_MASK);
 170         switch(src->pid) {
 171                 case USB_PID_SETUP:
 172                         printf("pid_setup\n");
 173                         dest->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_SETUP);
 174                         dest->flags |= ACCESS_LE(OHCI_TD_TOGGLE_0);
 175                         dest->flags |= ACCESS_LE(OHCI_TD_BUFFER_ROUNDING);
 176                         break;
 177                 case USB_PID_OUT:
 178                         printf("pid_out\n");
 179                         dest->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_OUT);
 180                         dest->flags |= ACCESS_LE(OHCI_TD_BUFFER_ROUNDING);
 181
 182                         /*
 183                          * TODO: just temporary solution!
 184                          * there can be also regular PID_OUT pakets
 185                          */
 186                         dest->flags |= ACCESS_LE(OHCI_TD_TOGGLE_1);
 187                         break;
 188                 case USB_PID_IN:
 189                         printf("pid_in\n");
 190                         dest->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_IN);
 191                         dest->flags |= ACCESS_LE(OHCI_TD_BUFFER_ROUNDING);
 192                         /*
 193                          * let the endpoint do the togglestuff!
 194                          * TODO: just temporary solution!
 195                          * there can be also inregular PID_IN pakets (@Status Stage)
 196                          */
 197                         dest->flags |= ACCESS_LE(OHCI_TD_TOGGLE_CARRY);
 198 #if 0
 199                         /* should be done by HC!
 200                          * first pid_in start with DATA0 */
 201                          */
 202                         dummyconfig.headp = ACCESS_LE( src->togl ?
 203                                         ACCESS_LE(dummyconfig.headp) | OHCI_ENDPOINT_TOGGLE_CARRY :
 204                                         ACCESS_LE(dummyconfig.headp) & ~OHCI_ENDPOINT_TOGGLE_CARRY);
 205 #endif
 206                         break;
 207         }
 208         dest->flags |= ACCESS_LE(OHCI_TD_SET_DELAY_INTERRUPT(7));
 209         sync_after_write(dest, sizeof(struct general_td));
 210         sync_after_write((void*) phys_to_virt(ACCESS_LE(dest->cbp)), src->actlen);
 211 }
 212
 213 static void dump_address(void *addr, u32 size, const char* str)
 214 {
 215         sync_before_read(addr, size);
 216         printf("%s hexdump @ 0x%08X:\n", str, addr);
 217         hexdump(addr, size);
 218 }
 219
 220 /**
 221  * Enqueue a transfer descriptor.
 222  */
 223 u8 first = 0;
 224 u8 hcdi_enqueue(const usb_transfer_descriptor *td) {
 225         static struct general_td *tSetup,*tData;
 226         static u32 tSetupbuffer, tDatabuffer, tStatusbuffer;
 227         static u32 tSetupblen, tDatablen, tStatusblen;
 228
 229         if(first == 0) {
 230                 printf("step 0\n");
 231                 tSetup = allocate_general_td(td->actlen);
 232                 general_td_fill(tSetup, td);
 233                 tSetupbuffer = (u32) phys_to_virt(ACCESS_LE(tSetup->cbp));
 234                 tSetupblen = td->actlen;
 235                 first++;
 236                 return 0;
 237         }
 238         if(first == 1) {
 239                 printf("step 1\n");
 240                 tData = allocate_general_td(td->actlen);
 241                 general_td_fill(tData, td);
 242                 tDatabuffer = (u32) phys_to_virt(ACCESS_LE(tData->cbp));
 243                 tDatablen = td->actlen;
 244                 first++;
 245                 return 0;
 246         }
 247         first = 0;
 248         struct general_td *tStatus = allocate_general_td(td->actlen);
 249         general_td_fill(tStatus, td);
 250         tStatusbuffer = (u32) phys_to_virt(ACCESS_LE(tStatus->cbp));
 251         tStatusblen = td->actlen;
 252
 253         printf( "===========================\n"
 254                         "===========================\n");
 255         control_quirk(); //required? YES! :O ... erm... or no? :/ ... in fact I have no idea
 256
 257         struct endpoint_descriptor *dummyconfig = allocate_endpoint();
 258         dummyconfig->flags = ACCESS_LE(OHCI_ENDPOINT_GENERAL_FORMAT);
 259         dummyconfig->headp = dummyconfig->tailp = dummyconfig->nexted = ACCESS_LE(0);
 260         dummyconfig->flags |= ACCESS_LE(OHCI_ENDPOINT_LOW_SPEED |
 261                         OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
 262                         OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
 263                         OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
 264         write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(dummyconfig));
 265
 266 #define ED_MASK ((u32)~0x0f)
 267         dummyconfig->headp |= ACCESS_LE(virt_to_phys((void*) ((u32)tSetup & ED_MASK)));
 268         tSetup->nexttd = ACCESS_LE(virt_to_phys((void*) ((u32)tData & ED_MASK)));
 269         tData->nexttd = ACCESS_LE(virt_to_phys((void*) ((u32)tStatus & ED_MASK)));
 270
 271         sync_after_write(dummyconfig, 16);
 272         sync_after_write(tSetup, sizeof(struct general_td));
 273         sync_after_write(tData, sizeof(struct general_td));
 274         sync_after_write(tStatus, sizeof(struct general_td));
 275
 276         dump_address(tSetup, sizeof(struct general_td), "tSetup(before)");
 277         dump_address((void*) phys_to_virt(ACCESS_LE(tSetup->cbp)), tSetupblen, "tSetup->cbp(before)");
 278
 279         dump_address(tData, sizeof(struct general_td), "tData(before)");
 280         dump_address((void*) phys_to_virt(ACCESS_LE(tData->cbp)), tDatablen, "tData->cbp(before)");
 281
 282         dump_address(tStatus, sizeof(struct general_td), "tStatus(before)");
 283         dump_address((void*) phys_to_virt(ACCESS_LE(tStatus->cbp)), tStatusblen, "tStatus->cbp(before)");
 284
 285         dump_address(dummyconfig, sizeof(struct endpoint_descriptor), "dummyconfig(before)");
 286
 287         printf("ctrl head: 0x%08X\n", read32(OHCI0_HC_CTRL_HEAD_ED));
 288         /* trigger control list */
 289         set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 290         write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 291
 292         //don't use this quirk stuff here!
 293 #if 1
 294         while(!read32(OHCI0_HC_CTRL_CURRENT_ED)) {
 295         }
 296 #endif
 297
 298         udelay(100000);
 299         u32 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 300         printf("current: 0x%08X\n", current);
 301         printf("+++++++++++++++++++++++++++++\n");
 302         udelay(100000);
 303
 304         dump_address(tSetup, sizeof(struct general_td), "tSetup(after)");
 305         dump_address((void*) phys_to_virt(ACCESS_LE(tSetup->cbp)), tSetupblen, "tSetup->cbp(after)");
 306         dump_address((void*) tSetupbuffer, tSetupblen, "tSetupbuffer");
 307         dbg_td_flag(ACCESS_LE(tSetup->flags));
 308
 309         dump_address(tData, sizeof(struct general_td), "tData(after)");
 310         dump_address((void*) phys_to_virt(ACCESS_LE(tData->cbp)), tDatablen, "tData->cbp(after)");
 311         dump_address((void*) tDatabuffer, tDatablen, "tDatabuffer");
 312         dbg_td_flag(ACCESS_LE(tData->flags));
 313
 314         dump_address(tStatus, sizeof(struct general_td), "tStatus(after)");
 315         //dump_address((void*) phys_to_virt(ACCESS_LE(tStatus->cbp)), tStatusblen, "tStatus->cbp(after)");
 316         //dump_address((void*) tStatusbuffer, tStatusblen, "tStatusbuffer");
 317         dbg_td_flag(ACCESS_LE(tStatus->flags));
 318
 319         dump_address(dummyconfig, sizeof(struct endpoint_descriptor), "dummyconfig(after)");
 320
 321         /* disable control list */
 322         write32(OHCI0_HC_CONTROL, read32(OHCI0_HC_CONTROL)&~OHCI_CTRL_CLE);
 323
 324         /* TODO
 325          * TD should be free'd after taking it from the done queue.
 326          */
 327
 328 #if 1
 329         free(tSetup);
 330         free(tData);
 331         free(tStatus);
 332         free(dummyconfig);
 333 #endif
 334         printf("hcdi_enqueue, done!\n");
 335         return 0;
 336 }
 337
 338 /**
 339  * Remove an transfer descriptor from transfer queue.
 340  */
 341 u8 hcdi_dequeue(usb_transfer_descriptor *td) {
 342         return 0;
 343 }
 344
 345 void hcdi_init()
 346 {
 347         printf("ohci-- init\n");
 348         dbg_op_state();
 349
 350         /* disable hc interrupts */
 351         set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
 352
 353         /* save fmInterval and calculate FSMPS */
 354 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
 355 #define FI 0x2edf /* 12000 bits per frame (-1) */
 356         u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
 357         if(fmint != FI)
 358                 printf("ohci-- fminterval delta: %d\n", fmint - FI);
 359         fmint |= FSMP (fmint) << 16;
 360
 361         /* enable interrupts of both usb host controllers */
 362         set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
 363
 364         /* reset HC */
 365         write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
 366
 367         /* wait max. 30us */
 368         u32 ts = 30;
 369         while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
 370                  if(--ts == 0) {
 371                         printf("ohci-- FAILED");
 372                         return;
 373                  }
 374                  udelay(1);
 375         }
 376
 377         /* disable interrupts; 2ms timelimit here!
 378            now we're in the SUSPEND state ... must go OPERATIONAL
 379            within 2msec else HC enters RESUME */
 380
 381         u32 cookie = irq_kill();
 382
 383         /* Tell the controller where the control and bulk lists are
 384          * The lists are empty now. */
 385         write32(OHCI0_HC_CTRL_HEAD_ED, 0);
 386         write32(OHCI0_HC_BULK_HEAD_ED, 0);
 387
 388         /* set hcca adress */
 389         sync_after_write(&hcca_oh0, 256);
 390         write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
 391
 392         /* set periodicstart */
 393 #define FIT (1<<31)
 394         u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
 395         u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
 396
 397         write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
 398         write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
 399
 400         /* testing bla */
 401         if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
 402                 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
 403         }
 404
 405         /* start HC operations */
 406         write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
 407
 408         /* wake on ConnectStatusChange, matching external hubs */
 409         write32(OHCI0_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC);
 410
 411         /* Choose the interrupts we care about now, others later on demand */
 412         write32(OHCI0_HC_INT_STATUS, ~0);
 413         write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
 414
 415         //wtf?
 416         wait_ms ((read32(OHCI0_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe);
 417
 418         configure_ports((u8)1);
 419         irq_restore(cookie);
 420
 421         dbg_op_state();
 422 }
 423
 424 static void configure_ports(u8 from_init)
 425 {
 426         printf("OHCI0_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_A));
 427         printf("OHCI0_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_B));
 428         printf("OHCI0_HC_RH_STATUS:\t\t0x%08X\n", read32(OHCI0_HC_RH_STATUS));
 429         printf("OHCI0_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_1));
 430         printf("OHCI0_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_2));
 431
 432         setup_port(OHCI0_HC_RH_PORT_STATUS_1, from_init);
 433         setup_port(OHCI0_HC_RH_PORT_STATUS_2, from_init);
 434         printf("configure_ports done\n");
 435 }
 436
 437 static void setup_port(u32 reg, u8 from_init)
 438 {
 439         u32 port = read32(reg);
 440         if((port & RH_PS_CCS) && ((port & RH_PS_CSC) || from_init)) {
 441                 write32(reg, RH_PS_CSC);
 442
 443                 wait_ms(120);
 444
 445                 /* clear CSC flag, set PES and start port reset (PRS) */
 446                 write32(reg, RH_PS_PES);
 447                 while(!(read32(reg) & RH_PS_PES)) {
 448                         printf("fu\n");
 449                         return;
 450                 }
 451
 452                 write32(reg, RH_PS_PRS);
 453
 454                 /* spin until port reset is complete */
 455                 while(!(read32(reg) & RH_PS_PRSC)); // hint: it may stuck here
 456                 printf("loop done\n");
 457
 458                 wait_ms(20);
 459
 460                 (void) usb_add_device();
 461         }
 462 }
 463
 464 void hcdi_irq()
 465 {
 466         /* read interrupt status */
 467         u32 flags = read32(OHCI0_HC_INT_STATUS);
 468
 469         /* when all bits are set to 1 some problem occured */
 470         if (flags == 0xffffffff) {
 471                 printf("ohci-- Houston, we have a serious problem! :(\n");
 472                 return;
 473         }
 474
 475         /* only care about interrupts that are enabled */
 476         flags &= read32(OHCI0_HC_INT_ENABLE);
 477
 478         /* nothing to do? */
 479         if (flags == 0) {
 480                 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
 481                 return;
 482         }
 483
 484         printf("OHCI Interrupt occured: ");
 485         /* UnrecoverableError */
 486         if (flags & OHCI_INTR_UE) {
 487                 printf("UnrecoverableError\n");
 488                 /* TODO: well, I don't know... nothing,
 489                  *       because it won't happen anyway? ;-) */
 490         }
 491
 492         /* RootHubStatusChange */
 493         if (flags & OHCI_INTR_RHSC) {
 494                 printf("RootHubStatusChange\n");
 495                 /* TODO: set some next_statechange variable... */
 496                 configure_ports(0);
 497                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
 498         }
 499         /* ResumeDetected */
 500         else if (flags & OHCI_INTR_RD) {
 501                 printf("ResumeDetected\n");
 502                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
 503                 /* TODO: figure out what the linux kernel does here... */
 504         }
 505
 506         /* WritebackDoneHead */
 507         if (flags & OHCI_INTR_WDH) {
 508                 printf("WritebackDoneHead\n");
 509                 /* basically the linux irq handler reverse TDs to their urbs
 510                  * and set done_head to null.
 511                  * since we are polling atm, just should do the latter task.
 512                  * however, this won't work for now (i don't know why...)
 513                  * TODO!
 514                  */
 515 #if 0
 516                 sync_before_read(&hcca_oh0, 256);
 517                 hcca_oh0.done_head = 0;
 518                 sync_after_write(&hcca_oh0, 256);
 519 #endif
 520         }
 521
 522         /* TODO: handle any pending URB/ED unlinks... */
 523
 524 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
 525         if (HC_IS_RUNNING()) {
 526                 write32(OHCI0_HC_INT_STATUS, flags);
 527                 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);
 528         }
 529 }
 530
 531 void show_frame_no()
 532 {
 533         sync_before_read(&hcca_oh0, 256);
 534         printf("***** frame_no: %d *****\n", ACCESS_LE(hcca_oh0.frame_no));
 535 }