usb/host/ohci.c

   1 /*
   2        ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
   3        ohci hardware support
   4
   5 Copyright (C) 2009     Bernhard Urban <lewurm@gmx.net>
   6 Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
   7
   8 # This code is licensed to you under the terms of the GNU GPL, version 2;
   9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
  10 */
  11
  12 #include "../../bootmii_ppc.h"
  13 #include "../../hollywood.h"
  14 #include "../../irq.h"
  15 #include "../../string.h"
  16 #include "../../malloc.h"
  17 #include "ohci.h"
  18 #include "host.h"
  19 #include "../usbspec/usb11spec.h"
  20
  21 // macro for accessing u32 variables that need to be in little endian byte order;
  22 // whenever you read or write from an u32 field that the ohci host controller
  23 // will read or write from too, use this macro for access!
  24 #define ACCESS_LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
  25                            (((dword) & 0x00FF0000) >> 8)  | \
  26                            (((dword) & 0x0000FF00) << 8)  | \
  27                            (((dword) & 0x000000FF) << 24) )
  28
  29 static struct ohci_hcca hcca_oh0;
  30
  31 static struct endpoint_descriptor *allocate_endpoint()
  32 {
  33         struct endpoint_descriptor *ep;
  34         //memalign instead of calloc doesn't work here?! WTF
  35         ep = (struct endpoint_descriptor *)memalign(sizeof(struct endpoint_descriptor), 16);
  36         ep->flags = ACCESS_LE(OHCI_ENDPOINT_GENERAL_FORMAT);
  37         ep->headp = ep->tailp = ep->nexted = ACCESS_LE(0);
  38         return ep;
  39 }
  40
  41 static struct general_td *allocate_general_td(size_t bsize)
  42 {
  43         struct general_td *td;
  44         td = (struct general_td *)memalign(sizeof(struct general_td), 16);
  45         td->flags = ACCESS_LE(0);
  46         td->nexttd = ACCESS_LE(virt_to_phys(td));
  47         if(bsize == 0) {
  48                 td->cbp = td->be = ACCESS_LE(0);
  49         } else {
  50                 //td->cbp = ACCESS_LE(virt_to_phys(memalign(bsize, 16))); //memailgn required here?
  51                 td->cbp = ACCESS_LE(virt_to_phys(malloc(bsize))); //memailgn required here?
  52                 td->be = ACCESS_LE(ACCESS_LE(td->cbp) + bsize - 1);
  53         }
  54         return td;
  55 }
  56
  57 static void control_quirk()
  58 {
  59         static struct endpoint_descriptor *ed; /* empty ED */
  60         static struct general_td *td; /* dummy TD */
  61         u32 head;
  62         u32 current;
  63         u32 status;
  64
  65         /*
  66          * One time only.
  67          * Allocate and keep a special empty ED with just a dummy TD.
  68          */
  69         if (!ed) {
  70                 ed = allocate_endpoint();
  71                 if (!ed)
  72                         return;
  73
  74                 td = allocate_general_td(0);
  75                 if (!td) {
  76                         free(ed);
  77                         ed = NULL;
  78                         return;
  79                 }
  80
  81 #define ED_MASK ((u32)~0x0f)
  82                 ed->tailp = ed->headp = ACCESS_LE(virt_to_phys((void*) ((u32)td & ED_MASK)));
  83                 ed->flags |= ACCESS_LE(OHCI_ENDPOINT_DIRECTION_OUT);
  84         }
  85
  86         /*
  87          * The OHCI USB host controllers on the Nintendo Wii
  88          * video game console stop working when new TDs are
  89          * added to a scheduled control ED after a transfer has
  90          * has taken place on it.
  91          *
  92          * Before scheduling any new control TD, we make the
  93          * controller happy by always loading a special control ED
  94          * with a single dummy TD and letting the controller attempt
  95          * the transfer.
  96          * The controller won't do anything with it, as the special
  97          * ED has no TDs, but it will keep the controller from failing
  98          * on the next transfer.
  99          */
 100         head = read32(OHCI0_HC_CTRL_HEAD_ED);
 101         if (head) {
 102                 printf("head: 0x%08X\n", head);
 103                 /*
 104                  * Load the special empty ED and tell the controller to
 105                  * process the control list.
 106                  */
 107                 sync_after_write(ed, 16);
 108                 sync_after_write(td, 16);
 109                 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed));
 110
 111                 status = read32(OHCI0_HC_CONTROL);
 112                 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 113                 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 114
 115                 /* spin until the controller is done with the control list */
 116                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 117                 while(!current) {
 118                         udelay(10);
 119                         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 120                 }
 121
 122                 printf("current: 0x%08X\n", current);
 123
 124                 /* restore the old control head and control settings */
 125                 write32(OHCI0_HC_CONTROL, status);
 126                 write32(OHCI0_HC_CTRL_HEAD_ED, head);
 127         } else {
 128                 printf("nohead!\n");
 129         }
 130 }
 131
 132
 133 static void dbg_op_state()
 134 {
 135         switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
 136                 case OHCI_USB_SUSPEND:
 137                         printf("ohci-- OHCI_USB_SUSPEND\n");
 138                         break;
 139                 case OHCI_USB_RESET:
 140                         printf("ohci-- OHCI_USB_RESET\n");
 141                         break;
 142                 case OHCI_USB_OPER:
 143                         printf("ohci-- OHCI_USB_OPER\n");
 144                         break;
 145                 case OHCI_USB_RESUME:
 146                         printf("ohci-- OHCI_USB_RESUME\n");
 147                         break;
 148         }
 149 }
 150
 151
 152 /**
 153  * Enqueue a transfer descriptor.
 154  */
 155 u8 first = 0;
 156 u8 hcdi_enqueue(usb_transfer_descriptor *td) {
 157         control_quirk();
 158
 159         printf( "===========================\n"
 160                         "===========================\n");
 161         sync_before_read(&hcca_oh0, 256);
 162         printf("done head (nach sync): 0x%08X\n", ACCESS_LE(hcca_oh0.done_head));
 163         printf("HCCA->frame_no: %d\nhcca->hccapad1: %d\n", ((ACCESS_LE(hcca_oh0.frame_no) & 0xffff0000)>>16), ACCESS_LE(hcca_oh0.frame_no)&0xffff );
 164         if(hcca_oh0.done_head) printf("WWWWWWWWOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOTTTTTTTTTTTT\n");
 165
 166         struct general_td *tmptd = allocate_general_td(td->actlen);
 167         (void) memcpy((void*) (phys_to_virt(ACCESS_LE(tmptd->cbp))), td->buffer, td->actlen);
 168
 169         tmptd->flags &= ACCESS_LE(~OHCI_TD_DIRECTION_PID_MASK);
 170         switch(td->pid) {
 171                 case USB_PID_SETUP:
 172                         printf("pid_setup\n");
 173                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_SETUP);
 174                         break;
 175                 case USB_PID_OUT:
 176                         printf("pid_out\n");
 177                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_OUT);
 178                         break;
 179                 case USB_PID_IN:
 180                         printf("pid_in\n");
 181                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_IN);
 182                         break;
 183         }
 184         tmptd->flags |= ACCESS_LE((td->togl) ? OHCI_TD_TOGGLE_1 : OHCI_TD_TOGGLE_0);
 185
 186         printf("tmptd hexdump (before) 0x%08X:\n", tmptd);
 187         hexdump(tmptd, sizeof(struct general_td));
 188         printf("tmptd->cbp hexdump (before) 0x%08X:\n", tmptd->cbp);
 189         hexdump((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 190
 191         sync_after_write((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 192         sync_after_write(tmptd, sizeof(struct general_td));
 193
 194         struct endpoint_descriptor *dummyconfig = allocate_endpoint();
 195
 196 #define ED_MASK2 ~0 /*((u32)~0x0f) */
 197 #define ED_MASK ((u32)~0x0f)
 198         dummyconfig->tailp = dummyconfig->headp = ACCESS_LE(virt_to_phys((void*) ((u32)tmptd & ED_MASK)));
 199
 200         dummyconfig->flags |= ACCESS_LE(OHCI_ENDPOINT_LOW_SPEED |
 201                 OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
 202                 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
 203                 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
 204
 205         printf("dummyconfig hexdump (before) 0x%08X:\n", dummyconfig);
 206         hexdump((void*) dummyconfig, 16);
 207
 208         sync_after_write(dummyconfig, 16);
 209         write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(dummyconfig));
 210
 211         printf("OHCI_CTRL_CLE: 0x%08X || ", read32(OHCI0_HC_CONTROL)&OHCI_CTRL_CLE);
 212         printf("OHCI_CLF: 0x%08X\n", read32(OHCI0_HC_COMMAND_STATUS)&OHCI_CLF);
 213         set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 214         write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 215
 216         printf("+++++++++++++++++++++++++++++\n");
 217         /* spin until the controller is done with the control list */
 218         u32 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 219         printf("current: 0x%08X\n", current);
 220         while(!current) {
 221                 udelay(10);
 222                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 223         }
 224
 225         udelay(20000);
 226         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 227         printf("current: 0x%08X\n", current);
 228         printf("+++++++++++++++++++++++++++++\n");
 229         udelay(20000);
 230
 231
 232         sync_before_read(tmptd, sizeof(struct general_td));
 233         printf("tmptd hexdump (after) 0x%08X:\n", tmptd);
 234         hexdump(tmptd, sizeof(struct general_td));
 235
 236         sync_before_read((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 237         printf("tmptd->cbp hexdump (after) 0x%08X:\n", tmptd->cbp);
 238         hexdump((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 239
 240         sync_before_read(dummyconfig, 16);
 241         printf("dummyconfig hexdump (after) 0x%08X:\n", dummyconfig);
 242         hexdump((void*) dummyconfig, 16);
 243
 244         sync_before_read(&hcca_oh0, 256);
 245         printf("done head (nach sync): 0x%08X\n", ACCESS_LE(hcca_oh0.done_head));
 246
 247         //should be free'd after taking it from the done queue
 248         //free(tmptd);
 249         return 0;
 250 }
 251
 252 /**
 253  * Remove an transfer descriptor from transfer queue.
 254  */
 255 u8 hcdi_dequeue(usb_transfer_descriptor *td) {
 256         return 0;
 257 }
 258
 259 void hcdi_init()
 260 {
 261         printf("ohci-- init\n");
 262         dbg_op_state();
 263
 264         /* disable hc interrupts */
 265         set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
 266
 267         /* save fmInterval and calculate FSMPS */
 268 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
 269 #define FI 0x2edf /* 12000 bits per frame (-1) */
 270         u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
 271         if(fmint != FI)
 272                 printf("ohci-- fminterval delta: %d\n", fmint - FI);
 273         fmint |= FSMP (fmint) << 16;
 274
 275         /* enable interrupts of both usb host controllers */
 276         set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
 277
 278         /* reset HC */
 279         write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
 280
 281         /* wait max. 30us */
 282         u32 ts = 30;
 283         while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
 284                  if(--ts == 0) {
 285                         printf("ohci-- FAILED");
 286                         return;
 287                  }
 288                  udelay(1);
 289         }
 290
 291         /* disable interrupts; 2ms timelimit here!
 292            now we're in the SUSPEND state ... must go OPERATIONAL
 293            within 2msec else HC enters RESUME */
 294
 295         u32 cookie = irq_kill();
 296
 297         /* Tell the controller where the control and bulk lists are
 298          * The lists are empty now. */
 299         write32(OHCI0_HC_CTRL_HEAD_ED, 0);
 300         write32(OHCI0_HC_BULK_HEAD_ED, 0);
 301
 302         /* set hcca adress */
 303         sync_after_write(&hcca_oh0, 256);
 304         write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
 305
 306         /* set periodicstart */
 307 #define FIT (1<<31)
 308         u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
 309         u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
 310
 311         write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
 312         write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
 313
 314         /* testing bla */
 315         if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
 316                 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
 317         }
 318
 319         /* start HC operations */
 320         write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
 321
 322         /* wake on ConnectStatusChange, matching external hubs */
 323         set32(OHCI0_HC_RH_STATUS, RH_HS_DRWE);
 324
 325         /* Choose the interrupts we care about now, others later on demand */
 326         write32(OHCI0_HC_INT_STATUS, ~0);
 327         write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
 328
 329         irq_restore(cookie);
 330
 331         dbg_op_state();
 332 }
 333
 334 void hcdi_irq()
 335 {
 336         /* read interrupt status */
 337         u32 flags = read32(OHCI0_HC_INT_STATUS);
 338
 339         /* when all bits are set to 1 some problem occured */
 340         if (flags == 0xffffffff) {
 341                 printf("ohci-- Houston, we have a serious problem! :(\n");
 342                 return;
 343         }
 344
 345         /* only care about interrupts that are enabled */
 346         flags &= read32(OHCI0_HC_INT_ENABLE);
 347
 348         /* nothing to do? */
 349         if (flags == 0) {
 350                 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
 351                 return;
 352         }
 353
 354         printf("OHCI Interrupt occured: ");
 355         /* UnrecoverableError */
 356         if (flags & OHCI_INTR_UE) {
 357                 printf("UnrecoverableError\n");
 358                 /* TODO: well, I don't know... nothing,
 359                  *       because it won't happen anyway? ;-) */
 360         }
 361
 362         /* RootHubStatusChange */
 363         if (flags & OHCI_INTR_RHSC) {
 364                 printf("RootHubStatusChange\n");
 365                 /* TODO: set some next_statechange variable... */
 366                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
 367         }
 368         /* ResumeDetected */
 369         else if (flags & OHCI_INTR_RD) {
 370                 printf("ResumeDetected\n");
 371                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
 372                 /* TODO: figure out what the linux kernel does here... */
 373         }
 374
 375         /* WritebackDoneHead */
 376         if (flags & OHCI_INTR_WDH) {
 377                 printf("WritebackDoneHead\n");
 378                 /* TODO: figure out what the linux kernel does here... */
 379         }
 380
 381         /* TODO: handle any pending URB/ED unlinks... */
 382
 383 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
 384         if (HC_IS_RUNNING()) {
 385                 write32(OHCI0_HC_INT_STATUS, flags);
 386                 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);
 387         }
 388 }
 389