usb/host/ohci.c

   1 /*
   2        ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
   3        ohci hardware support
   4
   5 Copyright (C) 2009     Bernhard Urban <lewurm@gmx.net>
   6 Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
   7
   8 # This code is licensed to you under the terms of the GNU GPL, version 2;
   9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
  10 */
  11
  12 #include "../../bootmii_ppc.h"
  13 #include "../../hollywood.h"
  14 #include "../../irq.h"
  15 #include "../../string.h"
  16 #include "../../malloc.h"
  17 #include "ohci.h"
  18 #include "host.h"
  19 #include "../usbspec/usb11spec.h"
  20
  21 // macro for accessing u32 variables that need to be in little endian byte order;
  22 // whenever you read or write from an u32 field that the ohci host controller
  23 // will read or write from too, use this macro for access!
  24 #define ACCESS_LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
  25                            (((dword) & 0x00FF0000) >> 8)  | \
  26                            (((dword) & 0x0000FF00) << 8)  | \
  27                            (((dword) & 0x000000FF) << 24) )
  28
  29 static struct ohci_hcca hcca_oh0;
  30
  31 static struct endpoint_descriptor *allocate_endpoint()
  32 {
  33         struct endpoint_descriptor *ep;
  34         //memalign instead of calloc doesn't work here?! WTF
  35         ep = (struct endpoint_descriptor *)memalign(sizeof(struct endpoint_descriptor), 16);
  36         ep->flags = ACCESS_LE(OHCI_ENDPOINT_GENERAL_FORMAT);
  37         ep->headp = ep->tailp = ep->nexted = ACCESS_LE(0);
  38         return ep;
  39 }
  40
  41 static struct general_td *allocate_general_td(size_t bsize)
  42 {
  43         struct general_td *td;
  44         td = (struct general_td *)memalign(sizeof(struct general_td), 16);
  45         td->flags = ACCESS_LE(0);
  46         // TODO !! nexttd?
  47         td->nexttd = ACCESS_LE(virt_to_phys(td));
  48         //td->nexttd = ACCESS_LE(0);
  49         if(bsize == 0) {
  50                 td->cbp = td->be = ACCESS_LE(0);
  51         } else {
  52                 //td->cbp = ACCESS_LE(virt_to_phys(memalign(bsize, 16))); //memailgn required here?
  53                 td->cbp = ACCESS_LE(virt_to_phys(malloc(bsize)));
  54                 td->be = ACCESS_LE(ACCESS_LE(td->cbp) + bsize - 1);
  55         }
  56         return td;
  57 }
  58
  59 static void control_quirk()
  60 {
  61         static struct endpoint_descriptor *ed = 0; /* empty ED */
  62         static struct general_td *td = 0; /* dummy TD */
  63         u32 head;
  64         u32 current;
  65         u32 status;
  66
  67         /*
  68          * One time only.
  69          * Allocate and keep a special empty ED with just a dummy TD.
  70          */
  71         if (!ed) {
  72                 ed = allocate_endpoint();
  73                 if (!ed)
  74                         return;
  75
  76                 td = allocate_general_td(0);
  77                 if (!td) {
  78                         free(ed);
  79                         ed = NULL;
  80                         return;
  81                 }
  82
  83 #define ED_MASK ((u32)~0x0f)
  84                 ed->tailp = ed->headp = ACCESS_LE(virt_to_phys((void*) ((u32)td & ED_MASK)));
  85                 ed->flags |= ACCESS_LE(OHCI_ENDPOINT_DIRECTION_OUT);
  86         }
  87
  88         /*
  89          * The OHCI USB host controllers on the Nintendo Wii
  90          * video game console stop working when new TDs are
  91          * added to a scheduled control ED after a transfer has
  92          * has taken place on it.
  93          *
  94          * Before scheduling any new control TD, we make the
  95          * controller happy by always loading a special control ED
  96          * with a single dummy TD and letting the controller attempt
  97          * the transfer.
  98          * The controller won't do anything with it, as the special
  99          * ED has no TDs, but it will keep the controller from failing
 100          * on the next transfer.
 101          */
 102         head = read32(OHCI0_HC_CTRL_HEAD_ED);
 103         if (head) {
 104                 printf("head: 0x%08X\n", head);
 105                 /*
 106                  * Load the special empty ED and tell the controller to
 107                  * process the control list.
 108                  */
 109                 sync_after_write(ed, 16);
 110                 sync_after_write(td, 16);
 111                 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed));
 112
 113                 status = read32(OHCI0_HC_CONTROL);
 114                 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 115                 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 116
 117                 /* spin until the controller is done with the control list */
 118                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 119                 while(!current) {
 120                         udelay(10);
 121                         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 122                 }
 123
 124                 printf("current: 0x%08X\n", current);
 125
 126                 /* restore the old control head and control settings */
 127                 write32(OHCI0_HC_CONTROL, status);
 128                 write32(OHCI0_HC_CTRL_HEAD_ED, head);
 129         } else {
 130                 printf("nohead!\n");
 131         }
 132 }
 133
 134
 135 static void dbg_op_state()
 136 {
 137         switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
 138                 case OHCI_USB_SUSPEND:
 139                         printf("ohci-- OHCI_USB_SUSPEND\n");
 140                         break;
 141                 case OHCI_USB_RESET:
 142                         printf("ohci-- OHCI_USB_RESET\n");
 143                         break;
 144                 case OHCI_USB_OPER:
 145                         printf("ohci-- OHCI_USB_OPER\n");
 146                         break;
 147                 case OHCI_USB_RESUME:
 148                         printf("ohci-- OHCI_USB_RESUME\n");
 149                         break;
 150         }
 151 }
 152
 153 static void dbg_td_flag(u32 flag)
 154 {
 155         printf("**************** dbg_td_flag: 0x%08X ***************\n", flag);
 156         printf("CC: %X\tshould be 0, see page 32 (ohci spec)\n", (flag>>28)&0xf);
 157         printf("EC: %X\tsee page 20 (ohci spec)\n", (flag>>26)&3);
 158         printf(" T: %X\n", (flag>>24)&3);
 159         printf("DI: %X\n", (flag>>21)&7);
 160         printf("DP: %X\n", (flag>>19)&3);
 161         printf(" R: %X\n", (flag>>18)&1);
 162         printf("********************************************************\n");
 163 }
 164
 165
 166
 167 /**
 168  * Enqueue a transfer descriptor.
 169  */
 170 u8 hcdi_enqueue(usb_transfer_descriptor *td) {
 171         control_quirk(); //required? YES! :O
 172
 173         static struct endpoint_descriptor dummyconfig;
 174         dummyconfig.flags = ACCESS_LE(OHCI_ENDPOINT_GENERAL_FORMAT);
 175         dummyconfig.headp = dummyconfig.tailp = dummyconfig.nexted = ACCESS_LE(0);
 176
 177         printf( "===========================\n"
 178                         "===========================\n");
 179         sync_before_read(&hcca_oh0, 256);
 180         printf("done head (nach sync): 0x%08X\n", ACCESS_LE(hcca_oh0.done_head));
 181         printf("HCCA->frame_no: %d\nhcca->hccapad1: %d\n",
 182                         ((ACCESS_LE(hcca_oh0.frame_no) & 0xffff)>>16),
 183                         ACCESS_LE(hcca_oh0.frame_no)&0x0000ffff );
 184
 185         struct general_td *tmptd = allocate_general_td(td->actlen);
 186         (void) memcpy((void*) (phys_to_virt(ACCESS_LE(tmptd->cbp))), td->buffer, td->actlen);
 187
 188         tmptd->flags &= ACCESS_LE(~OHCI_TD_DIRECTION_PID_MASK);
 189         switch(td->pid) {
 190                 case USB_PID_SETUP:
 191                         printf("pid_setup\n");
 192                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_SETUP);
 193                         break;
 194                 case USB_PID_OUT:
 195                         printf("pid_out\n");
 196                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_OUT);
 197                         break;
 198                 case USB_PID_IN:
 199                         printf("pid_in\n");
 200                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_IN);
 201                         break;
 202         }
 203         tmptd->flags |= ACCESS_LE((td->togl) ? OHCI_TD_TOGGLE_1 : OHCI_TD_TOGGLE_0);
 204
 205         printf("tmptd hexdump (before) 0x%08X:\n", tmptd);
 206         hexdump(tmptd, sizeof(struct general_td));
 207         printf("tmptd->cbp hexdump (before) 0x%08X:\n", phys_to_virt(ACCESS_LE(tmptd->cbp)));
 208         hexdump((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 209
 210         sync_after_write(tmptd, sizeof(struct general_td));
 211         sync_after_write((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 212
 213
 214 #define ED_MASK2 ~0 /*((u32)~0x0f) */
 215 #define ED_MASK ((u32)~0x0f)
 216         dummyconfig.headp = ACCESS_LE(virt_to_phys((void*) ((u32)tmptd & ED_MASK)));
 217
 218         dummyconfig.flags |= ACCESS_LE(OHCI_ENDPOINT_LOW_SPEED |
 219                 OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
 220                 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
 221                 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
 222
 223         printf("dummyconfig hexdump (before) 0x%08X:\n", &dummyconfig);
 224         hexdump((void*) &dummyconfig, 16);
 225
 226         sync_after_write(&dummyconfig, 16);
 227         write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(&dummyconfig));
 228
 229         printf("OHCI_CTRL_CLE: 0x%08X || ", read32(OHCI0_HC_CONTROL)&OHCI_CTRL_CLE);
 230         printf("OHCI_CLF: 0x%08X\n", read32(OHCI0_HC_COMMAND_STATUS)&OHCI_CLF);
 231         set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 232         write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 233
 234         printf("+++++++++++++++++++++++++++++\n");
 235         /* spin until the controller is done with the control list */
 236         u32 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 237         printf("current: 0x%08X\n", current);
 238         while(!current) {
 239                 udelay(2);
 240                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 241         }
 242
 243         udelay(20000);
 244         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 245         printf("current: 0x%08X\n", current);
 246         printf("+++++++++++++++++++++++++++++\n");
 247         udelay(20000);
 248
 249         sync_before_read(tmptd, sizeof(struct general_td));
 250         printf("tmptd hexdump (after) 0x%08X:\n", tmptd);
 251         hexdump(tmptd, sizeof(struct general_td));
 252         dbg_td_flag(ACCESS_LE(tmptd->flags));
 253
 254         sync_before_read((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 255         printf("tmptd->cbp hexdump (after) 0x%08X:\n", phys_to_virt(ACCESS_LE(tmptd->cbp)));
 256         hexdump((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 257
 258         sync_before_read(&dummyconfig, 16);
 259         printf("dummyconfig hexdump (after) 0x%08X:\n", &dummyconfig);
 260         hexdump((void*) &dummyconfig, 16);
 261
 262         sync_before_read(&hcca_oh0, 256);
 263         printf("done head (nach sync): 0x%08X\n", ACCESS_LE(hcca_oh0.done_head));
 264
 265         sync_before_read((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 266         (void) memcpy((void*) (td->buffer), phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 267
 268         write32(OHCI0_HC_CONTROL, read32(OHCI0_HC_CONTROL)&~OHCI_CTRL_CLE);
 269         dummyconfig.headp = dummyconfig.tailp = dummyconfig.nexted = ACCESS_LE(0);
 270         //should be free'd after taking it from the done queue
 271         //however, it fails?! WTF
 272 #if 0
 273         printf("WTF1\n");
 274         free(tmptd);
 275         printf("WTF0\n");
 276         free((void*) tmptd->cbp);
 277         printf("WTF3\n");
 278 #endif
 279         return 0;
 280 }
 281
 282 /**
 283  * Remove an transfer descriptor from transfer queue.
 284  */
 285 u8 hcdi_dequeue(usb_transfer_descriptor *td) {
 286         return 0;
 287 }
 288
 289 void hcdi_init()
 290 {
 291         printf("ohci-- init\n");
 292         dbg_op_state();
 293
 294         /* disable hc interrupts */
 295         set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
 296
 297         /* save fmInterval and calculate FSMPS */
 298 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
 299 #define FI 0x2edf /* 12000 bits per frame (-1) */
 300         u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
 301         if(fmint != FI)
 302                 printf("ohci-- fminterval delta: %d\n", fmint - FI);
 303         fmint |= FSMP (fmint) << 16;
 304
 305         /* enable interrupts of both usb host controllers */
 306         set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
 307
 308         /* reset HC */
 309         write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
 310
 311         /* wait max. 30us */
 312         u32 ts = 30;
 313         while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
 314                  if(--ts == 0) {
 315                         printf("ohci-- FAILED");
 316                         return;
 317                  }
 318                  udelay(1);
 319         }
 320
 321         /* disable interrupts; 2ms timelimit here!
 322            now we're in the SUSPEND state ... must go OPERATIONAL
 323            within 2msec else HC enters RESUME */
 324
 325         u32 cookie = irq_kill();
 326
 327         /* Tell the controller where the control and bulk lists are
 328          * The lists are empty now. */
 329         write32(OHCI0_HC_CTRL_HEAD_ED, 0);
 330         write32(OHCI0_HC_BULK_HEAD_ED, 0);
 331
 332         /* set hcca adress */
 333         sync_after_write(&hcca_oh0, 256);
 334         write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
 335
 336         /* set periodicstart */
 337 #define FIT (1<<31)
 338         u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
 339         u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
 340
 341         write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
 342         write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
 343
 344         /* testing bla */
 345         if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
 346                 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
 347         }
 348
 349         /* start HC operations */
 350         write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
 351
 352         /* wake on ConnectStatusChange, matching external hubs */
 353         set32(OHCI0_HC_RH_STATUS, RH_HS_DRWE);
 354
 355         /* Choose the interrupts we care about now, others later on demand */
 356         write32(OHCI0_HC_INT_STATUS, ~0);
 357         write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
 358
 359         irq_restore(cookie);
 360
 361         dbg_op_state();
 362 }
 363
 364 void hcdi_irq()
 365 {
 366         /* read interrupt status */
 367         u32 flags = read32(OHCI0_HC_INT_STATUS);
 368
 369         /* when all bits are set to 1 some problem occured */
 370         if (flags == 0xffffffff) {
 371                 printf("ohci-- Houston, we have a serious problem! :(\n");
 372                 return;
 373         }
 374
 375         /* only care about interrupts that are enabled */
 376         flags &= read32(OHCI0_HC_INT_ENABLE);
 377
 378         /* nothing to do? */
 379         if (flags == 0) {
 380                 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
 381                 return;
 382         }
 383
 384         printf("OHCI Interrupt occured: ");
 385         /* UnrecoverableError */
 386         if (flags & OHCI_INTR_UE) {
 387                 printf("UnrecoverableError\n");
 388                 /* TODO: well, I don't know... nothing,
 389                  *       because it won't happen anyway? ;-) */
 390         }
 391
 392         /* RootHubStatusChange */
 393         if (flags & OHCI_INTR_RHSC) {
 394                 printf("RootHubStatusChange\n");
 395                 /* TODO: set some next_statechange variable... */
 396                 u32 port1 = read32(OHCI0_HC_RH_PORT_STATUS_1);
 397                 u32 port2 = read32(OHCI0_HC_RH_PORT_STATUS_2);
 398                 printf("OHCI0_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_A));
 399                 printf("OHCI0_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_B));
 400                 printf("OHCI0_HC_RH_STATUS:\t\t0x%08X\n", read32(OHCI0_HC_RH_STATUS));
 401                 printf("OHCI0_HC_RH_PORT_STATUS_1:\t0x%08X\n", port1);
 402                 printf("OHCI0_HC_RH_PORT_STATUS_2:\t0x%08X\n", port2);
 403
 404                 if((port1 & RH_PS_CCS) && (port1 & RH_PS_CSC)) {
 405                         write32(OHCI0_HC_RH_PORT_STATUS_1, RH_PS_CSC);
 406
 407                         wait_ms(100);
 408
 409                         /* clear CSC flag, set PES and start port reset (PRS) */
 410                         write32(OHCI0_HC_RH_PORT_STATUS_1, RH_PS_PES);
 411                         write32(OHCI0_HC_RH_PORT_STATUS_1, RH_PS_PRS);
 412
 413                         /* spin until port reset is complete */
 414                         port1 = read32(OHCI0_HC_RH_PORT_STATUS_1);
 415                         while(!(port1 & RH_PS_PRSC)) {
 416                                 udelay(2);
 417                                 printf("fuck");
 418                                 port1 = read32(OHCI0_HC_RH_PORT_STATUS_1);
 419                         }
 420
 421                         (void) usb_add_device();
 422                 }
 423                 if((port2 & RH_PS_CCS) && (port2 & RH_PS_CSC)) {
 424                         wait_ms(100);
 425
 426                         /* clear CSC flag, set PES and start port reset (PRS) */
 427                         write32(OHCI0_HC_RH_PORT_STATUS_2, port2 | RH_PS_CSC | RH_PS_PES | RH_PS_PRS);
 428
 429                         /* spin until port reset is complete */
 430                         port2 = read32(OHCI0_HC_RH_PORT_STATUS_2);
 431                         while(!(port2 & RH_PS_PRSC)) {
 432                                 udelay(2);
 433                                 port2 = read32(OHCI0_HC_RH_PORT_STATUS_2);
 434                         }
 435
 436                         (void) usb_add_device();
 437                 }
 438
 439                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
 440         }
 441         /* ResumeDetected */
 442         else if (flags & OHCI_INTR_RD) {
 443                 printf("ResumeDetected\n");
 444                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
 445                 /* TODO: figure out what the linux kernel does here... */
 446         }
 447
 448         /* WritebackDoneHead */
 449         if (flags & OHCI_INTR_WDH) {
 450                 printf("WritebackDoneHead\n");
 451                 /* basically the linux irq handler reverse TDs to their urbs
 452                  * and set done_head to null.
 453                  * since we are polling atm, just should do the latter task.
 454                  * however, this won't work for now (i don't know why...)
 455                  * TODO!
 456                  */
 457 #if 0
 458                 sync_before_read(&hcca_oh0, 256);
 459                 hcca_oh0.done_head = 0;
 460                 sync_after_write(&hcca_oh0, 256);
 461 #endif
 462         }
 463
 464         /* TODO: handle any pending URB/ED unlinks... */
 465
 466 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
 467         if (HC_IS_RUNNING()) {
 468                 write32(OHCI0_HC_INT_STATUS, flags);
 469                 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);
 470         }
 471 }
 472