2 ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
5 Copyright (C) 2009 Bernhard Urban <lewurm@gmx.net>
6 Copyright (C) 2009 Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
8 # This code is licensed to you under the terms of the GNU GPL, version 2;
9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
12 #include "../../bootmii_ppc.h"
13 #include "../../hollywood.h"
14 #include "../../irq.h"
15 #include "../../string.h"
16 #include "../../malloc.h"
19 #include "../usbspec/usb11spec.h"
21 /* macro for accessing u32 variables that need to be in little endian byte order;
23 * whenever you read or write from an u32 field that the ohci host controller
24 * will read or write from too, use this macro for access!
26 #define LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
27 (((dword) & 0x00FF0000) >> 8) | \
28 (((dword) & 0x0000FF00) << 8) | \
29 (((dword) & 0x000000FF) << 24) )
31 static struct endpoint_descriptor *allocate_endpoint();
32 static struct general_td *allocate_general_td();
33 static void control_quirk();
34 static void dbg_op_state();
35 //static void dbg_td_flag(u32 flag);
36 static void configure_ports(u8 from_init);
37 static void setup_port(u32 reg, u8 from_init);
39 static struct ohci_hcca hcca_oh0;
42 static struct endpoint_descriptor *allocate_endpoint()
44 struct endpoint_descriptor *ep;
45 ep = (struct endpoint_descriptor *)memalign(16, sizeof(struct endpoint_descriptor));
46 ep->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
47 ep->headp = ep->tailp = ep->nexted = LE(0);
51 static struct general_td *allocate_general_td()
53 struct general_td *td;
54 td = (struct general_td *)memalign(16, sizeof(struct general_td));
57 td->cbp = td->be = LE(0);
61 static void control_quirk()
63 static struct endpoint_descriptor *ed = 0; /* empty ED */
64 static struct general_td *td = 0; /* dummy TD */
71 * Allocate and keep a special empty ED with just a dummy TD.
74 ed = allocate_endpoint();
78 td = allocate_general_td(0);
85 #define ED_MASK ((u32)~0x0f)
86 ed->tailp = ed->headp = LE(virt_to_phys((void*) ((u32)td & ED_MASK)));
87 ed->flags |= LE(OHCI_ENDPOINT_DIRECTION_OUT);
91 * The OHCI USB host controllers on the Nintendo Wii
92 * video game console stop working when new TDs are
93 * added to a scheduled control ED after a transfer has
94 * has taken place on it.
96 * Before scheduling any new control TD, we make the
97 * controller happy by always loading a special control ED
98 * with a single dummy TD and letting the controller attempt
100 * The controller won't do anything with it, as the special
101 * ED has no TDs, but it will keep the controller from failing
102 * on the next transfer.
104 head = read32(OHCI0_HC_CTRL_HEAD_ED);
106 printf("head: 0x%08X\n", head);
108 * Load the special empty ED and tell the controller to
109 * process the control list.
111 sync_after_write(ed, 16);
112 sync_after_write(td, 16);
113 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed));
115 status = read32(OHCI0_HC_CONTROL);
116 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
117 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
119 /* spin until the controller is done with the control list */
120 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
123 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
126 printf("current: 0x%08X\n", current);
128 /* restore the old control head and control settings */
129 write32(OHCI0_HC_CONTROL, status);
130 write32(OHCI0_HC_CTRL_HEAD_ED, head);
137 static void dbg_op_state()
139 switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
140 case OHCI_USB_SUSPEND:
141 printf("ohci-- OHCI_USB_SUSPEND\n");
144 printf("ohci-- OHCI_USB_RESET\n");
147 printf("ohci-- OHCI_USB_OPER\n");
149 case OHCI_USB_RESUME:
150 printf("ohci-- OHCI_USB_RESUME\n");
156 static void dbg_td_flag(u32 flag)
158 printf("**************** dbg_td_flag: 0x%08X ***************\n", flag);
159 printf("CC: %X\tshould be 0, see page 32 (ohci spec)\n", (flag>>28)&0xf);
160 printf("EC: %X\tsee page 20 (ohci spec)\n", (flag>>26)&3);
161 printf(" T: %X\n", (flag>>24)&3);
162 printf("DI: %X\n", (flag>>21)&7);
163 printf("DP: %X\n", (flag>>19)&3);
164 printf(" R: %X\n", (flag>>18)&1);
165 printf("********************************************************\n");
169 static void general_td_fill(struct general_td *dest, const usb_transfer_descriptor *src)
171 dest->bufaddr = dest->cbp = LE(virt_to_phys(src->buffer));
172 dest->be = src->actlen ? LE(LE(dest->cbp) + src->actlen - 1) : LE(0);
173 dest->flags &= LE(~OHCI_TD_DIRECTION_PID_MASK);
174 dest->buflen = src->actlen;
178 printf("pid_setup\n");
179 dest->flags |= LE(OHCI_TD_DIRECTION_PID_SETUP);
180 dest->flags |= LE(OHCI_TD_TOGGLE_0);
181 dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
185 dest->flags |= LE(OHCI_TD_DIRECTION_PID_OUT);
186 dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
189 * TODO: just temporary solution! (consider it with len?)
190 * there can be also regular PID_OUT pakets
192 dest->flags |= LE(OHCI_TD_TOGGLE_1);
196 dest->flags |= LE(OHCI_TD_DIRECTION_PID_IN);
197 dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
199 * let the endpoint do the togglestuff!
200 * TODO: just temporary solution!
201 * there can be also inregular PID_IN pakets (@Status Stage)
203 dest->flags |= LE(OHCI_TD_TOGGLE_CARRY);
205 /* should be done by HC!
206 * first pid_in start with DATA0 */
208 dummyconfig.headp = LE( src->togl ?
209 LE(dummyconfig.headp) | OHCI_ENDPOINT_TOGGLE_CARRY :
210 LE(dummyconfig.headp) & ~OHCI_ENDPOINT_TOGGLE_CARRY);
214 dest->flags |= LE(OHCI_TD_SET_DELAY_INTERRUPT(7));
216 // not necessary here anymore?
217 sync_after_write(dest, sizeof(struct general_td));
218 sync_after_write((void*) phys_to_virt(LE(dest->cbp)), src->actlen);
222 static void dump_address(void *addr, u32 size, const char* str)
224 sync_before_read(addr, size);
225 printf("%s hexdump @ 0x%08X:\n", str, addr);
229 struct endpoint_descriptor *edhead = 0;
232 printf("<^> <^> <^> hcdi_fire(start)\n");
234 control_quirk(); //required? YES! :O ... erm... or no? :/ ... in fact I have no idea
237 sync_after_write(edhead, sizeof(struct endpoint_descriptor));
238 dump_address(edhead, sizeof(struct endpoint_descriptor), "edhead(before)");
240 struct general_td *x = phys_to_virt(LE(edhead->headp));
241 while(virt_to_phys(x)) {
242 sync_after_write(x, sizeof(struct general_td));
243 dump_address(x, sizeof(struct general_td), "x(before)");
246 sync_after_write((void*) x->cbp, x->buflen);
247 dump_address((void*) phys_to_virt(LE(x->cbp)), x->buflen, "x->cbp(before)");
249 x = phys_to_virt(LE(x->nexttd));
252 /* trigger control list */
254 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
255 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
257 //don't use this quirk stuff here!?
259 while(!read32(OHCI0_HC_CTRL_CURRENT_ED)) {
262 printf("+++++++++++++++++++++++++++++\n");
263 printf("wait: %d\n", wait);
266 sync_before_read(&hcca_oh0, sizeof(hcca_oh0));
267 struct general_td *n = phys_to_virt(LE(hcca_oh0.done_head));
268 printf("done_head: 0x%08X\n", n);
270 struct general_td *prev = 0;
275 sync_before_read((void*) n, sizeof(struct general_td));
276 dump_address(n, sizeof(struct general_td), "n(after)");
277 dump_address((void*) phys_to_virt(LE(n->cbp)), n->buflen, "n->cbp(after)");
278 dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
279 dbg_td_flag(LE(n->flags));
280 n = prev = phys_to_virt(LE(n->nexttd));
282 hcca_oh0.done_head = 0;
283 sync_after_write(&hcca_oh0, sizeof(hcca_oh0));
286 write32(OHCI0_HC_CONTROL, read32(OHCI0_HC_CONTROL)&~OHCI_CTRL_CLE);
291 printf("<^> <^> <^> hcdi_fire(end)\n");
295 * Enqueue a transfer descriptor.
297 u8 hcdi_enqueue(const usb_transfer_descriptor *td) {
298 printf("*()*()*()*()*()*()*() hcdi_enqueue(start)\n");
300 edhead = allocate_endpoint();
301 edhead->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
302 edhead->headp = edhead->tailp = edhead->nexted = LE(0);
303 edhead->flags |= LE(OHCI_ENDPOINT_LOW_SPEED |
304 OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
305 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
306 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
307 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(edhead));
310 struct general_td *tdhw = allocate_general_td();
311 general_td_fill(tdhw, td);
313 #define ED_MASK ((u32)~0x0f)
316 edhead->headp = LE(virt_to_phys((void*) ((u32)tdhw & ED_MASK)));
319 /* headp in endpoint already exists
322 struct general_td *n = (struct general_td*) phys_to_virt(LE(edhead->headp));
323 while(LE(n->nexttd)) {
324 n = phys_to_virt(LE(n->nexttd));
326 n->nexttd = LE(virt_to_phys((void*) ((u32)tdhw & ED_MASK)));
329 printf("*()*()*()*()*()*()*() hcdi_enqueue(end)\n");
335 * Remove an transfer descriptor from transfer queue.
337 u8 hcdi_dequeue(usb_transfer_descriptor *td) {
343 printf("ohci-- init\n");
346 /* disable hc interrupts */
347 set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
349 /* save fmInterval and calculate FSMPS */
350 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
351 #define FI 0x2edf /* 12000 bits per frame (-1) */
352 u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
354 printf("ohci-- fminterval delta: %d\n", fmint - FI);
355 fmint |= FSMP (fmint) << 16;
357 /* enable interrupts of both usb host controllers */
358 set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
361 write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
365 while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
367 printf("ohci-- FAILED");
373 /* disable interrupts; 2ms timelimit here!
374 now we're in the SUSPEND state ... must go OPERATIONAL
375 within 2msec else HC enters RESUME */
377 u32 cookie = irq_kill();
379 /* Tell the controller where the control and bulk lists are
380 * The lists are empty now. */
381 write32(OHCI0_HC_CTRL_HEAD_ED, 0);
382 write32(OHCI0_HC_BULK_HEAD_ED, 0);
384 /* set hcca adress */
385 sync_after_write(&hcca_oh0, 256);
386 write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
388 /* set periodicstart */
390 u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
391 u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
393 write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
394 write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
397 if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
398 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
401 /* start HC operations */
402 write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
404 /* wake on ConnectStatusChange, matching external hubs */
405 write32(OHCI0_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC);
407 /* Choose the interrupts we care about now, others later on demand */
408 write32(OHCI0_HC_INT_STATUS, ~0);
409 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
412 wait_ms ((read32(OHCI0_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe);
414 configure_ports((u8)1);
420 static void configure_ports(u8 from_init)
422 printf("OHCI0_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_A));
423 printf("OHCI0_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_B));
424 printf("OHCI0_HC_RH_STATUS:\t\t0x%08X\n", read32(OHCI0_HC_RH_STATUS));
425 printf("OHCI0_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_1));
426 printf("OHCI0_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_2));
428 setup_port(OHCI0_HC_RH_PORT_STATUS_1, from_init);
429 setup_port(OHCI0_HC_RH_PORT_STATUS_2, from_init);
430 printf("configure_ports done\n");
433 static void setup_port(u32 reg, u8 from_init)
435 u32 port = read32(reg);
436 if((port & RH_PS_CCS) && ((port & RH_PS_CSC) || from_init)) {
437 write32(reg, RH_PS_CSC);
441 /* clear CSC flag, set PES and start port reset (PRS) */
442 write32(reg, RH_PS_PES);
443 while(!(read32(reg) & RH_PS_PES)) {
448 write32(reg, RH_PS_PRS);
450 /* spin until port reset is complete */
451 while(!(read32(reg) & RH_PS_PRSC)); // hint: it may stuck here
452 printf("loop done\n");
454 (void) usb_add_device();
460 /* read interrupt status */
461 u32 flags = read32(OHCI0_HC_INT_STATUS);
463 /* when all bits are set to 1 some problem occured */
464 if (flags == 0xffffffff) {
465 printf("ohci-- Houston, we have a serious problem! :(\n");
469 /* only care about interrupts that are enabled */
470 flags &= read32(OHCI0_HC_INT_ENABLE);
474 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
478 printf("OHCI Interrupt occured: ");
479 /* UnrecoverableError */
480 if (flags & OHCI_INTR_UE) {
481 printf("UnrecoverableError\n");
482 /* TODO: well, I don't know... nothing,
483 * because it won't happen anyway? ;-) */
486 /* RootHubStatusChange */
487 if (flags & OHCI_INTR_RHSC) {
488 printf("RootHubStatusChange\n");
489 /* TODO: set some next_statechange variable... */
491 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
494 else if (flags & OHCI_INTR_RD) {
495 printf("ResumeDetected\n");
496 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
497 /* TODO: figure out what the linux kernel does here... */
500 /* WritebackDoneHead */
501 if (flags & OHCI_INTR_WDH) {
502 printf("WritebackDoneHead\n");
503 /* basically the linux irq handler reverse TDs to their urbs
504 * and set done_head to null.
505 * since we are polling atm, just should do the latter task.
506 * however, this won't work for now (i don't know why...)
510 sync_before_read(&hcca_oh0, 256);
511 hcca_oh0.done_head = 0;
512 sync_after_write(&hcca_oh0, 256);
516 /* TODO: handle any pending URB/ED unlinks... */
518 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
519 if (HC_IS_RUNNING()) {
520 write32(OHCI0_HC_INT_STATUS, flags);
521 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);
527 sync_before_read(&hcca_oh0, 256);
528 printf("***** frame_no: %d *****\n", LE(hcca_oh0.frame_no));