usb/host/ohci.c

   1 /*
   2        ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
   3        ohci hardware support
   4
   5 Copyright (C) 2009     Bernhard Urban <lewurm@gmx.net>
   6 Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
   7
   8 # This code is licensed to you under the terms of the GNU GPL, version 2;
   9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
  10 */
  11
  12 #include "../../bootmii_ppc.h"
  13 #include "../../hollywood.h"
  14 #include "../../irq.h"
  15 #include "../../string.h"
  16 #include "../../malloc.h"
  17 #include "ohci.h"
  18 #include "host.h"
  19 #include "../usbspec/usb11spec.h"
  20
  21 // macro for accessing u32 variables that need to be in little endian byte order;
  22 // whenever you read or write from an u32 field that the ohci host controller
  23 // will read or write from too, use this macro for access!
  24 #define ACCESS_LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
  25                            (((dword) & 0x00FF0000) >> 8)  | \
  26                            (((dword) & 0x0000FF00) << 8)  | \
  27                            (((dword) & 0x000000FF) << 24) )
  28
  29 static struct ohci_hcca hcca_oh0;
  30
  31 static struct endpoint_descriptor *allocate_endpoint()
  32 {
  33         struct endpoint_descriptor *ep;
  34         //memalign instead of calloc doesn't work here?! WTF
  35         ep = (struct endpoint_descriptor *)memalign(sizeof(struct endpoint_descriptor), 16);
  36         ep->flags = ACCESS_LE(OHCI_ENDPOINT_GENERAL_FORMAT);
  37         ep->headp = ep->tailp = ep->nexted = ACCESS_LE(0);
  38         return ep;
  39 }
  40
  41 static struct general_td *allocate_general_td(size_t bsize)
  42 {
  43         struct general_td *td;
  44         td = (struct general_td *)memalign(sizeof(struct general_td), 16);
  45         td->flags = ACCESS_LE(0);
  46         //td->nexttd = ACCESS_LE(virt_to_phys(td));
  47         td->nexttd = ACCESS_LE(0);
  48         if(bsize == 0) {
  49                 td->cbp = td->be = ACCESS_LE(0);
  50         } else {
  51                 td->cbp = ACCESS_LE(virt_to_phys(memalign(bsize, 16))); //memailgn required here?
  52                 //td->cbp = ACCESS_LE(virt_to_phys(malloc(bsize)));
  53                 td->be = ACCESS_LE(ACCESS_LE(td->cbp) + bsize - 1);
  54         }
  55         return td;
  56 }
  57
  58 static void control_quirk()
  59 {
  60         static struct endpoint_descriptor *ed = 0; /* empty ED */
  61         static struct general_td *td = 0; /* dummy TD */
  62         u32 head;
  63         u32 current;
  64         u32 status;
  65
  66         /*
  67          * One time only.
  68          * Allocate and keep a special empty ED with just a dummy TD.
  69          */
  70         if (!ed) {
  71                 ed = allocate_endpoint();
  72                 if (!ed)
  73                         return;
  74
  75                 td = allocate_general_td(0);
  76                 if (!td) {
  77                         free(ed);
  78                         ed = NULL;
  79                         return;
  80                 }
  81
  82 #define ED_MASK ((u32)~0x0f)
  83                 ed->tailp = ed->headp = ACCESS_LE(virt_to_phys((void*) ((u32)td & ED_MASK)));
  84                 ed->flags |= ACCESS_LE(OHCI_ENDPOINT_DIRECTION_OUT);
  85         }
  86
  87         /*
  88          * The OHCI USB host controllers on the Nintendo Wii
  89          * video game console stop working when new TDs are
  90          * added to a scheduled control ED after a transfer has
  91          * has taken place on it.
  92          *
  93          * Before scheduling any new control TD, we make the
  94          * controller happy by always loading a special control ED
  95          * with a single dummy TD and letting the controller attempt
  96          * the transfer.
  97          * The controller won't do anything with it, as the special
  98          * ED has no TDs, but it will keep the controller from failing
  99          * on the next transfer.
 100          */
 101         head = read32(OHCI0_HC_CTRL_HEAD_ED);
 102         if (head) {
 103                 printf("head: 0x%08X\n", head);
 104                 /*
 105                  * Load the special empty ED and tell the controller to
 106                  * process the control list.
 107                  */
 108                 sync_after_write(ed, 16);
 109                 sync_after_write(td, 16);
 110                 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed));
 111
 112                 status = read32(OHCI0_HC_CONTROL);
 113                 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 114                 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 115
 116                 /* spin until the controller is done with the control list */
 117                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 118                 while(!current) {
 119                         udelay(10);
 120                         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 121                 }
 122
 123                 printf("current: 0x%08X\n", current);
 124
 125                 /* restore the old control head and control settings */
 126                 write32(OHCI0_HC_CONTROL, status);
 127                 write32(OHCI0_HC_CTRL_HEAD_ED, head);
 128         } else {
 129                 printf("nohead!\n");
 130         }
 131 }
 132
 133
 134 static void dbg_op_state()
 135 {
 136         switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
 137                 case OHCI_USB_SUSPEND:
 138                         printf("ohci-- OHCI_USB_SUSPEND\n");
 139                         break;
 140                 case OHCI_USB_RESET:
 141                         printf("ohci-- OHCI_USB_RESET\n");
 142                         break;
 143                 case OHCI_USB_OPER:
 144                         printf("ohci-- OHCI_USB_OPER\n");
 145                         break;
 146                 case OHCI_USB_RESUME:
 147                         printf("ohci-- OHCI_USB_RESUME\n");
 148                         break;
 149         }
 150 }
 151
 152 static void dbg_td_flag(u32 flag)
 153 {
 154         printf("**************** dbg_td_flag: 0x%08X ***************\n", flag);
 155         printf("CC: %X\tshould be 0, see page 32 (ohci spec)\n", (flag>>28)&0xf);
 156         printf("EC: %X\tsee page 20 (ohci spec)\n", (flag>>26)&3);
 157         printf(" T: %X\n", (flag>>24)&3);
 158         printf("DI: %X\n", (flag>>21)&7);
 159         printf("DP: %X\n", (flag>>19)&3);
 160         printf(" R: %X\n", (flag>>18)&1);
 161         printf("********************************************************\n");
 162 }
 163
 164
 165
 166 /**
 167  * Enqueue a transfer descriptor.
 168  */
 169 u8 hcdi_enqueue(usb_transfer_descriptor *td) {
 170         control_quirk(); //required?
 171
 172         printf( "===========================\n"
 173                         "===========================\n");
 174         sync_before_read(&hcca_oh0, 256);
 175         printf("done head (nach sync): 0x%08X\n", ACCESS_LE(hcca_oh0.done_head));
 176         printf("HCCA->frame_no: %d\nhcca->hccapad1: %d\n",
 177                         ((ACCESS_LE(hcca_oh0.frame_no) & 0xffff0000)>>16),
 178                         ACCESS_LE(hcca_oh0.frame_no)&0xffff );
 179         if(hcca_oh0.done_head) printf("WWWWWWWWOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOTTTTTTTTTTTT\n");
 180
 181         struct general_td *tmptd = allocate_general_td(td->actlen);
 182         (void) memcpy((void*) (phys_to_virt(ACCESS_LE(tmptd->cbp))), td->buffer, td->actlen);
 183
 184         tmptd->flags &= ACCESS_LE(~OHCI_TD_DIRECTION_PID_MASK);
 185         switch(td->pid) {
 186                 case USB_PID_SETUP:
 187                         printf("pid_setup\n");
 188                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_SETUP);
 189                         break;
 190                 case USB_PID_OUT:
 191                         printf("pid_out\n");
 192                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_OUT);
 193                         break;
 194                 case USB_PID_IN:
 195                         printf("pid_in\n");
 196                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_IN);
 197                         break;
 198         }
 199         tmptd->flags |= ACCESS_LE((td->togl) ? OHCI_TD_TOGGLE_1 : OHCI_TD_TOGGLE_0);
 200
 201         printf("tmptd hexdump (before) 0x%08X:\n", tmptd);
 202         hexdump(tmptd, sizeof(struct general_td));
 203         printf("tmptd->cbp hexdump (before) 0x%08X:\n", phys_to_virt(ACCESS_LE(tmptd->cbp)));
 204         hexdump((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 205
 206         sync_after_write(tmptd, sizeof(struct general_td));
 207         sync_after_write((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 208
 209         struct endpoint_descriptor *dummyconfig = allocate_endpoint();
 210
 211 #define ED_MASK2 ~0 /*((u32)~0x0f) */
 212 #define ED_MASK ((u32)~0x0f)
 213         /*dummyconfig->tailp =*/ dummyconfig->headp = ACCESS_LE(virt_to_phys((void*) ((u32)tmptd & ED_MASK)));
 214
 215         dummyconfig->flags |= ACCESS_LE(OHCI_ENDPOINT_LOW_SPEED |
 216                 OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
 217                 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
 218                 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
 219
 220         printf("dummyconfig hexdump (before) 0x%08X:\n", dummyconfig);
 221         hexdump((void*) dummyconfig, 16);
 222
 223         sync_after_write(dummyconfig, 16);
 224         write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(dummyconfig));
 225
 226         printf("OHCI_CTRL_CLE: 0x%08X || ", read32(OHCI0_HC_CONTROL)&OHCI_CTRL_CLE);
 227         printf("OHCI_CLF: 0x%08X\n", read32(OHCI0_HC_COMMAND_STATUS)&OHCI_CLF);
 228         set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 229         write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 230
 231         printf("+++++++++++++++++++++++++++++\n");
 232         /* spin until the controller is done with the control list */
 233         u32 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 234         printf("current: 0x%08X\n", current);
 235         while(!current) {
 236                 udelay(2);
 237                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 238         }
 239
 240         udelay(20000);
 241         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 242         printf("current: 0x%08X\n", current);
 243         printf("+++++++++++++++++++++++++++++\n");
 244         udelay(20000);
 245
 246
 247         sync_before_read(tmptd, sizeof(struct general_td));
 248         printf("tmptd hexdump (after) 0x%08X:\n", tmptd);
 249         hexdump(tmptd, sizeof(struct general_td));
 250         dbg_td_flag(ACCESS_LE(tmptd->flags));
 251
 252         sync_before_read((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 253         printf("tmptd->cbp hexdump (after) 0x%08X:\n", phys_to_virt(ACCESS_LE(tmptd->cbp)));
 254         hexdump((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 255
 256         sync_before_read(dummyconfig, 16);
 257         printf("dummyconfig hexdump (after) 0x%08X:\n", dummyconfig);
 258         hexdump((void*) dummyconfig, 16);
 259
 260         sync_before_read(&hcca_oh0, 256);
 261         printf("done head (nach sync): 0x%08X\n", ACCESS_LE(hcca_oh0.done_head));
 262
 263         //should be free'd after taking it from the done queue
 264         //free(tmptd);
 265         return 0;
 266 }
 267
 268 /**
 269  * Remove an transfer descriptor from transfer queue.
 270  */
 271 u8 hcdi_dequeue(usb_transfer_descriptor *td) {
 272         return 0;
 273 }
 274
 275 void hcdi_init()
 276 {
 277         printf("ohci-- init\n");
 278         dbg_op_state();
 279
 280         /* disable hc interrupts */
 281         set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
 282
 283         /* save fmInterval and calculate FSMPS */
 284 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
 285 #define FI 0x2edf /* 12000 bits per frame (-1) */
 286         u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
 287         if(fmint != FI)
 288                 printf("ohci-- fminterval delta: %d\n", fmint - FI);
 289         fmint |= FSMP (fmint) << 16;
 290
 291         /* enable interrupts of both usb host controllers */
 292         set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
 293
 294         /* reset HC */
 295         write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
 296
 297         /* wait max. 30us */
 298         u32 ts = 30;
 299         while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
 300                  if(--ts == 0) {
 301                         printf("ohci-- FAILED");
 302                         return;
 303                  }
 304                  udelay(1);
 305         }
 306
 307         /* disable interrupts; 2ms timelimit here!
 308            now we're in the SUSPEND state ... must go OPERATIONAL
 309            within 2msec else HC enters RESUME */
 310
 311         u32 cookie = irq_kill();
 312
 313         /* Tell the controller where the control and bulk lists are
 314          * The lists are empty now. */
 315         write32(OHCI0_HC_CTRL_HEAD_ED, 0);
 316         write32(OHCI0_HC_BULK_HEAD_ED, 0);
 317
 318         /* set hcca adress */
 319         sync_after_write(&hcca_oh0, 256);
 320         write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
 321
 322         /* set periodicstart */
 323 #define FIT (1<<31)
 324         u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
 325         u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
 326
 327         write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
 328         write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
 329
 330         /* testing bla */
 331         if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
 332                 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
 333         }
 334
 335         /* start HC operations */
 336         write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
 337
 338         /* wake on ConnectStatusChange, matching external hubs */
 339         set32(OHCI0_HC_RH_STATUS, RH_HS_DRWE);
 340
 341         /* Choose the interrupts we care about now, others later on demand */
 342         write32(OHCI0_HC_INT_STATUS, ~0);
 343         write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
 344
 345         irq_restore(cookie);
 346
 347         dbg_op_state();
 348 }
 349
 350 void hcdi_irq()
 351 {
 352         /* read interrupt status */
 353         u32 flags = read32(OHCI0_HC_INT_STATUS);
 354
 355         /* when all bits are set to 1 some problem occured */
 356         if (flags == 0xffffffff) {
 357                 printf("ohci-- Houston, we have a serious problem! :(\n");
 358                 return;
 359         }
 360
 361         /* only care about interrupts that are enabled */
 362         flags &= read32(OHCI0_HC_INT_ENABLE);
 363
 364         /* nothing to do? */
 365         if (flags == 0) {
 366                 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
 367                 return;
 368         }
 369
 370         printf("OHCI Interrupt occured: ");
 371         /* UnrecoverableError */
 372         if (flags & OHCI_INTR_UE) {
 373                 printf("UnrecoverableError\n");
 374                 /* TODO: well, I don't know... nothing,
 375                  *       because it won't happen anyway? ;-) */
 376         }
 377
 378         /* RootHubStatusChange */
 379         if (flags & OHCI_INTR_RHSC) {
 380                 printf("RootHubStatusChange\n");
 381                 /* TODO: set some next_statechange variable... */
 382                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
 383         }
 384         /* ResumeDetected */
 385         else if (flags & OHCI_INTR_RD) {
 386                 printf("ResumeDetected\n");
 387                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
 388                 /* TODO: figure out what the linux kernel does here... */
 389         }
 390
 391         /* WritebackDoneHead */
 392         if (flags & OHCI_INTR_WDH) {
 393                 printf("WritebackDoneHead\n");
 394                 /* basically the linux irq handler reverse TDs to their urbs
 395                  * and set done_head to null.
 396                  * since we are polling atm, just should do the latter task.
 397                  * however, this won't work for now (i don't know why...)
 398                  * TODO!
 399                  */
 400 #if 0
 401                 sync_before_read(&hcca_oh0, 256);
 402                 hcca_oh0.done_head = 0;
 403                 sync_after_write(&hcca_oh0, 256);
 404 #endif
 405         }
 406
 407         /* TODO: handle any pending URB/ED unlinks... */
 408
 409 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
 410         if (HC_IS_RUNNING()) {
 411                 write32(OHCI0_HC_INT_STATUS, flags);
 412                 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);
 413         }
 414 }
 415