usb/host/ohci.c

   1 /*
   2        ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
   3        ohci hardware support
   4
   5 Copyright (C) 2009     Bernhard Urban <lewurm@gmx.net>
   6 Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
   7
   8 # This code is licensed to you under the terms of the GNU GPL, version 2;
   9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
  10 */
  11
  12 #include "../../bootmii_ppc.h"
  13 #include "../../hollywood.h"
  14 #include "../../irq.h"
  15 #include "../../string.h"
  16 #include "../../malloc.h"
  17 #include "ohci.h"
  18 #include "host.h"
  19 #include "../usbspec/usb11spec.h"
  20
  21 // macro for accessing u32 variables that need to be in little endian byte order;
  22 // whenever you read or write from an u32 field that the ohci host controller
  23 // will read or write from too, use this macro for access!
  24 #define ACCESS_LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
  25                            (((dword) & 0x00FF0000) >> 8)  | \
  26                            (((dword) & 0x0000FF00) << 8)  | \
  27                            (((dword) & 0x000000FF) << 24) )
  28
  29 static struct endpoint_descriptor *allocate_endpoint();
  30 static struct general_td *allocate_general_td(size_t);
  31 static void control_quirk();
  32 static void dbg_op_state();
  33 static void dbg_td_flag(u32 flag);
  34 static void configure_ports(u8 from_init);
  35 static void setup_port(u32 reg, u8 from_init);
  36
  37 static struct ohci_hcca hcca_oh0;
  38
  39
  40 static struct endpoint_descriptor *allocate_endpoint()
  41 {
  42         struct endpoint_descriptor *ep;
  43         ep = (struct endpoint_descriptor *)memalign(16, sizeof(struct endpoint_descriptor));
  44         ep->flags = ACCESS_LE(OHCI_ENDPOINT_GENERAL_FORMAT);
  45         ep->headp = ep->tailp = ep->nexted = ACCESS_LE(0);
  46         return ep;
  47 }
  48
  49 static struct general_td *allocate_general_td(size_t bsize)
  50 {
  51         struct general_td *td;
  52         td = (struct general_td *)memalign(16, sizeof(struct general_td));
  53         td->flags = ACCESS_LE(0);
  54         // TODO !! nexttd?
  55         td->nexttd = ACCESS_LE(virt_to_phys(td));
  56         //td->nexttd = ACCESS_LE(0);
  57         if(bsize == 0) {
  58                 td->cbp = td->be = ACCESS_LE(0);
  59         } else {
  60                 td->cbp = ACCESS_LE(virt_to_phys(memalign(16, bsize))); //memailgn required here?
  61                 //td->cbp = ACCESS_LE(virt_to_phys(malloc(bsize)));
  62                 td->be = ACCESS_LE(ACCESS_LE(td->cbp) + bsize - 1);
  63         }
  64         return td;
  65 }
  66
  67 static void control_quirk()
  68 {
  69         static struct endpoint_descriptor *ed = 0; /* empty ED */
  70         static struct general_td *td = 0; /* dummy TD */
  71         u32 head;
  72         u32 current;
  73         u32 status;
  74
  75         /*
  76          * One time only.
  77          * Allocate and keep a special empty ED with just a dummy TD.
  78          */
  79         if (!ed) {
  80                 ed = allocate_endpoint();
  81                 if (!ed)
  82                         return;
  83
  84                 td = allocate_general_td(0);
  85                 if (!td) {
  86                         free(ed);
  87                         ed = NULL;
  88                         return;
  89                 }
  90
  91 #define ED_MASK ((u32)~0x0f)
  92                 ed->tailp = ed->headp = ACCESS_LE(virt_to_phys((void*) ((u32)td & ED_MASK)));
  93                 ed->flags |= ACCESS_LE(OHCI_ENDPOINT_DIRECTION_OUT);
  94         }
  95
  96         /*
  97          * The OHCI USB host controllers on the Nintendo Wii
  98          * video game console stop working when new TDs are
  99          * added to a scheduled control ED after a transfer has
 100          * has taken place on it.
 101          *
 102          * Before scheduling any new control TD, we make the
 103          * controller happy by always loading a special control ED
 104          * with a single dummy TD and letting the controller attempt
 105          * the transfer.
 106          * The controller won't do anything with it, as the special
 107          * ED has no TDs, but it will keep the controller from failing
 108          * on the next transfer.
 109          */
 110         head = read32(OHCI0_HC_CTRL_HEAD_ED);
 111         if (head) {
 112                 printf("head: 0x%08X\n", head);
 113                 /*
 114                  * Load the special empty ED and tell the controller to
 115                  * process the control list.
 116                  */
 117                 sync_after_write(ed, 16);
 118                 sync_after_write(td, 16);
 119                 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed));
 120
 121                 status = read32(OHCI0_HC_CONTROL);
 122                 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 123                 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 124
 125                 /* spin until the controller is done with the control list */
 126                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 127                 while(!current) {
 128                         udelay(10);
 129                         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 130                 }
 131
 132                 printf("current: 0x%08X\n", current);
 133
 134                 /* restore the old control head and control settings */
 135                 write32(OHCI0_HC_CONTROL, status);
 136                 write32(OHCI0_HC_CTRL_HEAD_ED, head);
 137         } else {
 138                 printf("nohead!\n");
 139         }
 140 }
 141
 142
 143 static void dbg_op_state()
 144 {
 145         switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
 146                 case OHCI_USB_SUSPEND:
 147                         printf("ohci-- OHCI_USB_SUSPEND\n");
 148                         break;
 149                 case OHCI_USB_RESET:
 150                         printf("ohci-- OHCI_USB_RESET\n");
 151                         break;
 152                 case OHCI_USB_OPER:
 153                         printf("ohci-- OHCI_USB_OPER\n");
 154                         break;
 155                 case OHCI_USB_RESUME:
 156                         printf("ohci-- OHCI_USB_RESUME\n");
 157                         break;
 158         }
 159 }
 160
 161 static void dbg_td_flag(u32 flag)
 162 {
 163         printf("**************** dbg_td_flag: 0x%08X ***************\n", flag);
 164         printf("CC: %X\tshould be 0, see page 32 (ohci spec)\n", (flag>>28)&0xf);
 165         printf("EC: %X\tsee page 20 (ohci spec)\n", (flag>>26)&3);
 166         printf(" T: %X\n", (flag>>24)&3);
 167         printf("DI: %X\n", (flag>>21)&7);
 168         printf("DP: %X\n", (flag>>19)&3);
 169         printf(" R: %X\n", (flag>>18)&1);
 170         printf("********************************************************\n");
 171 }
 172
 173
 174
 175 /**
 176  * Enqueue a transfer descriptor.
 177  */
 178 u8 hcdi_enqueue(usb_transfer_descriptor *td) {
 179         control_quirk(); //required? YES! :O
 180         u32 tmptdbuffer;
 181
 182         static struct endpoint_descriptor dummyconfig;
 183         dummyconfig.flags = ACCESS_LE(OHCI_ENDPOINT_GENERAL_FORMAT);
 184         dummyconfig.headp = dummyconfig.tailp = dummyconfig.nexted = ACCESS_LE(0);
 185
 186         printf( "===========================\n"
 187                         "===========================\n");
 188         sync_before_read(&hcca_oh0, 256);
 189         printf("done head (nach sync): 0x%08X\n", ACCESS_LE(hcca_oh0.done_head));
 190         printf("HCCA->frame_no: %d\nhcca->hccapad1: %d\n",
 191                         ((ACCESS_LE(hcca_oh0.frame_no) & 0xffff)>>16),
 192                         ACCESS_LE(hcca_oh0.frame_no)&0x0000ffff );
 193
 194         struct general_td *tmptd = allocate_general_td(td->actlen);
 195         (void) memcpy((void*) (phys_to_virt(ACCESS_LE(tmptd->cbp))), td->buffer, td->actlen);
 196
 197         tmptd->flags &= ACCESS_LE(~OHCI_TD_DIRECTION_PID_MASK);
 198         switch(td->pid) {
 199                 case USB_PID_SETUP:
 200                         printf("pid_setup\n");
 201                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_SETUP);
 202                         break;
 203                 case USB_PID_OUT:
 204                         printf("pid_out\n");
 205                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_OUT);
 206                         break;
 207                 case USB_PID_IN:
 208                         printf("pid_in\n");
 209                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_IN);
 210                         break;
 211         }
 212         tmptd->flags |= ACCESS_LE((td->togl) ? OHCI_TD_TOGGLE_1 : OHCI_TD_TOGGLE_0);
 213
 214         printf("tmptd hexdump (before) 0x%08X:\n", tmptd);
 215         hexdump(tmptd, sizeof(struct general_td));
 216         //save buffer adress here; HC may change tmptd->cbp
 217         tmptdbuffer = phys_to_virt(ACCESS_LE(tmptd->cbp));
 218         printf("tmptd->cbp hexdump (before) 0x%08X:\n", phys_to_virt(ACCESS_LE(tmptd->cbp)));
 219         hexdump((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 220
 221         sync_after_write(tmptd, sizeof(struct general_td));
 222         sync_after_write((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 223
 224 #define ED_MASK ((u32)~0x0f)
 225         dummyconfig.headp = ACCESS_LE(virt_to_phys((void*) ((u32)tmptd & ED_MASK)));
 226
 227         dummyconfig.flags |= ACCESS_LE(OHCI_ENDPOINT_LOW_SPEED |
 228                 OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
 229                 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
 230                 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
 231
 232         printf("dummyconfig hexdump (before) 0x%08X:\n", &dummyconfig);
 233         hexdump((void*) &dummyconfig, 16);
 234
 235         sync_after_write(&dummyconfig, 16);
 236         write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(&dummyconfig));
 237
 238         printf("OHCI_CTRL_CLE: 0x%08X || ", read32(OHCI0_HC_CONTROL)&OHCI_CTRL_CLE);
 239         printf("OHCI_CLF: 0x%08X\n", read32(OHCI0_HC_COMMAND_STATUS)&OHCI_CLF);
 240         set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 241         write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 242
 243         printf("+++++++++++++++++++++++++++++\n");
 244         /* spin until the controller is done with the control list */
 245         u32 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 246         printf("current: 0x%08X\n", current);
 247
 248         //don't use this quirk stuff here!
 249 #if 0
 250         while(!current) {
 251                 udelay(2);
 252                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 253         }
 254 #endif
 255
 256         udelay(20000);
 257         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 258         printf("current: 0x%08X\n", current);
 259         printf("+++++++++++++++++++++++++++++\n");
 260         udelay(20000);
 261
 262         sync_before_read(tmptd, sizeof(struct general_td));
 263         printf("tmptd hexdump (after) 0x%08X:\n", tmptd);
 264         hexdump(tmptd, sizeof(struct general_td));
 265         dbg_td_flag(ACCESS_LE(tmptd->flags));
 266
 267         sync_before_read((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 268         printf("tmptd->cbp hexdump (after) 0x%08X:\n", phys_to_virt(ACCESS_LE(tmptd->cbp)));
 269         hexdump((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 270
 271         sync_before_read(&dummyconfig, 16);
 272         printf("dummyconfig hexdump (after) 0x%08X:\n", &dummyconfig);
 273         hexdump((void*) &dummyconfig, 16);
 274
 275         sync_before_read(&hcca_oh0, 256);
 276         printf("done head (nach sync): 0x%08X\n", ACCESS_LE(hcca_oh0.done_head));
 277
 278         struct general_td* donetd = phys_to_virt(ACCESS_LE(hcca_oh0.done_head)&~1);
 279         sync_before_read(donetd, 16);
 280         printf("done head hexdump: 0x%08X\n", donetd);
 281         hexdump((void*) donetd, 16);
 282
 283         sync_before_read((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 284         (void) memcpy((void*) (td->buffer), phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 285
 286         write32(OHCI0_HC_CONTROL, read32(OHCI0_HC_CONTROL)&~OHCI_CTRL_CLE);
 287         dummyconfig.headp = dummyconfig.tailp = dummyconfig.nexted = ACCESS_LE(0);
 288
 289
 290         /*
 291          * TD should be free'd after taking it from the done queue.
 292          * but we are very very dirty and do it anyway :p
 293          */
 294
 295         /* only when a buffer is allocated */
 296         if(td->actlen)
 297                 free((void*)tmptdbuffer);
 298         free(tmptd);
 299         return 0;
 300 }
 301
 302 /**
 303  * Remove an transfer descriptor from transfer queue.
 304  */
 305 u8 hcdi_dequeue(usb_transfer_descriptor *td) {
 306         return 0;
 307 }
 308
 309 void hcdi_init()
 310 {
 311         printf("ohci-- init\n");
 312         dbg_op_state();
 313
 314         /* disable hc interrupts */
 315         set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
 316
 317         /* save fmInterval and calculate FSMPS */
 318 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
 319 #define FI 0x2edf /* 12000 bits per frame (-1) */
 320         u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
 321         if(fmint != FI)
 322                 printf("ohci-- fminterval delta: %d\n", fmint - FI);
 323         fmint |= FSMP (fmint) << 16;
 324
 325         /* enable interrupts of both usb host controllers */
 326         set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
 327
 328         /* reset HC */
 329         write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
 330
 331         /* wait max. 30us */
 332         u32 ts = 30;
 333         while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
 334                  if(--ts == 0) {
 335                         printf("ohci-- FAILED");
 336                         return;
 337                  }
 338                  udelay(1);
 339         }
 340
 341         /* disable interrupts; 2ms timelimit here!
 342            now we're in the SUSPEND state ... must go OPERATIONAL
 343            within 2msec else HC enters RESUME */
 344
 345         u32 cookie = irq_kill();
 346
 347         /* Tell the controller where the control and bulk lists are
 348          * The lists are empty now. */
 349         write32(OHCI0_HC_CTRL_HEAD_ED, 0);
 350         write32(OHCI0_HC_BULK_HEAD_ED, 0);
 351
 352         /* set hcca adress */
 353         sync_after_write(&hcca_oh0, 256);
 354         write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
 355
 356         /* set periodicstart */
 357 #define FIT (1<<31)
 358         u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
 359         u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
 360
 361         write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
 362         write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
 363
 364         /* testing bla */
 365         if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
 366                 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
 367         }
 368
 369         /* start HC operations */
 370         write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
 371
 372         /* wake on ConnectStatusChange, matching external hubs */
 373         write32(OHCI0_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC);
 374
 375         /* Choose the interrupts we care about now, others later on demand */
 376         write32(OHCI0_HC_INT_STATUS, ~0);
 377         write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
 378
 379         //wtf?
 380         wait_ms ((read32(OHCI0_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe);
 381
 382         configure_ports((u8)1);
 383         irq_restore(cookie);
 384
 385         dbg_op_state();
 386 }
 387
 388 static void configure_ports(u8 from_init)
 389 {
 390         printf("OHCI0_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_A));
 391         printf("OHCI0_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_B));
 392         printf("OHCI0_HC_RH_STATUS:\t\t0x%08X\n", read32(OHCI0_HC_RH_STATUS));
 393         printf("OHCI0_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_1));
 394         printf("OHCI0_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_2));
 395
 396         setup_port(OHCI0_HC_RH_PORT_STATUS_1, from_init);
 397         setup_port(OHCI0_HC_RH_PORT_STATUS_2, from_init);
 398         printf("configure_ports done\n");
 399 }
 400
 401 static void setup_port(u32 reg, u8 from_init)
 402 {
 403         u32 port = read32(reg);
 404         if((port & RH_PS_CCS) && ((port & RH_PS_CSC) || from_init)) {
 405                 write32(reg, RH_PS_CSC);
 406
 407                 wait_ms(150);
 408
 409                 /* clear CSC flag, set PES and start port reset (PRS) */
 410                 write32(reg, RH_PS_PES);
 411                 while(!(read32(reg) & RH_PS_PES)) {
 412                         printf("fu\n");
 413                         return;
 414                 }
 415
 416                 write32(reg, RH_PS_PRS);
 417
 418                 /* spin until port reset is complete */
 419                 while(!(read32(reg) & RH_PS_PRSC)); // hint: it may stuck here
 420                 printf("loop done\n");
 421
 422                 (void) usb_add_device();
 423         }
 424 }
 425
 426 void hcdi_irq()
 427 {
 428         /* read interrupt status */
 429         u32 flags = read32(OHCI0_HC_INT_STATUS);
 430
 431         /* when all bits are set to 1 some problem occured */
 432         if (flags == 0xffffffff) {
 433                 printf("ohci-- Houston, we have a serious problem! :(\n");
 434                 return;
 435         }
 436
 437         /* only care about interrupts that are enabled */
 438         flags &= read32(OHCI0_HC_INT_ENABLE);
 439
 440         /* nothing to do? */
 441         if (flags == 0) {
 442                 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
 443                 return;
 444         }
 445
 446         printf("OHCI Interrupt occured: ");
 447         /* UnrecoverableError */
 448         if (flags & OHCI_INTR_UE) {
 449                 printf("UnrecoverableError\n");
 450                 /* TODO: well, I don't know... nothing,
 451                  *       because it won't happen anyway? ;-) */
 452         }
 453
 454         /* RootHubStatusChange */
 455         if (flags & OHCI_INTR_RHSC) {
 456                 printf("RootHubStatusChange\n");
 457                 /* TODO: set some next_statechange variable... */
 458                 configure_ports(0);
 459                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
 460         }
 461         /* ResumeDetected */
 462         else if (flags & OHCI_INTR_RD) {
 463                 printf("ResumeDetected\n");
 464                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
 465                 /* TODO: figure out what the linux kernel does here... */
 466         }
 467
 468         /* WritebackDoneHead */
 469         if (flags & OHCI_INTR_WDH) {
 470                 printf("WritebackDoneHead\n");
 471                 /* basically the linux irq handler reverse TDs to their urbs
 472                  * and set done_head to null.
 473                  * since we are polling atm, just should do the latter task.
 474                  * however, this won't work for now (i don't know why...)
 475                  * TODO!
 476                  */
 477 #if 0
 478                 sync_before_read(&hcca_oh0, 256);
 479                 hcca_oh0.done_head = 0;
 480                 sync_after_write(&hcca_oh0, 256);
 481 #endif
 482         }
 483
 484         /* TODO: handle any pending URB/ED unlinks... */
 485
 486 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
 487         if (HC_IS_RUNNING()) {
 488                 write32(OHCI0_HC_INT_STATUS, flags);
 489                 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);
 490         }
 491 }
 492
 493 void show_frame_no()
 494 {
 495         sync_before_read(&hcca_oh0, 256);
 496         printf("***** frame_no: %d *****\n", ACCESS_LE(hcca_oh0.frame_no));
 497 }