8 #define OHCI0_REG_BASE 0xd050000
10 #define OHCI0_HC_REVISION (OHCI0_REG_BASE + 0x00)
11 #define OHCI0_HC_CONTROL (OHCI0_REG_BASE + 0x04)
12 #define OHCI0_HC_COMMAND_STATUS (OHCI0_REG_BASE + 0x08)
13 #define OHCI0_HC_INT_STATUS (OHCI0_REG_BASE + 0x0C)
15 #define OHCI0_HC_INT_ENABLE (OHCI0_REG_BASE + 0x10)
16 #define OHCI0_HC_INT_DISABLE (OHCI0_REG_BASE + 0x14)
17 #define OHCI0_HC_HCCA (OHCI0_REG_BASE + 0x18)
18 #define OHCI0_HC_PERIOD_CURRENT_ED (OHCI0_REG_BASE + 0x1C)
20 #define OHCI0_HC_CTRL_HEAD_ED (OHCI0_REG_BASE + 0x20)
21 #define OHCI0_HC_CTRL_CURRENT_ED (OHCI0_REG_BASE + 0x24)
22 #define OHCI0_HC_BULK_HEAD_ED (OHCI0_REG_BASE + 0x28)
23 #define OHCI0_HC_BULK_CURRENT_ED (OHCI0_REG_BASE + 0x2C)
25 #define OHCI0_HC_DONE_HEAD (OHCI0_REG_BASE + 0x30)
26 #define OHCI0_HC_FM_INTERVAL (OHCI0_REG_BASE + 0x34)
27 #define OHCI0_HC_FM_REMAINING (OHCI0_REG_BASE + 0x38)
28 #define OHCI0_HC_FM_NUMBER (OHCI0_REG_BASE + 0x3C)
30 #define OHCI0_HC_PERIODIC_START (OHCI0_REG_BASE + 0x40)
31 #define OHCI0_HC_LS_THRESHOLD (OHCI0_REG_BASE + 0x44)
32 #define OHCI0_HC_RH_DESCRIPTOR_A (OHCI0_REG_BASE + 0x48)
33 #define OHCI0_HC_RH_DESCRIPTOR_B (OHCI0_REG_BASE + 0x4C)
35 #define OHCI0_HC_RH_STATUS (OHCI0_REG_BASE + 0x50)
40 #define OHCI1_REG_BASE 0xd060000
42 #define OHCI1_HC_REVISION (OHCI1_REG_BASE + 0x00)
43 #define OHCI1_HC_CONTROL (OHCI1_REG_BASE + 0x04)
44 #define OHCI1_HC_COMMAND_STATUS (OHCI1_REG_BASE + 0x08)
45 #define OHCI1_HC_INT_STATUS (OHCI1_REG_BASE + 0x0C)
47 #define OHCI1_HC_INT_ENABLE (OHCI1_REG_BASE + 0x10)
48 #define OHCI1_HC_INT_DISABLE (OHCI1_REG_BASE + 0x14)
49 #define OHCI1_HC_HCCA (OHCI1_REG_BASE + 0x18)
50 #define OHCI1_HC_PERIOD_CURRENT_ED (OHCI1_REG_BASE + 0x1C)
52 #define OHCI1_HC_CTRL_HEAD_ED (OHCI1_REG_BASE + 0x20)
53 #define OHCI1_HC_CTRL_CURRENT_ED (OHCI1_REG_BASE + 0x24)
54 #define OHCI1_HC_BULK_HEAD_ED (OHCI1_REG_BASE + 0x28)
55 #define OHCI1_HC_BULK_CURRENT_ED (OHCI1_REG_BASE + 0x2C)
57 #define OHCI1_HC_DONE_HEAD (OHCI1_REG_BASE + 0x30)
58 #define OHCI1_HC_FM_INTERVAL (OHCI1_REG_BASE + 0x34)
59 #define OHCI1_HC_FM_REMAINING (OHCI1_REG_BASE + 0x38)
60 #define OHCI1_HC_FM_NUMBER (OHCI1_REG_BASE + 0x3C)
62 #define OHCI1_HC_PERIODIC_START (OHCI1_REG_BASE + 0x40)
63 #define OHCI1_HC_LS_THRESHOLD (OHCI1_REG_BASE + 0x44)
64 #define OHCI1_HC_RH_DESCRIPTOR_A (OHCI1_REG_BASE + 0x48)
65 #define OHCI1_HC_RH_DESCRIPTOR_B (OHCI1_REG_BASE + 0x4C)
67 #define OHCI1_HC_RH_STATUS (OHCI1_REG_BASE + 0x50)
70 #define EHCI_REG_BASE 0xd040000
72 /* stolen from mikep2 patched linux kernel: drivers/usb/host/ohci-mipc.c */
73 #define EHCI_CTL (EHCI_REG_BASE + 0xCC)
74 #define EHCI_CTL_OH0INTE (1<<11) /* oh0 interrupt enable */
75 #define EHCI_CTL_OH1INTE (1<<12) /* oh1 interrupt enable */
77 /* stolen from drivers/usb/host/ohci.h (linux-kernel) :) */
79 /* OHCI CONTROL AND STATUS REGISTER MASKS */
82 * HcControl (control) register masks
84 #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
85 #define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
86 #define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
87 #define OHCI_CTRL_CLE (1 << 4) /* control list enable */
88 #define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
89 #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
90 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
91 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
92 #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
94 /* pre-shifted values for HCFS */
95 #define OHCI_USB_RESET (0 << 6)
96 #define OHCI_USB_RESUME (1 << 6)
97 #define OHCI_USB_OPER (2 << 6)
98 #define OHCI_USB_SUSPEND (3 << 6)
101 * HcCommandStatus (cmdstatus) register masks
103 #define OHCI_HCR (1 << 0) /* host controller reset */
104 #define OHCI_CLF (1 << 1) /* control list filled */
105 #define OHCI_BLF (1 << 2) /* bulk list filled */
106 #define OHCI_OCR (1 << 3) /* ownership change request */
107 #define OHCI_SOC (3 << 16) /* scheduling overrun count */
110 * masks used with interrupt registers:
111 * HcInterruptStatus (intrstatus)
112 * HcInterruptEnable (intrenable)
113 * HcInterruptDisable (intrdisable)
115 #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
116 #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
117 #define OHCI_INTR_SF (1 << 2) /* start frame */
118 #define OHCI_INTR_RD (1 << 3) /* resume detect */
119 #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
120 #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
121 #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
122 #define OHCI_INTR_OC (1 << 30) /* ownership change */
123 #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
126 * masks used with interrupt registers:
127 * HcInterruptStatus (intrstatus)
128 * HcInterruptEnable (intrenable)
129 * HcInterruptDisable (intrdisable)
131 #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
132 #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
133 #define OHCI_INTR_SF (1 << 2) /* start frame */
134 #define OHCI_INTR_RD (1 << 3) /* resume detect */
135 #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
136 #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
137 #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
138 #define OHCI_INTR_OC (1 << 30) /* ownership change */
139 #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
142 /* For initializing controller (mask in an HCFS mode too) */
143 #define OHCI_CONTROL_INIT (3 << 0)
144 #define OHCI_INTR_INIT \
145 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
146 | OHCI_INTR_RD | OHCI_INTR_WDH)
148 /* OHCI ROOT HUB REGISTER MASKS */
150 /* roothub.portstatus [i] bits */
151 #define RH_PS_CCS 0x00000001 /* current connect status */
152 #define RH_PS_PES 0x00000002 /* port enable status*/
153 #define RH_PS_PSS 0x00000004 /* port suspend status */
154 #define RH_PS_POCI 0x00000008 /* port over current indicator */
155 #define RH_PS_PRS 0x00000010 /* port reset status */
156 #define RH_PS_PPS 0x00000100 /* port power status */
157 #define RH_PS_LSDA 0x00000200 /* low speed device attached */
158 #define RH_PS_CSC 0x00010000 /* connect status change */
159 #define RH_PS_PESC 0x00020000 /* port enable status change */
160 #define RH_PS_PSSC 0x00040000 /* port suspend status change */
161 #define RH_PS_OCIC 0x00080000 /* over current indicator change */
162 #define RH_PS_PRSC 0x00100000 /* port reset status change */
164 /* roothub.status bits */
165 #define RH_HS_LPS 0x00000001 /* local power status */
166 #define RH_HS_OCI 0x00000002 /* over current indicator */
167 #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
168 #define RH_HS_LPSC 0x00010000 /* local power status change */
169 #define RH_HS_OCIC 0x00020000 /* over current indicator change */
170 #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
172 /* roothub.b masks */
173 #define RH_B_DR 0x0000ffff /* device removable flags */
174 #define RH_B_PPCM 0xffff0000 /* port power control mask */
176 /* roothub.a masks */
177 #define RH_A_NDP (0xff << 0) /* number of downstream ports */
178 #define RH_A_PSM (1 << 8) /* power switching mode */
179 #define RH_A_NPS (1 << 9) /* no power switching */
180 #define RH_A_DT (1 << 10) /* device type (mbz) */
181 #define RH_A_OCPM (1 << 11) /* over current protection mode */
182 #define RH_A_NOCP (1 << 12) /* no over current protection */
183 #define RH_A_POTPGT (0xff << 24) /* power on to power good time */
187 u32 int_table[NUM_INITS]; /* periodic schedule */
189 * OHCI defines u16 frame_no, followed by u16 zero pad.
190 * Since some processors can't do 16 bit bus accesses,
191 * portable access must be a 32 bits wide.
193 u32 frame_no; /* current frame number */
194 u32 done_head; /* info returned for an interrupt */
195 u8 reserved_for_hc [116];
196 u8 what [4]; /* spec only identifies 252 bytes :) */
199 void ohci_init(void);