ohci.c

   1 /*
   2        mini - a Free Software replacement for the Nintendo/BroadOn IOS.
   3        ohci hardware support
   4
   5 Copyright (C) 2009     Bernhard Urban <lewurm@gmx.net>
   6 Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
   7
   8 # This code is licensed to you under the terms of the GNU GPL, version 2;
   9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
  10 */
  11
  12 #include "bootmii_ppc.h"
  13 #include "ohci.h"
  14 #include "irq.h"
  15 #include "string.h"
  16
  17 #define gecko_printf printf
  18 #define dma_addr(address) virt_to_phys(address)
  19
  20
  21 static struct ohci_hcca hcca_oh0;
  22
  23 static void dbg_op_state() {
  24        switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
  25                case OHCI_USB_SUSPEND:
  26                        gecko_printf("ohci-- OHCI_USB_SUSPEND\n");
  27                        break;
  28                case OHCI_USB_RESET:
  29                        gecko_printf("ohci-- OHCI_USB_RESET\n");
  30                        break;
  31                case OHCI_USB_OPER:
  32                        gecko_printf("ohci-- OHCI_USB_OPER\n");
  33                        break;
  34                case OHCI_USB_RESUME:
  35                        gecko_printf("ohci-- OHCI_USB_RESUME\n");
  36                        break;
  37        }
  38 }
  39
  40 void ohci_init() {
  41        gecko_printf("ohci-- init\n");
  42        dbg_op_state();
  43
  44        /* disable hc interrupts */
  45        set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
  46
  47        /* save fmInterval and calculate FSMPS */
  48 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
  49 #define FI 0x2edf /* 12000 bits per frame (-1) */
  50        u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
  51        if(fmint != FI)
  52                gecko_printf("ohci-- fminterval delta: %d\n", fmint - FI);
  53        fmint |= FSMP (fmint) << 16;
  54
  55        /* enable interrupts of both usb host controllers */
  56        set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
  57
  58
  59
  60            u32 temp = 0;
  61            u32 hcctrl = read32(OHCI0_HC_CONTROL);
  62            switch(hcctrl & OHCI_CTRL_HCFS) {
  63                    case OHCI_USB_OPER:
  64                            temp = 0;
  65                            break;
  66                    case OHCI_USB_SUSPEND:
  67                    case OHCI_USB_RESUME:
  68                            hcctrl &= OHCI_CTRL_RWC;
  69                            hcctrl |= OHCI_USB_RESUME;
  70                            temp = 10;
  71                            break;
  72                    case OHCI_USB_RESET:
  73                            hcctrl &= OHCI_CTRL_RWC;
  74                            hcctrl |= OHCI_USB_RESET;
  75                            temp = 50;
  76                            break;
  77            }
  78            write32(OHCI0_HC_CONTROL, hcctrl);
  79            (void) read32(OHCI0_HC_CONTROL);
  80            udelay(temp*1000);
  81
  82            memset(&hcca_oh0, 0, sizeof(struct ohci_hcca));
  83
  84
  85        dbg_op_state();
  86
  87
  88        /* reset HC */
  89        write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
  90
  91        /* wait max. 30us */
  92        u32 ts = 30;
  93        while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
  94                if(--ts == 0) {
  95                        gecko_printf("ohci-- FAILED");
  96                        return;
  97                }
  98                udelay(1);
  99        }
 100
 101        /* disable interrupts; 2ms timelimit here!
 102           now we're in the SUSPEND state ... must go OPERATIONAL
 103           within 2msec else HC enters RESUME */
 104
 105
 106            u32 cookie = irq_kill();
 107
 108        /* Tell the controller where the control and bulk lists are
 109         * The lists are empty now. */
 110        write32(OHCI0_HC_CTRL_HEAD_ED, 0);
 111        write32(OHCI0_HC_BULK_HEAD_ED, 0);
 112
 113        /* set hcca adress */
 114        write32(OHCI0_HC_HCCA, dma_addr(&hcca_oh0));
 115
 116        /* set periodicstart */
 117 #define FIT (1<<31)
 118        u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
 119            u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
 120
 121        write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
 122        write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
 123
 124        /* testing bla */
 125        if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
 126                gecko_printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
 127        }
 128
 129        /* start HC operations */
 130        write32(OHCI0_HC_CONTROL, (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_RWC) | OHCI_CONTROL_INIT | OHCI_USB_OPER);
 131
 132        /* wake on ConnectStatusChange, matching external hubs */
 133        set32(OHCI0_HC_RH_STATUS, RH_HS_DRWE);
 134
 135        /* Choose the interrupts we care about now, others later on demand */
 136        write32(OHCI0_HC_INT_STATUS, ~0);
 137        write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
 138
 139
 140        irq_restore(cookie);
 141
 142        dbg_op_state();
 143 }
 144
 145 void ohci0_irq() {
 146         gecko_printf("ohci_irq\n");
 147         write32(OHCI0_HC_INT_STATUS, ~0);
 148 }
 149
 150