ohci.c

   1 /*
   2        mini - a Free Software replacement for the Nintendo/BroadOn IOS.
   3        ohci hardware support
   4
   5 Copyright (C) 2009     Bernhard Urban <lewurm@gmx.net>
   6 Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
   7
   8 # This code is licensed to you under the terms of the GNU GPL, version 2;
   9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
  10 */
  11
  12 #include "bootmii_ppc.h"
  13 #include "ohci.h"
  14 #include "irq.h"
  15
  16 #define gecko_printf printf
  17 #define set32(address, flags) write32(address, read32(address) | flags)
  18 #define dma_addr(address) virt_to_phys(address)
  19
  20
  21 static struct ohci_hcca hcca_oh0;
  22
  23 static void dbg_op_state() {
  24        switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
  25                case OHCI_USB_SUSPEND:
  26                        gecko_printf("ohci-- OHCI_USB_SUSPEND\n");
  27                        break;
  28                case OHCI_USB_RESET:
  29                        gecko_printf("ohci-- OHCI_USB_RESET\n");
  30                        break;
  31                case OHCI_USB_OPER:
  32                        gecko_printf("ohci-- OHCI_USB_OPER\n");
  33                        break;
  34                case OHCI_USB_RESUME:
  35                        gecko_printf("ohci-- OHCI_USB_RESUME\n");
  36                        break;
  37        }
  38 }
  39
  40 void ohci_init() {
  41        gecko_printf("ohci-- init\n");
  42        dbg_op_state();
  43        /*
  44        u32 i = 0;
  45        for(; i <= 0x200; i+=4) {
  46                gecko_printf("0x0d050000 + %X: %X\n", i, read32(0x0d050000+i));
  47                udelay(10000); //'cause usb gecko is lame
  48        }
  49        * see output in ohci.default
  50        */
  51
  52        /* enable interrupts of both usb host controllers */
  53        set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
  54
  55        /* reset HC */
  56        set32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
  57
  58        /* wait max. 30us */
  59        u32 ts = 30;
  60        while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
  61                if(--ts == 0) {
  62                        gecko_printf("ohci-- FAILED");
  63                        return;
  64                }
  65                udelay(1);
  66        }
  67
  68        /* disable interrupts; 2ms timelimit here!
  69           now we're in the SUSPEND state ... must go OPERATIONAL
  70           within 2msec else HC enters RESUME */
  71
  72
  73        //u32 cookie = irq_kill();
  74        u32 cookie;
  75        _CPU_ISR_Disable(cookie);
  76
  77
  78        /* Tell the controller where the control and bulk lists are
  79         * The lists are empty now. */
  80        write32(OHCI0_HC_CTRL_HEAD_ED, 0);
  81        write32(OHCI0_HC_BULK_HEAD_ED, 0);
  82
  83        /* set hcca adress */
  84        write32(OHCI0_HC_HCCA, dma_addr(&hcca_oh0));
  85
  86        /* set periodicstart */
  87 #define FIT (1<<31)
  88        u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
  89        u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
  90
  91        write32(OHCI0_HC_FM_INTERVAL, read32(OHCI0_HC_FM_INTERVAL) | (fit ^ FIT));
  92        write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
  93
  94        /* testing bla */
  95        if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
  96                gecko_printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
  97        }
  98
  99        /* start HC operations */
 100        set32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
 101
 102        /* wake on ConnectStatusChange, matching external hubs */
 103        set32(OHCI0_HC_RH_STATUS, RH_HS_DRWE);
 104
 105        /* Choose the interrupts we care about now, others later on demand */
 106        write32(OHCI0_HC_INT_STATUS, ~0);
 107        write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
 108
 109
 110        //irq_restore(cookie);
 111        _CPU_ISR_Restore(cookie);
 112
 113
 114        dbg_op_state();
 115
 116 }
 117