1 # crt0.s file for the GameCube V1.0 by Costis (costis@gbaemu.com)!
8 .irp i, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
12 lis 1,_stack_bot@h ; ori 1,1,_stack_bot@l
16 stw 1,0x34(2) # write sp
18 # ori 13,13,_SDA_BASE_@l # Set the Small Data (Read\Write) base register.
20 bl InitHardware # Initialize the GameCube Hardware (Floating Point Registers, Caches, etc.)
21 bl SystemInit # Initialize more cache aspects, clear a few SPR's, and disable interrupts.
25 ori 3, 3, __bss_start@l
33 bl main # Branch to the user code!
34 b . # If the main function returns, then just loop endlessly.
37 mflr 31 # Store the link register in r31
39 bl PSInit # Initialize Paired Singles
40 bl FPRInit # Initialize the FPR's
41 bl CacheInit # Initialize the system caches
43 mtlr 31 # Retreive the link register from r31
51 # Set the Instruction Cache invalidation bit in HID0
58 # Clear various Special Purpose Registers
73 # Enable the Floating Point Registers
78 # Clear all of the FPR's to 0
125 mfspr 3,1008 # (HID0)
126 rlwinm 0, 3, 0, 16, 16
127 cmplwi 0, 0x0000 # Check if the Instruction Cache has been enabled or not.
130 # If not, then enable it.
137 mfspr 3, 1008 # bl PPCMfhid0
138 rlwinm 0, 3, 0, 17, 17
139 cmplwi 0, 0x0000 # Check if the Data Cache has been enabled or not.
142 # If not, then enable it.
150 mfspr 3, 1017 # (L2CR)
151 clrrwi 0, 3, 31 # Clear all of the bits except 31
153 bne L2GISkip # Skip the L2 Global Cache Invalidation process if it has already been done befor.
155 # Store the current state of the MSR in r30
161 # Enable Instruction and Data Address Translation
168 # Disable the L2 Global Cache.
169 mfspr 3, 1017 # (L2CR
171 mtspr 1017, 3 # (L2CR)
174 # Invalidate the L2 Global Cache.
175 bl L2GlobalInvalidate
177 # Restore the previous state of the MSR from r30
181 # Enable the L2 Global Cache and disable the L2 Data Only bit and the L2 Global Invalidate Bit.
182 mfspr 3, 1017 # (L2CR)
184 rlwinm 3, 0, 0, 11, 9
185 mtspr 1017, 3 # (L2CR)
189 # Restore the non-volatile registers to their previous values and return.
204 # Disable the L2 Cache.
205 mfspr 3, 1017 # bl PPCMf1017
207 mtspr 1017, 3 # bl PPCMt1017
211 # Initiate the L2 Cache Global Invalidation process.
212 mfspr 3, 1017 # (L2CR)
214 mtspr 1017, 3 # (L2CR)
216 # Wait until the L2 Cache Global Invalidation has been completed.
218 mfspr 3, 1017 # (L2CR)
221 bne L2GICheckComplete
223 # Clear the L2 Data Only bit and the L2 Global Invalidate Bit.
224 mfspr 3, 1017 # (L2CR)
225 rlwinm 3, 3, 0, 11, 9
226 mtspr 1017, 3 # (L2CR)
228 # Wait until the L2 Cache Global Invalidation status bit signifies that it is ready.
230 mfspr 3, 1017 # (L2CR)
233 bne L2GDICheckComplete
235 # Restore the non-volatile registers to their previous values and return.
250 # Disable interrupts!
256 # Clear various SPR's
265 # Disable Speculative Bus Accesses to non-guarded space from both caches.
266 mfspr 3, 1008 # (HID0)
270 # Set the Non-IEEE mode in the FPSCR
277 # Restore the non-volatile registers to their previous values and return.