Merge pull request #4663 from xmcclure/bump-linker

Bump linker external to its master

diff --git a/external/corert b/external/corert
index 8dce492077a2cd43abff2e9d4e0c9e186f44af2e..f9066eefa76d961b11dfb89faa612762cc214ef4 160000 (submodule)
--- a/external/corert
+++ b/external/corert
@@ -1 +1 @@
-Subproject commit 8dce492077a2cd43abff2e9d4e0c9e186f44af2e
+Subproject commit f9066eefa76d961b11dfb89faa612762cc214ef4

diff --git a/mcs/build/gensources.sh b/mcs/build/gensources.sh
index 14a0a01db59d07b4503b9a5d1ae8882e25442524..a501a5b816c206e2fc3e271f8cf2c998d85d614e 100644 (file)
--- a/mcs/build/gensources.sh
+++ b/mcs/build/gensources.sh
@@ -29,6 +29,17 @@ process_includes() {
     rm -f $t
 }
 
+check_newline_eof() {
+       file=$1
+       if ! test -n "$file"; then return; fi
+       if ! test -z "$(tail -c 1 "$file")"; then echo "$file: missing newline at end of file."; exit 1; fi
+}
+
+check_newline_eof $incfile
+check_newline_eof $excfile
+check_newline_eof $extfile
+check_newline_eof $extexcfile
+
 rm -f $outfile.makefrag
 
 process_includes $incfile $outfile.inc

diff --git a/mcs/class/Facades/System.Security.Cryptography.Algorithms/System.Security.Cryptography.Algorithms.dll.sources b/mcs/class/Facades/System.Security.Cryptography.Algorithms/System.Security.Cryptography.Algorithms.dll.sources
index edeedfecef565692e59897f73e677baaaed68f21..bc50224ae2c5f03351bce7b833e573ee3c5537a2 100644 (file)
--- a/mcs/class/Facades/System.Security.Cryptography.Algorithms/System.Security.Cryptography.Algorithms.dll.sources
+++ b/mcs/class/Facades/System.Security.Cryptography.Algorithms/System.Security.Cryptography.Algorithms.dll.sources
@@ -1,4 +1,4 @@
 TypeForwarders.cs
 AssemblyInfo.cs
 SR.cs
-../../../../external/corefx/src/System.Security.Cryptography.Algorithms/src/System/Security/Cryptography/IncrementalHash.net46.cs
\ No newline at end of file
+../../../../external/corefx/src/System.Security.Cryptography.Algorithms/src/System/Security/Cryptography/IncrementalHash.net46.cs

diff --git a/mcs/class/System.Data/System.Data_test.dll.sources b/mcs/class/System.Data/System.Data_test.dll.sources
index d0cc818ecc9c01a7b7b974aaad8bd3db38fac771..aa503bf956e28fc2418880d7e3b6d081b5cc9a63 100644 (file)
--- a/mcs/class/System.Data/System.Data_test.dll.sources
+++ b/mcs/class/System.Data/System.Data_test.dll.sources
@@ -151,4 +151,4 @@ ProviderTests/System.Data.SqlClient/SqlTransactionTest.cs
 ProviderTests/System.Data.SqlClient/SqlConnectionStringBuilderTest.cs
 ProviderTests/System.Data.SqlClient/SqlConnectionTest.cs
 ProviderTests/System.Data.SqlClient/SqlParameterTest.cs
-ProviderTests/System.Data.SqlClient/SqlParameterCollectionTest.cs
\ No newline at end of file
+ProviderTests/System.Data.SqlClient/SqlParameterCollectionTest.cs

diff --git a/mcs/class/System.Data/Test/ProviderTests/System.Data.Connected.Tests.dll.sources b/mcs/class/System.Data/Test/ProviderTests/System.Data.Connected.Tests.dll.sources
index aae0e84b04933ca7e63d21d70049cbba2be6ae9b..839b12e7d79b82937294b5f1bb9d160494ed20fe 100644 (file)
--- a/mcs/class/System.Data/Test/ProviderTests/System.Data.Connected.Tests.dll.sources
+++ b/mcs/class/System.Data/Test/ProviderTests/System.Data.Connected.Tests.dll.sources
@@ -23,4 +23,4 @@ System.Data.SqlClient/SqlTransactionTest.cs
 System.Data.SqlClient/SqlConnectionStringBuilderTest.cs
 System.Data.SqlClient/SqlConnectionTest.cs
 System.Data.SqlClient/SqlParameterTest.cs
-System.Data.SqlClient/SqlParameterCollectionTest.cs
\ No newline at end of file
+System.Data.SqlClient/SqlParameterCollectionTest.cs

diff --git a/mcs/class/System.Data/corefx.common.sources b/mcs/class/System.Data/corefx.common.sources
index 24f91f3bef67b61465ba24629462d3c5ddb49ee7..a7673c77610aefa3f3527a156f9f13f4fd84a6c6 100644 (file)
--- a/mcs/class/System.Data/corefx.common.sources
+++ b/mcs/class/System.Data/corefx.common.sources
@@ -291,4 +291,4 @@
 ../referencesource/System.Data/System/Data/SqlClient/SqlConnectionStringBuilder.cs
 ../referencesource/System.Data/System/Data/SqlClient/SqlUtil.cs
 ../referencesource/System.Data/System/Data/SqlClient/TdsEnums.cs
-../referencesource/System.Data/System/Data/SqlClient/TdsParserStaticMethods.cs
\ No newline at end of file
+../referencesource/System.Data/System/Data/SqlClient/TdsParserStaticMethods.cs

diff --git a/mcs/class/System.Drawing/winaot_System.Drawing.dll.sources b/mcs/class/System.Drawing/winaot_System.Drawing.dll.sources
index c7c763e880b21990b8a5de9e072f13d1533097f4..0a0a514c1cc600bf827e3863369eed3535462c51 100644 (file)
--- a/mcs/class/System.Drawing/winaot_System.Drawing.dll.sources
+++ b/mcs/class/System.Drawing/winaot_System.Drawing.dll.sources
@@ -1,3 +1,3 @@
 Assembly/AssemblyInfo.cs
 ../../build/common/Consts.cs
-#include netstandard.sources
\ No newline at end of file
+#include netstandard.sources

diff --git a/mcs/class/System.IO.Compression.FileSystem/System.IO.Compression.FileSystem.dll.sources b/mcs/class/System.IO.Compression.FileSystem/System.IO.Compression.FileSystem.dll.sources
index e4bd34fd2d04b178a2636942cc975a63bda37bf1..30a80ab5f2fa067c12b8fc0c42a1140b78ebfa77 100644 (file)
--- a/mcs/class/System.IO.Compression.FileSystem/System.IO.Compression.FileSystem.dll.sources
+++ b/mcs/class/System.IO.Compression.FileSystem/System.IO.Compression.FileSystem.dll.sources
@@ -11,4 +11,4 @@ corefx/SR.cs
 ../../../external/corefx/src/System.Buffers/src/System/Buffers/ArrayPoolEventSource.cs
 ../../../external/corefx/src/System.Buffers/src/System/Buffers/DefaultArrayPool.cs
 ../../../external/corefx/src/System.Buffers/src/System/Buffers/DefaultArrayPoolBucket.cs
-../../../external/corefx/src/System.Buffers/src/System/Buffers/Utilities.cs
\ No newline at end of file
+../../../external/corefx/src/System.Buffers/src/System/Buffers/Utilities.cs

diff --git a/mcs/tools/installutil/installutil.exe.sources b/mcs/tools/installutil/installutil.exe.sources
index c245e0a25228c92c0551c9e5c5b74801c1bed8c9..10b03c22d4ca8a5be8226c4aed9de7050e64be70 100644 (file)
--- a/mcs/tools/installutil/installutil.exe.sources
+++ b/mcs/tools/installutil/installutil.exe.sources
@@ -1 +1 @@
-installutil.cs
\ No newline at end of file
+installutil.cs

diff --git a/mcs/tools/mdbrebase/mdbrebase.exe.sources b/mcs/tools/mdbrebase/mdbrebase.exe.sources
index 424003ed5ab73767d09ae15095633e3c77dddfb3..7d4f16b9d6f1cdb304953d5190098d8cc67fc1e1 100644 (file)
--- a/mcs/tools/mdbrebase/mdbrebase.exe.sources
+++ b/mcs/tools/mdbrebase/mdbrebase.exe.sources
@@ -1,2 +1,2 @@
 ../../class/Mono.Options/Mono.Options/Options.cs
-./mdbrebase.cs
\ No newline at end of file
+./mdbrebase.cs

diff --git a/mono/arch/arm/.gitignore b/mono/arch/arm/.gitignore
index 978145d1b6e8a3a9ccfa8da6f6d127790bc6cbfe..7040246bec9fcd42f7a87152afe122130af8135b 100644 (file)
--- a/mono/arch/arm/.gitignore
+++ b/mono/arch/arm/.gitignore
@@ -9,7 +9,4 @@
 /*.obj
 /*.exe
 /*.dll
-/arm_dpimacros.h
-/arm_fpamacros.h
-/arm_vfpmacros.h
 /fixeol.sh

diff --git a/mono/arch/arm/Makefile.am b/mono/arch/arm/Makefile.am
index 8d2f52782003ea31467289c88cec4ca111c2f4aa..6c13092a2f981a73ba66256b7fe8fe1b2d16b4cf 100644 (file)
--- a/mono/arch/arm/Makefile.am
+++ b/mono/arch/arm/Makefile.am
@@ -1,8 +1,6 @@
 
 AM_CPPFLAGS = $(GLIB_CFLAGS) -I$(top_srcdir)
 
-BUILT_SOURCES = arm_dpimacros.h arm_vfpmacros.h
-
 arm_dpimacros.h: dpiops.sh mov_macros.th dpi_macros.th cmp_macros.th
        (cd $(srcdir); bash ./dpiops.sh) > $@t
        mv $@t $@
@@ -11,8 +9,10 @@ arm_vfpmacros.h: vfpops.sh vfpm_macros.th vfp_macros.th
        (cd $(srcdir); bash ./vfpops.sh) > $@t
        mv $@t $@
 
-CLEANFILES = $(BUILT_SOURCES)
+gen: arm_dpimacros.h arm_vfpmacros.h
 
 EXTRA_DIST = arm-codegen.h dpiops.sh mov_macros.th dpi_macros.th cmp_macros.th \
-       vfpm_macros.th vfp_macros.th arm-vfp-codegen.h vfpops.sh
+       vfpm_macros.th vfp_macros.th arm-vfp-codegen.h vfpops.sh \
+       arm_dpimacros.h arm_vfpmacros.h
+
 

diff --git a/mono/arch/arm/arm_dpimacros.h b/mono/arch/arm/arm_dpimacros.h
new file mode 100644 (file)
index 0000000..d8ff666
--- /dev/null
+++ b/mono/arch/arm/arm_dpimacros.h
@@ -0,0 +1,1603 @@
+/* Macros for DPI ops, auto-generated from template */
+
+
+/* mov/mvn */
+
+/* Rd := imm8 ROR rot */
+#define ARM_MOV_REG_IMM_COND(p, reg, imm8, rot, cond) \
+       ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_MOV, reg, 0, imm8, rot, cond)
+#define ARM_MOV_REG_IMM(p, reg, imm8, rot) \
+       ARM_MOV_REG_IMM_COND(p, reg, imm8, rot, ARMCOND_AL)
+/* S */
+#define ARM_MOVS_REG_IMM_COND(p, reg, imm8, rot, cond) \
+       ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_MOV, reg, 0, imm8, rot, cond)
+#define ARM_MOVS_REG_IMM(p, reg, imm8, rot) \
+       ARM_MOVS_REG_IMM_COND(p, reg, imm8, rot, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _MOV_REG_IMM_COND(reg, imm8, rot, cond) \
+       ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_MOV, reg, 0, imm8, rot, cond)
+#define _MOV_REG_IMM(reg, imm8, rot) \
+       _MOV_REG_IMM_COND(reg, imm8, rot, ARMCOND_AL)
+/* S */
+#define _MOVS_REG_IMM_COND(reg, imm8, rot, cond) \
+       ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_MOV, reg, 0, imm8, rot, cond)
+#define _MOVS_REG_IMM(reg, imm8, rot) \
+       _MOVS_REG_IMM_COND(reg, imm8, rot, ARMCOND_AL)
+#endif
+
+
+/* Rd := imm8 */
+#define ARM_MOV_REG_IMM8_COND(p, reg, imm8, cond) \
+       ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_MOV, reg, 0, imm8, 0, cond)
+#define ARM_MOV_REG_IMM8(p, reg, imm8) \
+       ARM_MOV_REG_IMM8_COND(p, reg, imm8, ARMCOND_AL)
+/* S */
+#define ARM_MOVS_REG_IMM8_COND(p, reg, imm8, cond) \
+       ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_MOV, reg, 0, imm8, 0, cond)
+#define ARM_MOVS_REG_IMM8(p, reg, imm8) \
+       ARM_MOVS_REG_IMM8_COND(p, reg, imm8, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _MOV_REG_IMM8_COND(reg, imm8, cond) \
+       ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_MOV, reg, 0, imm8, 0, cond)
+#define _MOV_REG_IMM8(reg, imm8) \
+       _MOV_REG_IMM8_COND(reg, imm8, ARMCOND_AL)
+/* S */
+#define _MOVS_REG_IMM8_COND(reg, imm8, cond) \
+       ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_MOV, reg, 0, imm8, 0, cond)
+#define _MOVS_REG_IMM8(reg, imm8) \
+       _MOVS_REG_IMM8_COND(reg, imm8, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rm */
+#define ARM_MOV_REG_REG_COND(p, rd, rm, cond) \
+       ARM_DPIOP_REG_REG_COND(p, ARMOP_MOV, rd, 0, rm, cond)
+#define ARM_MOV_REG_REG(p, rd, rm) \
+       ARM_MOV_REG_REG_COND(p, rd, rm, ARMCOND_AL)
+/* S */
+#define ARM_MOVS_REG_REG_COND(p, rd, rm, cond) \
+       ARM_DPIOP_S_REG_REG_COND(p, ARMOP_MOV, rd, 0, rm, cond)
+#define ARM_MOVS_REG_REG(p, rd, rm) \
+       ARM_MOVS_REG_REG_COND(p, rd, rm, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _MOV_REG_REG_COND(rd, rm, cond) \
+       ARM_IASM_DPIOP_REG_REG_COND(ARMOP_MOV, rd, 0, rm, cond)
+#define _MOV_REG_REG(rd, rm) \
+       _MOV_REG_REG_COND(rd, rm, ARMCOND_AL)
+/* S */
+#define _MOVS_REG_REG_COND(rd, rm, cond) \
+       ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_MOV, rd, 0, rm, cond)
+#define _MOVS_REG_REG(rd, rm) \
+       _MOVS_REG_REG_COND(rd, rm, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rm <shift_type> imm_shift */
+#define ARM_MOV_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_MOV, rd, 0, rm, shift_type, imm_shift, cond)
+#define ARM_MOV_REG_IMMSHIFT(p, rd, rm, shift_type, imm_shift) \
+       ARM_MOV_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, ARMCOND_AL)
+/* S */
+#define ARM_MOVS_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_MOV, rd, 0, rm, shift_type, imm_shift, cond)
+#define ARM_MOVS_REG_IMMSHIFT(p, rd, rm, shift_type, imm_shift) \
+       ARM_MOVS_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _MOV_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_MOV, rd, 0, rm, shift_type, imm_shift, cond)
+#define _MOV_REG_IMMSHIFT(rd, rm, shift_type, imm_shift) \
+       _MOV_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, ARMCOND_AL)
+/* S */
+#define _MOVS_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_MOV, rd, 0, rm, shift_type, imm_shift, cond)
+#define _MOVS_REG_IMMSHIFT(rd, rm, shift_type, imm_shift) \
+       _MOVS_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, ARMCOND_AL)
+#endif
+
+
+
+/* Rd := (Rm <shift_type> Rs) */
+#define ARM_MOV_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, cond) \
+       ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_MOV, rd, 0, rm, shift_type, rs, cond)
+#define ARM_MOV_REG_REGSHIFT(p, rd, rm, shift_type, rs) \
+       ARM_MOV_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, ARMCOND_AL)
+/* S */
+#define ARM_MOVS_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, cond) \
+       ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_MOV, rd, 0, rm, shift_type, rs, cond)
+#define ARM_MOVS_REG_REGSHIFT(p, rd, rm, shift_type, rs) \
+       ARM_MOVS_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _MOV_REG_REGSHIFT_COND(rd, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_MOV, rd, 0, rm, shift_type, rs, cond)
+#define _MOV_REG_REGSHIFT(rd, rm, shift_type, rs) \
+       _MOV_REG_REGSHIFT_COND(rd, rm, shift_type, rs, ARMCOND_AL)
+/* S */
+#define _MOVS_REG_REGSHIFT_COND(rd, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_MOV, rd, 0, rm, shift_type, rs, cond)
+#define _MOVS_REG_REGSHIFT(rd, rm, shift_type, rs) \
+       _MOVS_REG_REGSHIFT_COND(rd, rm, shift_type, rs, ARMCOND_AL)
+#endif
+
+
+/* Rd := imm8 ROR rot */
+#define ARM_MVN_REG_IMM_COND(p, reg, imm8, rot, cond) \
+       ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_MVN, reg, 0, imm8, rot, cond)
+#define ARM_MVN_REG_IMM(p, reg, imm8, rot) \
+       ARM_MVN_REG_IMM_COND(p, reg, imm8, rot, ARMCOND_AL)
+/* S */
+#define ARM_MVNS_REG_IMM_COND(p, reg, imm8, rot, cond) \
+       ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_MVN, reg, 0, imm8, rot, cond)
+#define ARM_MVNS_REG_IMM(p, reg, imm8, rot) \
+       ARM_MVNS_REG_IMM_COND(p, reg, imm8, rot, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _MVN_REG_IMM_COND(reg, imm8, rot, cond) \
+       ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_MVN, reg, 0, imm8, rot, cond)
+#define _MVN_REG_IMM(reg, imm8, rot) \
+       _MVN_REG_IMM_COND(reg, imm8, rot, ARMCOND_AL)
+/* S */
+#define _MVNS_REG_IMM_COND(reg, imm8, rot, cond) \
+       ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_MVN, reg, 0, imm8, rot, cond)
+#define _MVNS_REG_IMM(reg, imm8, rot) \
+       _MVNS_REG_IMM_COND(reg, imm8, rot, ARMCOND_AL)
+#endif
+
+
+/* Rd := imm8 */
+#define ARM_MVN_REG_IMM8_COND(p, reg, imm8, cond) \
+       ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_MVN, reg, 0, imm8, 0, cond)
+#define ARM_MVN_REG_IMM8(p, reg, imm8) \
+       ARM_MVN_REG_IMM8_COND(p, reg, imm8, ARMCOND_AL)
+/* S */
+#define ARM_MVNS_REG_IMM8_COND(p, reg, imm8, cond) \
+       ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_MVN, reg, 0, imm8, 0, cond)
+#define ARM_MVNS_REG_IMM8(p, reg, imm8) \
+       ARM_MVNS_REG_IMM8_COND(p, reg, imm8, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _MVN_REG_IMM8_COND(reg, imm8, cond) \
+       ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_MVN, reg, 0, imm8, 0, cond)
+#define _MVN_REG_IMM8(reg, imm8) \
+       _MVN_REG_IMM8_COND(reg, imm8, ARMCOND_AL)
+/* S */
+#define _MVNS_REG_IMM8_COND(reg, imm8, cond) \
+       ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_MVN, reg, 0, imm8, 0, cond)
+#define _MVNS_REG_IMM8(reg, imm8) \
+       _MVNS_REG_IMM8_COND(reg, imm8, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rm */
+#define ARM_MVN_REG_REG_COND(p, rd, rm, cond) \
+       ARM_DPIOP_REG_REG_COND(p, ARMOP_MVN, rd, 0, rm, cond)
+#define ARM_MVN_REG_REG(p, rd, rm) \
+       ARM_MVN_REG_REG_COND(p, rd, rm, ARMCOND_AL)
+/* S */
+#define ARM_MVNS_REG_REG_COND(p, rd, rm, cond) \
+       ARM_DPIOP_S_REG_REG_COND(p, ARMOP_MVN, rd, 0, rm, cond)
+#define ARM_MVNS_REG_REG(p, rd, rm) \
+       ARM_MVNS_REG_REG_COND(p, rd, rm, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _MVN_REG_REG_COND(rd, rm, cond) \
+       ARM_IASM_DPIOP_REG_REG_COND(ARMOP_MVN, rd, 0, rm, cond)
+#define _MVN_REG_REG(rd, rm) \
+       _MVN_REG_REG_COND(rd, rm, ARMCOND_AL)
+/* S */
+#define _MVNS_REG_REG_COND(rd, rm, cond) \
+       ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_MVN, rd, 0, rm, cond)
+#define _MVNS_REG_REG(rd, rm) \
+       _MVNS_REG_REG_COND(rd, rm, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rm <shift_type> imm_shift */
+#define ARM_MVN_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_MVN, rd, 0, rm, shift_type, imm_shift, cond)
+#define ARM_MVN_REG_IMMSHIFT(p, rd, rm, shift_type, imm_shift) \
+       ARM_MVN_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, ARMCOND_AL)
+/* S */
+#define ARM_MVNS_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_MVN, rd, 0, rm, shift_type, imm_shift, cond)
+#define ARM_MVNS_REG_IMMSHIFT(p, rd, rm, shift_type, imm_shift) \
+       ARM_MVNS_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _MVN_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_MVN, rd, 0, rm, shift_type, imm_shift, cond)
+#define _MVN_REG_IMMSHIFT(rd, rm, shift_type, imm_shift) \
+       _MVN_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, ARMCOND_AL)
+/* S */
+#define _MVNS_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_MVN, rd, 0, rm, shift_type, imm_shift, cond)
+#define _MVNS_REG_IMMSHIFT(rd, rm, shift_type, imm_shift) \
+       _MVNS_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, ARMCOND_AL)
+#endif
+
+
+
+/* Rd := (Rm <shift_type> Rs) */
+#define ARM_MVN_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, cond) \
+       ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_MVN, rd, 0, rm, shift_type, rs, cond)
+#define ARM_MVN_REG_REGSHIFT(p, rd, rm, shift_type, rs) \
+       ARM_MVN_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, ARMCOND_AL)
+/* S */
+#define ARM_MVNS_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, cond) \
+       ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_MVN, rd, 0, rm, shift_type, rs, cond)
+#define ARM_MVNS_REG_REGSHIFT(p, rd, rm, shift_type, rs) \
+       ARM_MVNS_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _MVN_REG_REGSHIFT_COND(rd, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_MVN, rd, 0, rm, shift_type, rs, cond)
+#define _MVN_REG_REGSHIFT(rd, rm, shift_type, rs) \
+       _MVN_REG_REGSHIFT_COND(rd, rm, shift_type, rs, ARMCOND_AL)
+/* S */
+#define _MVNS_REG_REGSHIFT_COND(rd, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_MVN, rd, 0, rm, shift_type, rs, cond)
+#define _MVNS_REG_REGSHIFT(rd, rm, shift_type, rs) \
+       _MVNS_REG_REGSHIFT_COND(rd, rm, shift_type, rs, ARMCOND_AL)
+#endif
+
+
+
+/* DPIs, arithmetic and logical */
+
+/* -- AND -- */
+
+/* Rd := Rn AND (imm8 ROR rot) ; rot is power of 2 */
+#define ARM_AND_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
+       ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_AND, rd, rn, imm8, rot, cond)
+#define ARM_AND_REG_IMM(p, rd, rn, imm8, rot) \
+       ARM_AND_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)
+#define ARM_ANDS_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
+       ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_AND, rd, rn, imm8, rot, cond)
+#define ARM_ANDS_REG_IMM(p, rd, rn, imm8, rot) \
+       ARM_ANDS_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _AND_REG_IMM_COND(rd, rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_AND, rd, rn, imm8, rot, cond)
+#define _AND_REG_IMM(rd, rn, imm8, rot) \
+       _AND_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
+#define _ANDS_REG_IMM_COND(rd, rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_AND, rd, rn, imm8, rot, cond)
+#define _ANDS_REG_IMM(rd, rn, imm8, rot) \
+       _ANDS_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn AND imm8 */
+#define ARM_AND_REG_IMM8_COND(p, rd, rn, imm8, cond) \
+       ARM_AND_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
+#define ARM_AND_REG_IMM8(p, rd, rn, imm8) \
+       ARM_AND_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)
+#define ARM_ANDS_REG_IMM8_COND(p, rd, rn, imm8, cond) \
+       ARM_ANDS_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
+#define ARM_ANDS_REG_IMM8(p, rd, rn, imm8) \
+       ARM_ANDS_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _AND_REG_IMM8_COND(rd, rn, imm8, cond) \
+       _AND_REG_IMM_COND(rd, rn, imm8, 0, cond)
+#define _AND_REG_IMM8(rd, rn, imm8) \
+       _AND_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
+#define _ANDS_REG_IMM8_COND(rd, rn, imm8, cond) \
+       _ANDS_REG_IMM_COND(rd, rn, imm8, 0, cond)
+#define _ANDS_REG_IMM8(rd, rn, imm8) \
+       _ANDS_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn AND Rm */
+#define ARM_AND_REG_REG_COND(p, rd, rn, rm, cond) \
+       ARM_DPIOP_REG_REG_COND(p, ARMOP_AND, rd, rn, rm, cond)
+#define ARM_AND_REG_REG(p, rd, rn, rm) \
+       ARM_AND_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL)
+#define ARM_ANDS_REG_REG_COND(p, rd, rn, rm, cond) \
+       ARM_DPIOP_S_REG_REG_COND(p, ARMOP_AND, rd, rn, rm, cond)
+#define ARM_ANDS_REG_REG(p, rd, rn, rm) \
+       ARM_ANDS_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _AND_REG_REG_COND(rd, rn, rm, cond) \
+       ARM_IASM_DPIOP_REG_REG_COND(ARMOP_AND, rd, rn, rm, cond)
+#define _AND_REG_REG(rd, rn, rm) \
+       _AND_REG_REG_COND(rd, rn, rm, ARMCOND_AL)
+#define _ANDS_REG_REG_COND(rd, rn, rm, cond) \
+       ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_AND, rd, rn, rm, cond)
+#define _ANDS_REG_REG(rd, rn, rm) \
+       _ANDS_REG_REG_COND(rd, rn, rm, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn AND (Rm <shift_type> imm_shift) */
+#define ARM_AND_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_AND, rd, rn, rm, shift_type, imm_shift, cond)
+#define ARM_AND_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \
+       ARM_AND_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#define ARM_ANDS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_AND, rd, rn, rm, shift_type, imm_shift, cond)
+#define ARM_ANDS_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \
+       ARM_ANDS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _AND_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_AND, rd, rn, rm, shift_type, imm_shift, cond)
+#define _AND_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \
+       _AND_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#define _ANDS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_AND, rd, rn, rm, shift_type, imm_shift, cond)
+#define _ANDS_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \
+       _ANDS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn AND (Rm <shift_type> Rs) */
+#define ARM_AND_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \
+       ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_AND, rd, rn, rm, shift_t, rs, cond)
+#define ARM_AND_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \
+       ARM_AND_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#define ARM_ANDS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \
+       ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_AND, rd, rn, rm, shift_t, rs, cond)
+#define ARM_ANDS_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \
+       ARM_ANDS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _AND_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_AND, rd, rn, rm, shift_t, rs, cond)
+#define _AND_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \
+       _AND_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#define _ANDS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_AND, rd, rn, rm, shift_t, rs, cond)
+#define _ANDS_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \
+       _ANDS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#endif
+
+
+/* -- EOR -- */
+
+/* Rd := Rn EOR (imm8 ROR rot) ; rot is power of 2 */
+#define ARM_EOR_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
+       ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_EOR, rd, rn, imm8, rot, cond)
+#define ARM_EOR_REG_IMM(p, rd, rn, imm8, rot) \
+       ARM_EOR_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)
+#define ARM_EORS_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
+       ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_EOR, rd, rn, imm8, rot, cond)
+#define ARM_EORS_REG_IMM(p, rd, rn, imm8, rot) \
+       ARM_EORS_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _EOR_REG_IMM_COND(rd, rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_EOR, rd, rn, imm8, rot, cond)
+#define _EOR_REG_IMM(rd, rn, imm8, rot) \
+       _EOR_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
+#define _EORS_REG_IMM_COND(rd, rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_EOR, rd, rn, imm8, rot, cond)
+#define _EORS_REG_IMM(rd, rn, imm8, rot) \
+       _EORS_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn EOR imm8 */
+#define ARM_EOR_REG_IMM8_COND(p, rd, rn, imm8, cond) \
+       ARM_EOR_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
+#define ARM_EOR_REG_IMM8(p, rd, rn, imm8) \
+       ARM_EOR_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)
+#define ARM_EORS_REG_IMM8_COND(p, rd, rn, imm8, cond) \
+       ARM_EORS_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
+#define ARM_EORS_REG_IMM8(p, rd, rn, imm8) \
+       ARM_EORS_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _EOR_REG_IMM8_COND(rd, rn, imm8, cond) \
+       _EOR_REG_IMM_COND(rd, rn, imm8, 0, cond)
+#define _EOR_REG_IMM8(rd, rn, imm8) \
+       _EOR_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
+#define _EORS_REG_IMM8_COND(rd, rn, imm8, cond) \
+       _EORS_REG_IMM_COND(rd, rn, imm8, 0, cond)
+#define _EORS_REG_IMM8(rd, rn, imm8) \
+       _EORS_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn EOR Rm */
+#define ARM_EOR_REG_REG_COND(p, rd, rn, rm, cond) \
+       ARM_DPIOP_REG_REG_COND(p, ARMOP_EOR, rd, rn, rm, cond)
+#define ARM_EOR_REG_REG(p, rd, rn, rm) \
+       ARM_EOR_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL)
+#define ARM_EORS_REG_REG_COND(p, rd, rn, rm, cond) \
+       ARM_DPIOP_S_REG_REG_COND(p, ARMOP_EOR, rd, rn, rm, cond)
+#define ARM_EORS_REG_REG(p, rd, rn, rm) \
+       ARM_EORS_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _EOR_REG_REG_COND(rd, rn, rm, cond) \
+       ARM_IASM_DPIOP_REG_REG_COND(ARMOP_EOR, rd, rn, rm, cond)
+#define _EOR_REG_REG(rd, rn, rm) \
+       _EOR_REG_REG_COND(rd, rn, rm, ARMCOND_AL)
+#define _EORS_REG_REG_COND(rd, rn, rm, cond) \
+       ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_EOR, rd, rn, rm, cond)
+#define _EORS_REG_REG(rd, rn, rm) \
+       _EORS_REG_REG_COND(rd, rn, rm, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn EOR (Rm <shift_type> imm_shift) */
+#define ARM_EOR_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_EOR, rd, rn, rm, shift_type, imm_shift, cond)
+#define ARM_EOR_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \
+       ARM_EOR_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#define ARM_EORS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_EOR, rd, rn, rm, shift_type, imm_shift, cond)
+#define ARM_EORS_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \
+       ARM_EORS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _EOR_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_EOR, rd, rn, rm, shift_type, imm_shift, cond)
+#define _EOR_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \
+       _EOR_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#define _EORS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_EOR, rd, rn, rm, shift_type, imm_shift, cond)
+#define _EORS_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \
+       _EORS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn EOR (Rm <shift_type> Rs) */
+#define ARM_EOR_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \
+       ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_EOR, rd, rn, rm, shift_t, rs, cond)
+#define ARM_EOR_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \
+       ARM_EOR_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#define ARM_EORS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \
+       ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_EOR, rd, rn, rm, shift_t, rs, cond)
+#define ARM_EORS_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \
+       ARM_EORS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _EOR_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_EOR, rd, rn, rm, shift_t, rs, cond)
+#define _EOR_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \
+       _EOR_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#define _EORS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_EOR, rd, rn, rm, shift_t, rs, cond)
+#define _EORS_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \
+       _EORS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#endif
+
+
+/* -- SUB -- */
+
+/* Rd := Rn SUB (imm8 ROR rot) ; rot is power of 2 */
+#define ARM_SUB_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
+       ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_SUB, rd, rn, imm8, rot, cond)
+#define ARM_SUB_REG_IMM(p, rd, rn, imm8, rot) \
+       ARM_SUB_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)
+#define ARM_SUBS_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
+       ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_SUB, rd, rn, imm8, rot, cond)
+#define ARM_SUBS_REG_IMM(p, rd, rn, imm8, rot) \
+       ARM_SUBS_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _SUB_REG_IMM_COND(rd, rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_SUB, rd, rn, imm8, rot, cond)
+#define _SUB_REG_IMM(rd, rn, imm8, rot) \
+       _SUB_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
+#define _SUBS_REG_IMM_COND(rd, rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_SUB, rd, rn, imm8, rot, cond)
+#define _SUBS_REG_IMM(rd, rn, imm8, rot) \
+       _SUBS_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn SUB imm8 */
+#define ARM_SUB_REG_IMM8_COND(p, rd, rn, imm8, cond) \
+       ARM_SUB_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
+#define ARM_SUB_REG_IMM8(p, rd, rn, imm8) \
+       ARM_SUB_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)
+#define ARM_SUBS_REG_IMM8_COND(p, rd, rn, imm8, cond) \
+       ARM_SUBS_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
+#define ARM_SUBS_REG_IMM8(p, rd, rn, imm8) \
+       ARM_SUBS_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _SUB_REG_IMM8_COND(rd, rn, imm8, cond) \
+       _SUB_REG_IMM_COND(rd, rn, imm8, 0, cond)
+#define _SUB_REG_IMM8(rd, rn, imm8) \
+       _SUB_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
+#define _SUBS_REG_IMM8_COND(rd, rn, imm8, cond) \
+       _SUBS_REG_IMM_COND(rd, rn, imm8, 0, cond)
+#define _SUBS_REG_IMM8(rd, rn, imm8) \
+       _SUBS_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn SUB Rm */
+#define ARM_SUB_REG_REG_COND(p, rd, rn, rm, cond) \
+       ARM_DPIOP_REG_REG_COND(p, ARMOP_SUB, rd, rn, rm, cond)
+#define ARM_SUB_REG_REG(p, rd, rn, rm) \
+       ARM_SUB_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL)
+#define ARM_SUBS_REG_REG_COND(p, rd, rn, rm, cond) \
+       ARM_DPIOP_S_REG_REG_COND(p, ARMOP_SUB, rd, rn, rm, cond)
+#define ARM_SUBS_REG_REG(p, rd, rn, rm) \
+       ARM_SUBS_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _SUB_REG_REG_COND(rd, rn, rm, cond) \
+       ARM_IASM_DPIOP_REG_REG_COND(ARMOP_SUB, rd, rn, rm, cond)
+#define _SUB_REG_REG(rd, rn, rm) \
+       _SUB_REG_REG_COND(rd, rn, rm, ARMCOND_AL)
+#define _SUBS_REG_REG_COND(rd, rn, rm, cond) \
+       ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_SUB, rd, rn, rm, cond)
+#define _SUBS_REG_REG(rd, rn, rm) \
+       _SUBS_REG_REG_COND(rd, rn, rm, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn SUB (Rm <shift_type> imm_shift) */
+#define ARM_SUB_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_SUB, rd, rn, rm, shift_type, imm_shift, cond)
+#define ARM_SUB_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \
+       ARM_SUB_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#define ARM_SUBS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_SUB, rd, rn, rm, shift_type, imm_shift, cond)
+#define ARM_SUBS_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \
+       ARM_SUBS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _SUB_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_SUB, rd, rn, rm, shift_type, imm_shift, cond)
+#define _SUB_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \
+       _SUB_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#define _SUBS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_SUB, rd, rn, rm, shift_type, imm_shift, cond)
+#define _SUBS_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \
+       _SUBS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn SUB (Rm <shift_type> Rs) */
+#define ARM_SUB_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \
+       ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_SUB, rd, rn, rm, shift_t, rs, cond)
+#define ARM_SUB_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \
+       ARM_SUB_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#define ARM_SUBS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \
+       ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_SUB, rd, rn, rm, shift_t, rs, cond)
+#define ARM_SUBS_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \
+       ARM_SUBS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _SUB_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_SUB, rd, rn, rm, shift_t, rs, cond)
+#define _SUB_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \
+       _SUB_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#define _SUBS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_SUB, rd, rn, rm, shift_t, rs, cond)
+#define _SUBS_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \
+       _SUBS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#endif
+
+
+/* -- RSB -- */
+
+/* Rd := Rn RSB (imm8 ROR rot) ; rot is power of 2 */
+#define ARM_RSB_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
+       ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_RSB, rd, rn, imm8, rot, cond)
+#define ARM_RSB_REG_IMM(p, rd, rn, imm8, rot) \
+       ARM_RSB_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)
+#define ARM_RSBS_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
+       ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_RSB, rd, rn, imm8, rot, cond)
+#define ARM_RSBS_REG_IMM(p, rd, rn, imm8, rot) \
+       ARM_RSBS_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _RSB_REG_IMM_COND(rd, rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_RSB, rd, rn, imm8, rot, cond)
+#define _RSB_REG_IMM(rd, rn, imm8, rot) \
+       _RSB_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
+#define _RSBS_REG_IMM_COND(rd, rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_RSB, rd, rn, imm8, rot, cond)
+#define _RSBS_REG_IMM(rd, rn, imm8, rot) \
+       _RSBS_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn RSB imm8 */
+#define ARM_RSB_REG_IMM8_COND(p, rd, rn, imm8, cond) \
+       ARM_RSB_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
+#define ARM_RSB_REG_IMM8(p, rd, rn, imm8) \
+       ARM_RSB_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)
+#define ARM_RSBS_REG_IMM8_COND(p, rd, rn, imm8, cond) \
+       ARM_RSBS_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
+#define ARM_RSBS_REG_IMM8(p, rd, rn, imm8) \
+       ARM_RSBS_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _RSB_REG_IMM8_COND(rd, rn, imm8, cond) \
+       _RSB_REG_IMM_COND(rd, rn, imm8, 0, cond)
+#define _RSB_REG_IMM8(rd, rn, imm8) \
+       _RSB_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
+#define _RSBS_REG_IMM8_COND(rd, rn, imm8, cond) \
+       _RSBS_REG_IMM_COND(rd, rn, imm8, 0, cond)
+#define _RSBS_REG_IMM8(rd, rn, imm8) \
+       _RSBS_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn RSB Rm */
+#define ARM_RSB_REG_REG_COND(p, rd, rn, rm, cond) \
+       ARM_DPIOP_REG_REG_COND(p, ARMOP_RSB, rd, rn, rm, cond)
+#define ARM_RSB_REG_REG(p, rd, rn, rm) \
+       ARM_RSB_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL)
+#define ARM_RSBS_REG_REG_COND(p, rd, rn, rm, cond) \
+       ARM_DPIOP_S_REG_REG_COND(p, ARMOP_RSB, rd, rn, rm, cond)
+#define ARM_RSBS_REG_REG(p, rd, rn, rm) \
+       ARM_RSBS_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _RSB_REG_REG_COND(rd, rn, rm, cond) \
+       ARM_IASM_DPIOP_REG_REG_COND(ARMOP_RSB, rd, rn, rm, cond)
+#define _RSB_REG_REG(rd, rn, rm) \
+       _RSB_REG_REG_COND(rd, rn, rm, ARMCOND_AL)
+#define _RSBS_REG_REG_COND(rd, rn, rm, cond) \
+       ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_RSB, rd, rn, rm, cond)
+#define _RSBS_REG_REG(rd, rn, rm) \
+       _RSBS_REG_REG_COND(rd, rn, rm, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn RSB (Rm <shift_type> imm_shift) */
+#define ARM_RSB_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_RSB, rd, rn, rm, shift_type, imm_shift, cond)
+#define ARM_RSB_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \
+       ARM_RSB_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#define ARM_RSBS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_RSB, rd, rn, rm, shift_type, imm_shift, cond)
+#define ARM_RSBS_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \
+       ARM_RSBS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _RSB_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_RSB, rd, rn, rm, shift_type, imm_shift, cond)
+#define _RSB_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \
+       _RSB_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#define _RSBS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_RSB, rd, rn, rm, shift_type, imm_shift, cond)
+#define _RSBS_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \
+       _RSBS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn RSB (Rm <shift_type> Rs) */
+#define ARM_RSB_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \
+       ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_RSB, rd, rn, rm, shift_t, rs, cond)
+#define ARM_RSB_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \
+       ARM_RSB_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#define ARM_RSBS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \
+       ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_RSB, rd, rn, rm, shift_t, rs, cond)
+#define ARM_RSBS_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \
+       ARM_RSBS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _RSB_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_RSB, rd, rn, rm, shift_t, rs, cond)
+#define _RSB_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \
+       _RSB_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#define _RSBS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_RSB, rd, rn, rm, shift_t, rs, cond)
+#define _RSBS_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \
+       _RSBS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#endif
+
+
+/* -- ADD -- */
+
+/* Rd := Rn ADD (imm8 ROR rot) ; rot is power of 2 */
+#define ARM_ADD_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
+       ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_ADD, rd, rn, imm8, rot, cond)
+#define ARM_ADD_REG_IMM(p, rd, rn, imm8, rot) \
+       ARM_ADD_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)
+#define ARM_ADDS_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
+       ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_ADD, rd, rn, imm8, rot, cond)
+#define ARM_ADDS_REG_IMM(p, rd, rn, imm8, rot) \
+       ARM_ADDS_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _ADD_REG_IMM_COND(rd, rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_ADD, rd, rn, imm8, rot, cond)
+#define _ADD_REG_IMM(rd, rn, imm8, rot) \
+       _ADD_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
+#define _ADDS_REG_IMM_COND(rd, rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_ADD, rd, rn, imm8, rot, cond)
+#define _ADDS_REG_IMM(rd, rn, imm8, rot) \
+       _ADDS_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn ADD imm8 */
+#define ARM_ADD_REG_IMM8_COND(p, rd, rn, imm8, cond) \
+       ARM_ADD_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
+#define ARM_ADD_REG_IMM8(p, rd, rn, imm8) \
+       ARM_ADD_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)
+#define ARM_ADDS_REG_IMM8_COND(p, rd, rn, imm8, cond) \
+       ARM_ADDS_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
+#define ARM_ADDS_REG_IMM8(p, rd, rn, imm8) \
+       ARM_ADDS_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _ADD_REG_IMM8_COND(rd, rn, imm8, cond) \
+       _ADD_REG_IMM_COND(rd, rn, imm8, 0, cond)
+#define _ADD_REG_IMM8(rd, rn, imm8) \
+       _ADD_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
+#define _ADDS_REG_IMM8_COND(rd, rn, imm8, cond) \
+       _ADDS_REG_IMM_COND(rd, rn, imm8, 0, cond)
+#define _ADDS_REG_IMM8(rd, rn, imm8) \
+       _ADDS_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn ADD Rm */
+#define ARM_ADD_REG_REG_COND(p, rd, rn, rm, cond) \
+       ARM_DPIOP_REG_REG_COND(p, ARMOP_ADD, rd, rn, rm, cond)
+#define ARM_ADD_REG_REG(p, rd, rn, rm) \
+       ARM_ADD_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL)
+#define ARM_ADDS_REG_REG_COND(p, rd, rn, rm, cond) \
+       ARM_DPIOP_S_REG_REG_COND(p, ARMOP_ADD, rd, rn, rm, cond)
+#define ARM_ADDS_REG_REG(p, rd, rn, rm) \
+       ARM_ADDS_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _ADD_REG_REG_COND(rd, rn, rm, cond) \
+       ARM_IASM_DPIOP_REG_REG_COND(ARMOP_ADD, rd, rn, rm, cond)
+#define _ADD_REG_REG(rd, rn, rm) \
+       _ADD_REG_REG_COND(rd, rn, rm, ARMCOND_AL)
+#define _ADDS_REG_REG_COND(rd, rn, rm, cond) \
+       ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_ADD, rd, rn, rm, cond)
+#define _ADDS_REG_REG(rd, rn, rm) \
+       _ADDS_REG_REG_COND(rd, rn, rm, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn ADD (Rm <shift_type> imm_shift) */
+#define ARM_ADD_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_ADD, rd, rn, rm, shift_type, imm_shift, cond)
+#define ARM_ADD_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \
+       ARM_ADD_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#define ARM_ADDS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_ADD, rd, rn, rm, shift_type, imm_shift, cond)
+#define ARM_ADDS_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \
+       ARM_ADDS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _ADD_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_ADD, rd, rn, rm, shift_type, imm_shift, cond)
+#define _ADD_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \
+       _ADD_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#define _ADDS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_ADD, rd, rn, rm, shift_type, imm_shift, cond)
+#define _ADDS_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \
+       _ADDS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn ADD (Rm <shift_type> Rs) */
+#define ARM_ADD_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \
+       ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_ADD, rd, rn, rm, shift_t, rs, cond)
+#define ARM_ADD_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \
+       ARM_ADD_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#define ARM_ADDS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \
+       ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_ADD, rd, rn, rm, shift_t, rs, cond)
+#define ARM_ADDS_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \
+       ARM_ADDS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _ADD_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_ADD, rd, rn, rm, shift_t, rs, cond)
+#define _ADD_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \
+       _ADD_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#define _ADDS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_ADD, rd, rn, rm, shift_t, rs, cond)
+#define _ADDS_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \
+       _ADDS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#endif
+
+
+/* -- ADC -- */
+
+/* Rd := Rn ADC (imm8 ROR rot) ; rot is power of 2 */
+#define ARM_ADC_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
+       ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_ADC, rd, rn, imm8, rot, cond)
+#define ARM_ADC_REG_IMM(p, rd, rn, imm8, rot) \
+       ARM_ADC_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)
+#define ARM_ADCS_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
+       ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_ADC, rd, rn, imm8, rot, cond)
+#define ARM_ADCS_REG_IMM(p, rd, rn, imm8, rot) \
+       ARM_ADCS_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _ADC_REG_IMM_COND(rd, rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_ADC, rd, rn, imm8, rot, cond)
+#define _ADC_REG_IMM(rd, rn, imm8, rot) \
+       _ADC_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
+#define _ADCS_REG_IMM_COND(rd, rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_ADC, rd, rn, imm8, rot, cond)
+#define _ADCS_REG_IMM(rd, rn, imm8, rot) \
+       _ADCS_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn ADC imm8 */
+#define ARM_ADC_REG_IMM8_COND(p, rd, rn, imm8, cond) \
+       ARM_ADC_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
+#define ARM_ADC_REG_IMM8(p, rd, rn, imm8) \
+       ARM_ADC_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)
+#define ARM_ADCS_REG_IMM8_COND(p, rd, rn, imm8, cond) \
+       ARM_ADCS_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
+#define ARM_ADCS_REG_IMM8(p, rd, rn, imm8) \
+       ARM_ADCS_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _ADC_REG_IMM8_COND(rd, rn, imm8, cond) \
+       _ADC_REG_IMM_COND(rd, rn, imm8, 0, cond)
+#define _ADC_REG_IMM8(rd, rn, imm8) \
+       _ADC_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
+#define _ADCS_REG_IMM8_COND(rd, rn, imm8, cond) \
+       _ADCS_REG_IMM_COND(rd, rn, imm8, 0, cond)
+#define _ADCS_REG_IMM8(rd, rn, imm8) \
+       _ADCS_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn ADC Rm */
+#define ARM_ADC_REG_REG_COND(p, rd, rn, rm, cond) \
+       ARM_DPIOP_REG_REG_COND(p, ARMOP_ADC, rd, rn, rm, cond)
+#define ARM_ADC_REG_REG(p, rd, rn, rm) \
+       ARM_ADC_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL)
+#define ARM_ADCS_REG_REG_COND(p, rd, rn, rm, cond) \
+       ARM_DPIOP_S_REG_REG_COND(p, ARMOP_ADC, rd, rn, rm, cond)
+#define ARM_ADCS_REG_REG(p, rd, rn, rm) \
+       ARM_ADCS_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _ADC_REG_REG_COND(rd, rn, rm, cond) \
+       ARM_IASM_DPIOP_REG_REG_COND(ARMOP_ADC, rd, rn, rm, cond)
+#define _ADC_REG_REG(rd, rn, rm) \
+       _ADC_REG_REG_COND(rd, rn, rm, ARMCOND_AL)
+#define _ADCS_REG_REG_COND(rd, rn, rm, cond) \
+       ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_ADC, rd, rn, rm, cond)
+#define _ADCS_REG_REG(rd, rn, rm) \
+       _ADCS_REG_REG_COND(rd, rn, rm, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn ADC (Rm <shift_type> imm_shift) */
+#define ARM_ADC_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_ADC, rd, rn, rm, shift_type, imm_shift, cond)
+#define ARM_ADC_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \
+       ARM_ADC_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#define ARM_ADCS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_ADC, rd, rn, rm, shift_type, imm_shift, cond)
+#define ARM_ADCS_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \
+       ARM_ADCS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _ADC_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_ADC, rd, rn, rm, shift_type, imm_shift, cond)
+#define _ADC_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \
+       _ADC_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#define _ADCS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_ADC, rd, rn, rm, shift_type, imm_shift, cond)
+#define _ADCS_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \
+       _ADCS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn ADC (Rm <shift_type> Rs) */
+#define ARM_ADC_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \
+       ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_ADC, rd, rn, rm, shift_t, rs, cond)
+#define ARM_ADC_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \
+       ARM_ADC_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#define ARM_ADCS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \
+       ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_ADC, rd, rn, rm, shift_t, rs, cond)
+#define ARM_ADCS_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \
+       ARM_ADCS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _ADC_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_ADC, rd, rn, rm, shift_t, rs, cond)
+#define _ADC_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \
+       _ADC_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#define _ADCS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_ADC, rd, rn, rm, shift_t, rs, cond)
+#define _ADCS_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \
+       _ADCS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#endif
+
+
+/* -- SBC -- */
+
+/* Rd := Rn SBC (imm8 ROR rot) ; rot is power of 2 */
+#define ARM_SBC_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
+       ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_SBC, rd, rn, imm8, rot, cond)
+#define ARM_SBC_REG_IMM(p, rd, rn, imm8, rot) \
+       ARM_SBC_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)
+#define ARM_SBCS_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
+       ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_SBC, rd, rn, imm8, rot, cond)
+#define ARM_SBCS_REG_IMM(p, rd, rn, imm8, rot) \
+       ARM_SBCS_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _SBC_REG_IMM_COND(rd, rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_SBC, rd, rn, imm8, rot, cond)
+#define _SBC_REG_IMM(rd, rn, imm8, rot) \
+       _SBC_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
+#define _SBCS_REG_IMM_COND(rd, rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_SBC, rd, rn, imm8, rot, cond)
+#define _SBCS_REG_IMM(rd, rn, imm8, rot) \
+       _SBCS_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn SBC imm8 */
+#define ARM_SBC_REG_IMM8_COND(p, rd, rn, imm8, cond) \
+       ARM_SBC_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
+#define ARM_SBC_REG_IMM8(p, rd, rn, imm8) \
+       ARM_SBC_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)
+#define ARM_SBCS_REG_IMM8_COND(p, rd, rn, imm8, cond) \
+       ARM_SBCS_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
+#define ARM_SBCS_REG_IMM8(p, rd, rn, imm8) \
+       ARM_SBCS_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _SBC_REG_IMM8_COND(rd, rn, imm8, cond) \
+       _SBC_REG_IMM_COND(rd, rn, imm8, 0, cond)
+#define _SBC_REG_IMM8(rd, rn, imm8) \
+       _SBC_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
+#define _SBCS_REG_IMM8_COND(rd, rn, imm8, cond) \
+       _SBCS_REG_IMM_COND(rd, rn, imm8, 0, cond)
+#define _SBCS_REG_IMM8(rd, rn, imm8) \
+       _SBCS_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn SBC Rm */
+#define ARM_SBC_REG_REG_COND(p, rd, rn, rm, cond) \
+       ARM_DPIOP_REG_REG_COND(p, ARMOP_SBC, rd, rn, rm, cond)
+#define ARM_SBC_REG_REG(p, rd, rn, rm) \
+       ARM_SBC_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL)
+#define ARM_SBCS_REG_REG_COND(p, rd, rn, rm, cond) \
+       ARM_DPIOP_S_REG_REG_COND(p, ARMOP_SBC, rd, rn, rm, cond)
+#define ARM_SBCS_REG_REG(p, rd, rn, rm) \
+       ARM_SBCS_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _SBC_REG_REG_COND(rd, rn, rm, cond) \
+       ARM_IASM_DPIOP_REG_REG_COND(ARMOP_SBC, rd, rn, rm, cond)
+#define _SBC_REG_REG(rd, rn, rm) \
+       _SBC_REG_REG_COND(rd, rn, rm, ARMCOND_AL)
+#define _SBCS_REG_REG_COND(rd, rn, rm, cond) \
+       ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_SBC, rd, rn, rm, cond)
+#define _SBCS_REG_REG(rd, rn, rm) \
+       _SBCS_REG_REG_COND(rd, rn, rm, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn SBC (Rm <shift_type> imm_shift) */
+#define ARM_SBC_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_SBC, rd, rn, rm, shift_type, imm_shift, cond)
+#define ARM_SBC_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \
+       ARM_SBC_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#define ARM_SBCS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_SBC, rd, rn, rm, shift_type, imm_shift, cond)
+#define ARM_SBCS_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \
+       ARM_SBCS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _SBC_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_SBC, rd, rn, rm, shift_type, imm_shift, cond)
+#define _SBC_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \
+       _SBC_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#define _SBCS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_SBC, rd, rn, rm, shift_type, imm_shift, cond)
+#define _SBCS_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \
+       _SBCS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn SBC (Rm <shift_type> Rs) */
+#define ARM_SBC_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \
+       ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_SBC, rd, rn, rm, shift_t, rs, cond)
+#define ARM_SBC_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \
+       ARM_SBC_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#define ARM_SBCS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \
+       ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_SBC, rd, rn, rm, shift_t, rs, cond)
+#define ARM_SBCS_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \
+       ARM_SBCS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _SBC_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_SBC, rd, rn, rm, shift_t, rs, cond)
+#define _SBC_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \
+       _SBC_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#define _SBCS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_SBC, rd, rn, rm, shift_t, rs, cond)
+#define _SBCS_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \
+       _SBCS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#endif
+
+
+/* -- RSC -- */
+
+/* Rd := Rn RSC (imm8 ROR rot) ; rot is power of 2 */
+#define ARM_RSC_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
+       ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_RSC, rd, rn, imm8, rot, cond)
+#define ARM_RSC_REG_IMM(p, rd, rn, imm8, rot) \
+       ARM_RSC_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)
+#define ARM_RSCS_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
+       ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_RSC, rd, rn, imm8, rot, cond)
+#define ARM_RSCS_REG_IMM(p, rd, rn, imm8, rot) \
+       ARM_RSCS_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _RSC_REG_IMM_COND(rd, rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_RSC, rd, rn, imm8, rot, cond)
+#define _RSC_REG_IMM(rd, rn, imm8, rot) \
+       _RSC_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
+#define _RSCS_REG_IMM_COND(rd, rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_RSC, rd, rn, imm8, rot, cond)
+#define _RSCS_REG_IMM(rd, rn, imm8, rot) \
+       _RSCS_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn RSC imm8 */
+#define ARM_RSC_REG_IMM8_COND(p, rd, rn, imm8, cond) \
+       ARM_RSC_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
+#define ARM_RSC_REG_IMM8(p, rd, rn, imm8) \
+       ARM_RSC_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)
+#define ARM_RSCS_REG_IMM8_COND(p, rd, rn, imm8, cond) \
+       ARM_RSCS_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
+#define ARM_RSCS_REG_IMM8(p, rd, rn, imm8) \
+       ARM_RSCS_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _RSC_REG_IMM8_COND(rd, rn, imm8, cond) \
+       _RSC_REG_IMM_COND(rd, rn, imm8, 0, cond)
+#define _RSC_REG_IMM8(rd, rn, imm8) \
+       _RSC_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
+#define _RSCS_REG_IMM8_COND(rd, rn, imm8, cond) \
+       _RSCS_REG_IMM_COND(rd, rn, imm8, 0, cond)
+#define _RSCS_REG_IMM8(rd, rn, imm8) \
+       _RSCS_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn RSC Rm */
+#define ARM_RSC_REG_REG_COND(p, rd, rn, rm, cond) \
+       ARM_DPIOP_REG_REG_COND(p, ARMOP_RSC, rd, rn, rm, cond)
+#define ARM_RSC_REG_REG(p, rd, rn, rm) \
+       ARM_RSC_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL)
+#define ARM_RSCS_REG_REG_COND(p, rd, rn, rm, cond) \
+       ARM_DPIOP_S_REG_REG_COND(p, ARMOP_RSC, rd, rn, rm, cond)
+#define ARM_RSCS_REG_REG(p, rd, rn, rm) \
+       ARM_RSCS_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _RSC_REG_REG_COND(rd, rn, rm, cond) \
+       ARM_IASM_DPIOP_REG_REG_COND(ARMOP_RSC, rd, rn, rm, cond)
+#define _RSC_REG_REG(rd, rn, rm) \
+       _RSC_REG_REG_COND(rd, rn, rm, ARMCOND_AL)
+#define _RSCS_REG_REG_COND(rd, rn, rm, cond) \
+       ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_RSC, rd, rn, rm, cond)
+#define _RSCS_REG_REG(rd, rn, rm) \
+       _RSCS_REG_REG_COND(rd, rn, rm, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn RSC (Rm <shift_type> imm_shift) */
+#define ARM_RSC_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_RSC, rd, rn, rm, shift_type, imm_shift, cond)
+#define ARM_RSC_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \
+       ARM_RSC_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#define ARM_RSCS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_RSC, rd, rn, rm, shift_type, imm_shift, cond)
+#define ARM_RSCS_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \
+       ARM_RSCS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _RSC_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_RSC, rd, rn, rm, shift_type, imm_shift, cond)
+#define _RSC_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \
+       _RSC_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#define _RSCS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_RSC, rd, rn, rm, shift_type, imm_shift, cond)
+#define _RSCS_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \
+       _RSCS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn RSC (Rm <shift_type> Rs) */
+#define ARM_RSC_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \
+       ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_RSC, rd, rn, rm, shift_t, rs, cond)
+#define ARM_RSC_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \
+       ARM_RSC_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#define ARM_RSCS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \
+       ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_RSC, rd, rn, rm, shift_t, rs, cond)
+#define ARM_RSCS_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \
+       ARM_RSCS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _RSC_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_RSC, rd, rn, rm, shift_t, rs, cond)
+#define _RSC_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \
+       _RSC_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#define _RSCS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_RSC, rd, rn, rm, shift_t, rs, cond)
+#define _RSCS_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \
+       _RSCS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#endif
+
+
+/* -- ORR -- */
+
+/* Rd := Rn ORR (imm8 ROR rot) ; rot is power of 2 */
+#define ARM_ORR_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
+       ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_ORR, rd, rn, imm8, rot, cond)
+#define ARM_ORR_REG_IMM(p, rd, rn, imm8, rot) \
+       ARM_ORR_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)
+#define ARM_ORRS_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
+       ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_ORR, rd, rn, imm8, rot, cond)
+#define ARM_ORRS_REG_IMM(p, rd, rn, imm8, rot) \
+       ARM_ORRS_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _ORR_REG_IMM_COND(rd, rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_ORR, rd, rn, imm8, rot, cond)
+#define _ORR_REG_IMM(rd, rn, imm8, rot) \
+       _ORR_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
+#define _ORRS_REG_IMM_COND(rd, rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_ORR, rd, rn, imm8, rot, cond)
+#define _ORRS_REG_IMM(rd, rn, imm8, rot) \
+       _ORRS_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn ORR imm8 */
+#define ARM_ORR_REG_IMM8_COND(p, rd, rn, imm8, cond) \
+       ARM_ORR_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
+#define ARM_ORR_REG_IMM8(p, rd, rn, imm8) \
+       ARM_ORR_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)
+#define ARM_ORRS_REG_IMM8_COND(p, rd, rn, imm8, cond) \
+       ARM_ORRS_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
+#define ARM_ORRS_REG_IMM8(p, rd, rn, imm8) \
+       ARM_ORRS_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _ORR_REG_IMM8_COND(rd, rn, imm8, cond) \
+       _ORR_REG_IMM_COND(rd, rn, imm8, 0, cond)
+#define _ORR_REG_IMM8(rd, rn, imm8) \
+       _ORR_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
+#define _ORRS_REG_IMM8_COND(rd, rn, imm8, cond) \
+       _ORRS_REG_IMM_COND(rd, rn, imm8, 0, cond)
+#define _ORRS_REG_IMM8(rd, rn, imm8) \
+       _ORRS_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn ORR Rm */
+#define ARM_ORR_REG_REG_COND(p, rd, rn, rm, cond) \
+       ARM_DPIOP_REG_REG_COND(p, ARMOP_ORR, rd, rn, rm, cond)
+#define ARM_ORR_REG_REG(p, rd, rn, rm) \
+       ARM_ORR_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL)
+#define ARM_ORRS_REG_REG_COND(p, rd, rn, rm, cond) \
+       ARM_DPIOP_S_REG_REG_COND(p, ARMOP_ORR, rd, rn, rm, cond)
+#define ARM_ORRS_REG_REG(p, rd, rn, rm) \
+       ARM_ORRS_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _ORR_REG_REG_COND(rd, rn, rm, cond) \
+       ARM_IASM_DPIOP_REG_REG_COND(ARMOP_ORR, rd, rn, rm, cond)
+#define _ORR_REG_REG(rd, rn, rm) \
+       _ORR_REG_REG_COND(rd, rn, rm, ARMCOND_AL)
+#define _ORRS_REG_REG_COND(rd, rn, rm, cond) \
+       ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_ORR, rd, rn, rm, cond)
+#define _ORRS_REG_REG(rd, rn, rm) \
+       _ORRS_REG_REG_COND(rd, rn, rm, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn ORR (Rm <shift_type> imm_shift) */
+#define ARM_ORR_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_ORR, rd, rn, rm, shift_type, imm_shift, cond)
+#define ARM_ORR_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \
+       ARM_ORR_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#define ARM_ORRS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_ORR, rd, rn, rm, shift_type, imm_shift, cond)
+#define ARM_ORRS_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \
+       ARM_ORRS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _ORR_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_ORR, rd, rn, rm, shift_type, imm_shift, cond)
+#define _ORR_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \
+       _ORR_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#define _ORRS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_ORR, rd, rn, rm, shift_type, imm_shift, cond)
+#define _ORRS_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \
+       _ORRS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn ORR (Rm <shift_type> Rs) */
+#define ARM_ORR_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \
+       ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_ORR, rd, rn, rm, shift_t, rs, cond)
+#define ARM_ORR_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \
+       ARM_ORR_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#define ARM_ORRS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \
+       ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_ORR, rd, rn, rm, shift_t, rs, cond)
+#define ARM_ORRS_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \
+       ARM_ORRS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _ORR_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_ORR, rd, rn, rm, shift_t, rs, cond)
+#define _ORR_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \
+       _ORR_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#define _ORRS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_ORR, rd, rn, rm, shift_t, rs, cond)
+#define _ORRS_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \
+       _ORRS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#endif
+
+
+/* -- BIC -- */
+
+/* Rd := Rn BIC (imm8 ROR rot) ; rot is power of 2 */
+#define ARM_BIC_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
+       ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_BIC, rd, rn, imm8, rot, cond)
+#define ARM_BIC_REG_IMM(p, rd, rn, imm8, rot) \
+       ARM_BIC_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)
+#define ARM_BICS_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
+       ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_BIC, rd, rn, imm8, rot, cond)
+#define ARM_BICS_REG_IMM(p, rd, rn, imm8, rot) \
+       ARM_BICS_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _BIC_REG_IMM_COND(rd, rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_BIC, rd, rn, imm8, rot, cond)
+#define _BIC_REG_IMM(rd, rn, imm8, rot) \
+       _BIC_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
+#define _BICS_REG_IMM_COND(rd, rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_BIC, rd, rn, imm8, rot, cond)
+#define _BICS_REG_IMM(rd, rn, imm8, rot) \
+       _BICS_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn BIC imm8 */
+#define ARM_BIC_REG_IMM8_COND(p, rd, rn, imm8, cond) \
+       ARM_BIC_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
+#define ARM_BIC_REG_IMM8(p, rd, rn, imm8) \
+       ARM_BIC_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)
+#define ARM_BICS_REG_IMM8_COND(p, rd, rn, imm8, cond) \
+       ARM_BICS_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
+#define ARM_BICS_REG_IMM8(p, rd, rn, imm8) \
+       ARM_BICS_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _BIC_REG_IMM8_COND(rd, rn, imm8, cond) \
+       _BIC_REG_IMM_COND(rd, rn, imm8, 0, cond)
+#define _BIC_REG_IMM8(rd, rn, imm8) \
+       _BIC_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
+#define _BICS_REG_IMM8_COND(rd, rn, imm8, cond) \
+       _BICS_REG_IMM_COND(rd, rn, imm8, 0, cond)
+#define _BICS_REG_IMM8(rd, rn, imm8) \
+       _BICS_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn BIC Rm */
+#define ARM_BIC_REG_REG_COND(p, rd, rn, rm, cond) \
+       ARM_DPIOP_REG_REG_COND(p, ARMOP_BIC, rd, rn, rm, cond)
+#define ARM_BIC_REG_REG(p, rd, rn, rm) \
+       ARM_BIC_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL)
+#define ARM_BICS_REG_REG_COND(p, rd, rn, rm, cond) \
+       ARM_DPIOP_S_REG_REG_COND(p, ARMOP_BIC, rd, rn, rm, cond)
+#define ARM_BICS_REG_REG(p, rd, rn, rm) \
+       ARM_BICS_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _BIC_REG_REG_COND(rd, rn, rm, cond) \
+       ARM_IASM_DPIOP_REG_REG_COND(ARMOP_BIC, rd, rn, rm, cond)
+#define _BIC_REG_REG(rd, rn, rm) \
+       _BIC_REG_REG_COND(rd, rn, rm, ARMCOND_AL)
+#define _BICS_REG_REG_COND(rd, rn, rm, cond) \
+       ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_BIC, rd, rn, rm, cond)
+#define _BICS_REG_REG(rd, rn, rm) \
+       _BICS_REG_REG_COND(rd, rn, rm, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn BIC (Rm <shift_type> imm_shift) */
+#define ARM_BIC_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_BIC, rd, rn, rm, shift_type, imm_shift, cond)
+#define ARM_BIC_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \
+       ARM_BIC_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#define ARM_BICS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_BIC, rd, rn, rm, shift_type, imm_shift, cond)
+#define ARM_BICS_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \
+       ARM_BICS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _BIC_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_BIC, rd, rn, rm, shift_type, imm_shift, cond)
+#define _BIC_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \
+       _BIC_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#define _BICS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_BIC, rd, rn, rm, shift_type, imm_shift, cond)
+#define _BICS_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \
+       _BICS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn BIC (Rm <shift_type> Rs) */
+#define ARM_BIC_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \
+       ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_BIC, rd, rn, rm, shift_t, rs, cond)
+#define ARM_BIC_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \
+       ARM_BIC_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#define ARM_BICS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \
+       ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_BIC, rd, rn, rm, shift_t, rs, cond)
+#define ARM_BICS_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \
+       ARM_BICS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _BIC_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_BIC, rd, rn, rm, shift_t, rs, cond)
+#define _BIC_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \
+       _BIC_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#define _BICS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_BIC, rd, rn, rm, shift_t, rs, cond)
+#define _BICS_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \
+       _BICS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#endif
+
+
+
+
+
+
+/* DPIs, comparison */
+
+/* PSR := TST Rn, (imm8 ROR 2*rot) */
+#define ARM_TST_REG_IMM_COND(p, rn, imm8, rot, cond) \
+       ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_TST, 0, rn, imm8, rot, cond)
+#define ARM_TST_REG_IMM(p, rn, imm8, rot) \
+       ARM_TST_REG_IMM_COND(p, rn, imm8, rot, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _TST_REG_IMM_COND(rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_TST, 0, rn, imm8, rot, cond)
+#define _TST_REG_IMM(rn, imm8, rot) \
+       _TST_REG_IMM_COND(rn, imm8, rot, ARMCOND_AL)
+#endif
+
+
+/* PSR := TST Rn, imm8 */
+#define ARM_TST_REG_IMM8_COND(p, rn, imm8, cond) \
+       ARM_TST_REG_IMM_COND(p, rn, imm8, 0, cond)
+#define ARM_TST_REG_IMM8(p, rn, imm8) \
+       ARM_TST_REG_IMM8_COND(p, rn, imm8, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _TST_REG_IMM8_COND(rn, imm8, cond) \
+       _TST_REG_IMM_COND(rn, imm8, 0, cond)
+#define _TST_REG_IMM8(rn, imm8) \
+       _TST_REG_IMM8_COND(rn, imm8, ARMCOND_AL)
+#endif
+
+
+/* PSR := TST Rn, Rm */
+#define ARM_TST_REG_REG_COND(p, rn, rm, cond) \
+       ARM_DPIOP_S_REG_REG_COND(p, ARMOP_TST, 0, rn, rm, cond)
+#define ARM_TST_REG_REG(p, rn, rm) \
+       ARM_TST_REG_REG_COND(p, rn, rm, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _TST_REG_REG_COND(rn, rm, cond) \
+       ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_TST, 0, rn, rm, cond)
+#define _TST_REG_REG(rn, rm) \
+       _TST_REG_REG_COND(rn, rm, ARMCOND_AL)
+#endif
+
+
+/* PSR := TST Rn, (Rm <shift_type> imm8) */
+#define ARM_TST_REG_IMMSHIFT_COND(p, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_TST, 0, rn, rm, shift_type, imm_shift, cond)
+#define ARM_TST_REG_IMMSHIFT(p, rn, rm, shift_type, imm_shift) \
+       ARM_TST_REG_IMMSHIFT_COND(p, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _TST_REG_IMMSHIFT_COND(rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_TST, 0, rn, rm, shift_type, imm_shift, cond)
+#define _TST_REG_IMMSHIFT(rn, rm, shift_type, imm_shift) \
+       _TST_REG_IMMSHIFT_COND(rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#endif
+
+
+/* PSR := TEQ Rn, (imm8 ROR 2*rot) */
+#define ARM_TEQ_REG_IMM_COND(p, rn, imm8, rot, cond) \
+       ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_TEQ, 0, rn, imm8, rot, cond)
+#define ARM_TEQ_REG_IMM(p, rn, imm8, rot) \
+       ARM_TEQ_REG_IMM_COND(p, rn, imm8, rot, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _TEQ_REG_IMM_COND(rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_TEQ, 0, rn, imm8, rot, cond)
+#define _TEQ_REG_IMM(rn, imm8, rot) \
+       _TEQ_REG_IMM_COND(rn, imm8, rot, ARMCOND_AL)
+#endif
+
+
+/* PSR := TEQ Rn, imm8 */
+#define ARM_TEQ_REG_IMM8_COND(p, rn, imm8, cond) \
+       ARM_TEQ_REG_IMM_COND(p, rn, imm8, 0, cond)
+#define ARM_TEQ_REG_IMM8(p, rn, imm8) \
+       ARM_TEQ_REG_IMM8_COND(p, rn, imm8, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _TEQ_REG_IMM8_COND(rn, imm8, cond) \
+       _TEQ_REG_IMM_COND(rn, imm8, 0, cond)
+#define _TEQ_REG_IMM8(rn, imm8) \
+       _TEQ_REG_IMM8_COND(rn, imm8, ARMCOND_AL)
+#endif
+
+
+/* PSR := TEQ Rn, Rm */
+#define ARM_TEQ_REG_REG_COND(p, rn, rm, cond) \
+       ARM_DPIOP_S_REG_REG_COND(p, ARMOP_TEQ, 0, rn, rm, cond)
+#define ARM_TEQ_REG_REG(p, rn, rm) \
+       ARM_TEQ_REG_REG_COND(p, rn, rm, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _TEQ_REG_REG_COND(rn, rm, cond) \
+       ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_TEQ, 0, rn, rm, cond)
+#define _TEQ_REG_REG(rn, rm) \
+       _TEQ_REG_REG_COND(rn, rm, ARMCOND_AL)
+#endif
+
+
+/* PSR := TEQ Rn, (Rm <shift_type> imm8) */
+#define ARM_TEQ_REG_IMMSHIFT_COND(p, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_TEQ, 0, rn, rm, shift_type, imm_shift, cond)
+#define ARM_TEQ_REG_IMMSHIFT(p, rn, rm, shift_type, imm_shift) \
+       ARM_TEQ_REG_IMMSHIFT_COND(p, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _TEQ_REG_IMMSHIFT_COND(rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_TEQ, 0, rn, rm, shift_type, imm_shift, cond)
+#define _TEQ_REG_IMMSHIFT(rn, rm, shift_type, imm_shift) \
+       _TEQ_REG_IMMSHIFT_COND(rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#endif
+
+
+/* PSR := CMP Rn, (imm8 ROR 2*rot) */
+#define ARM_CMP_REG_IMM_COND(p, rn, imm8, rot, cond) \
+       ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_CMP, 0, rn, imm8, rot, cond)
+#define ARM_CMP_REG_IMM(p, rn, imm8, rot) \
+       ARM_CMP_REG_IMM_COND(p, rn, imm8, rot, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _CMP_REG_IMM_COND(rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_CMP, 0, rn, imm8, rot, cond)
+#define _CMP_REG_IMM(rn, imm8, rot) \
+       _CMP_REG_IMM_COND(rn, imm8, rot, ARMCOND_AL)
+#endif
+
+
+/* PSR := CMP Rn, imm8 */
+#define ARM_CMP_REG_IMM8_COND(p, rn, imm8, cond) \
+       ARM_CMP_REG_IMM_COND(p, rn, imm8, 0, cond)
+#define ARM_CMP_REG_IMM8(p, rn, imm8) \
+       ARM_CMP_REG_IMM8_COND(p, rn, imm8, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _CMP_REG_IMM8_COND(rn, imm8, cond) \
+       _CMP_REG_IMM_COND(rn, imm8, 0, cond)
+#define _CMP_REG_IMM8(rn, imm8) \
+       _CMP_REG_IMM8_COND(rn, imm8, ARMCOND_AL)
+#endif
+
+
+/* PSR := CMP Rn, Rm */
+#define ARM_CMP_REG_REG_COND(p, rn, rm, cond) \
+       ARM_DPIOP_S_REG_REG_COND(p, ARMOP_CMP, 0, rn, rm, cond)
+#define ARM_CMP_REG_REG(p, rn, rm) \
+       ARM_CMP_REG_REG_COND(p, rn, rm, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _CMP_REG_REG_COND(rn, rm, cond) \
+       ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_CMP, 0, rn, rm, cond)
+#define _CMP_REG_REG(rn, rm) \
+       _CMP_REG_REG_COND(rn, rm, ARMCOND_AL)
+#endif
+
+
+/* PSR := CMP Rn, (Rm <shift_type> imm8) */
+#define ARM_CMP_REG_IMMSHIFT_COND(p, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_CMP, 0, rn, rm, shift_type, imm_shift, cond)
+#define ARM_CMP_REG_IMMSHIFT(p, rn, rm, shift_type, imm_shift) \
+       ARM_CMP_REG_IMMSHIFT_COND(p, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _CMP_REG_IMMSHIFT_COND(rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_CMP, 0, rn, rm, shift_type, imm_shift, cond)
+#define _CMP_REG_IMMSHIFT(rn, rm, shift_type, imm_shift) \
+       _CMP_REG_IMMSHIFT_COND(rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#endif
+
+
+/* PSR := CMN Rn, (imm8 ROR 2*rot) */
+#define ARM_CMN_REG_IMM_COND(p, rn, imm8, rot, cond) \
+       ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_CMN, 0, rn, imm8, rot, cond)
+#define ARM_CMN_REG_IMM(p, rn, imm8, rot) \
+       ARM_CMN_REG_IMM_COND(p, rn, imm8, rot, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _CMN_REG_IMM_COND(rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_CMN, 0, rn, imm8, rot, cond)
+#define _CMN_REG_IMM(rn, imm8, rot) \
+       _CMN_REG_IMM_COND(rn, imm8, rot, ARMCOND_AL)
+#endif
+
+
+/* PSR := CMN Rn, imm8 */
+#define ARM_CMN_REG_IMM8_COND(p, rn, imm8, cond) \
+       ARM_CMN_REG_IMM_COND(p, rn, imm8, 0, cond)
+#define ARM_CMN_REG_IMM8(p, rn, imm8) \
+       ARM_CMN_REG_IMM8_COND(p, rn, imm8, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _CMN_REG_IMM8_COND(rn, imm8, cond) \
+       _CMN_REG_IMM_COND(rn, imm8, 0, cond)
+#define _CMN_REG_IMM8(rn, imm8) \
+       _CMN_REG_IMM8_COND(rn, imm8, ARMCOND_AL)
+#endif
+
+
+/* PSR := CMN Rn, Rm */
+#define ARM_CMN_REG_REG_COND(p, rn, rm, cond) \
+       ARM_DPIOP_S_REG_REG_COND(p, ARMOP_CMN, 0, rn, rm, cond)
+#define ARM_CMN_REG_REG(p, rn, rm) \
+       ARM_CMN_REG_REG_COND(p, rn, rm, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _CMN_REG_REG_COND(rn, rm, cond) \
+       ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_CMN, 0, rn, rm, cond)
+#define _CMN_REG_REG(rn, rm) \
+       _CMN_REG_REG_COND(rn, rm, ARMCOND_AL)
+#endif
+
+
+/* PSR := CMN Rn, (Rm <shift_type> imm8) */
+#define ARM_CMN_REG_IMMSHIFT_COND(p, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_CMN, 0, rn, rm, shift_type, imm_shift, cond)
+#define ARM_CMN_REG_IMMSHIFT(p, rn, rm, shift_type, imm_shift) \
+       ARM_CMN_REG_IMMSHIFT_COND(p, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _CMN_REG_IMMSHIFT_COND(rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_CMN, 0, rn, rm, shift_type, imm_shift, cond)
+#define _CMN_REG_IMMSHIFT(rn, rm, shift_type, imm_shift) \
+       _CMN_REG_IMMSHIFT_COND(rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#endif
+
+
+
+/* end generated */
+

diff --git a/mono/arch/arm/arm_vfpmacros.h b/mono/arch/arm/arm_vfpmacros.h
new file mode 100644 (file)
index 0000000..f502645
--- /dev/null
+++ b/mono/arch/arm/arm_vfpmacros.h
@@ -0,0 +1,299 @@
+/* Macros for VFP ops, auto-generated from template */
+
+
+/* dyadic */
+
+/* -- ADD -- */
+
+
+/* Fd := Fn ADD Fm */
+#define ARM_VFP_ADDD_COND(p, rd, rn, rm, cond) \
+       ARM_EMIT((p), ARM_DEF_VFP_DYADIC(cond,ARM_VFP_COPROC_DOUBLE,ARM_VFP_ADD,rd,rn,rm))
+#define ARM_VFP_ADDD(p, rd, rn, rm) \
+       ARM_VFP_ADDD_COND(p, rd, rn, rm, ARMCOND_AL)
+
+#define ARM_VFP_ADDS_COND(p, rd, rn, rm, cond) \
+       ARM_EMIT((p), ARM_DEF_VFP_DYADIC(cond,ARM_VFP_COPROC_SINGLE,ARM_VFP_ADD,rd,rn,rm))
+#define ARM_VFP_ADDS(p, rd, rn, rm) \
+       ARM_VFP_ADDS_COND(p, rd, rn, rm, ARMCOND_AL)
+
+
+/* -- SUB -- */
+
+
+/* Fd := Fn SUB Fm */
+#define ARM_VFP_SUBD_COND(p, rd, rn, rm, cond) \
+       ARM_EMIT((p), ARM_DEF_VFP_DYADIC(cond,ARM_VFP_COPROC_DOUBLE,ARM_VFP_SUB,rd,rn,rm))
+#define ARM_VFP_SUBD(p, rd, rn, rm) \
+       ARM_VFP_SUBD_COND(p, rd, rn, rm, ARMCOND_AL)
+
+#define ARM_VFP_SUBS_COND(p, rd, rn, rm, cond) \
+       ARM_EMIT((p), ARM_DEF_VFP_DYADIC(cond,ARM_VFP_COPROC_SINGLE,ARM_VFP_SUB,rd,rn,rm))
+#define ARM_VFP_SUBS(p, rd, rn, rm) \
+       ARM_VFP_SUBS_COND(p, rd, rn, rm, ARMCOND_AL)
+
+
+/* -- MUL -- */
+
+
+/* Fd := Fn MUL Fm */
+#define ARM_VFP_MULD_COND(p, rd, rn, rm, cond) \
+       ARM_EMIT((p), ARM_DEF_VFP_DYADIC(cond,ARM_VFP_COPROC_DOUBLE,ARM_VFP_MUL,rd,rn,rm))
+#define ARM_VFP_MULD(p, rd, rn, rm) \
+       ARM_VFP_MULD_COND(p, rd, rn, rm, ARMCOND_AL)
+
+#define ARM_VFP_MULS_COND(p, rd, rn, rm, cond) \
+       ARM_EMIT((p), ARM_DEF_VFP_DYADIC(cond,ARM_VFP_COPROC_SINGLE,ARM_VFP_MUL,rd,rn,rm))
+#define ARM_VFP_MULS(p, rd, rn, rm) \
+       ARM_VFP_MULS_COND(p, rd, rn, rm, ARMCOND_AL)
+
+
+/* -- NMUL -- */
+
+
+/* Fd := Fn NMUL Fm */
+#define ARM_VFP_NMULD_COND(p, rd, rn, rm, cond) \
+       ARM_EMIT((p), ARM_DEF_VFP_DYADIC(cond,ARM_VFP_COPROC_DOUBLE,ARM_VFP_NMUL,rd,rn,rm))
+#define ARM_VFP_NMULD(p, rd, rn, rm) \
+       ARM_VFP_NMULD_COND(p, rd, rn, rm, ARMCOND_AL)
+
+#define ARM_VFP_NMULS_COND(p, rd, rn, rm, cond) \
+       ARM_EMIT((p), ARM_DEF_VFP_DYADIC(cond,ARM_VFP_COPROC_SINGLE,ARM_VFP_NMUL,rd,rn,rm))
+#define ARM_VFP_NMULS(p, rd, rn, rm) \
+       ARM_VFP_NMULS_COND(p, rd, rn, rm, ARMCOND_AL)
+
+
+/* -- DIV -- */
+
+
+/* Fd := Fn DIV Fm */
+#define ARM_VFP_DIVD_COND(p, rd, rn, rm, cond) \
+       ARM_EMIT((p), ARM_DEF_VFP_DYADIC(cond,ARM_VFP_COPROC_DOUBLE,ARM_VFP_DIV,rd,rn,rm))
+#define ARM_VFP_DIVD(p, rd, rn, rm) \
+       ARM_VFP_DIVD_COND(p, rd, rn, rm, ARMCOND_AL)
+
+#define ARM_VFP_DIVS_COND(p, rd, rn, rm, cond) \
+       ARM_EMIT((p), ARM_DEF_VFP_DYADIC(cond,ARM_VFP_COPROC_SINGLE,ARM_VFP_DIV,rd,rn,rm))
+#define ARM_VFP_DIVS(p, rd, rn, rm) \
+       ARM_VFP_DIVS_COND(p, rd, rn, rm, ARMCOND_AL)
+
+
+
+/* monadic */
+
+/* -- CPY -- */
+
+
+/* Fd := CPY Fm */
+
+#define ARM_CPYD_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_DOUBLE,ARM_VFP_CPY,(dreg),(sreg)))
+#define ARM_CPYD(p,dreg,sreg)      ARM_CPYD_COND(p,dreg,sreg,ARMCOND_AL)
+
+#define ARM_CPYS_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_SINGLE,ARM_VFP_CPY,(dreg),(sreg)))
+#define ARM_CPYS(p,dreg,sreg)      ARM_CPYS_COND(p,dreg,sreg,ARMCOND_AL)
+
+
+/* -- ABS -- */
+
+
+/* Fd := ABS Fm */
+
+#define ARM_ABSD_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_DOUBLE,ARM_VFP_ABS,(dreg),(sreg)))
+#define ARM_ABSD(p,dreg,sreg)      ARM_ABSD_COND(p,dreg,sreg,ARMCOND_AL)
+
+#define ARM_ABSS_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_SINGLE,ARM_VFP_ABS,(dreg),(sreg)))
+#define ARM_ABSS(p,dreg,sreg)      ARM_ABSS_COND(p,dreg,sreg,ARMCOND_AL)
+
+
+/* -- NEG -- */
+
+
+/* Fd := NEG Fm */
+
+#define ARM_NEGD_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_DOUBLE,ARM_VFP_NEG,(dreg),(sreg)))
+#define ARM_NEGD(p,dreg,sreg)      ARM_NEGD_COND(p,dreg,sreg,ARMCOND_AL)
+
+#define ARM_NEGS_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_SINGLE,ARM_VFP_NEG,(dreg),(sreg)))
+#define ARM_NEGS(p,dreg,sreg)      ARM_NEGS_COND(p,dreg,sreg,ARMCOND_AL)
+
+
+/* -- SQRT -- */
+
+
+/* Fd := SQRT Fm */
+
+#define ARM_SQRTD_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_DOUBLE,ARM_VFP_SQRT,(dreg),(sreg)))
+#define ARM_SQRTD(p,dreg,sreg)      ARM_SQRTD_COND(p,dreg,sreg,ARMCOND_AL)
+
+#define ARM_SQRTS_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_SINGLE,ARM_VFP_SQRT,(dreg),(sreg)))
+#define ARM_SQRTS(p,dreg,sreg)      ARM_SQRTS_COND(p,dreg,sreg,ARMCOND_AL)
+
+
+/* -- CMP -- */
+
+
+/* Fd := CMP Fm */
+
+#define ARM_CMPD_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_DOUBLE,ARM_VFP_CMP,(dreg),(sreg)))
+#define ARM_CMPD(p,dreg,sreg)      ARM_CMPD_COND(p,dreg,sreg,ARMCOND_AL)
+
+#define ARM_CMPS_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_SINGLE,ARM_VFP_CMP,(dreg),(sreg)))
+#define ARM_CMPS(p,dreg,sreg)      ARM_CMPS_COND(p,dreg,sreg,ARMCOND_AL)
+
+
+/* -- CMPE -- */
+
+
+/* Fd := CMPE Fm */
+
+#define ARM_CMPED_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_DOUBLE,ARM_VFP_CMPE,(dreg),(sreg)))
+#define ARM_CMPED(p,dreg,sreg)      ARM_CMPED_COND(p,dreg,sreg,ARMCOND_AL)
+
+#define ARM_CMPES_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_SINGLE,ARM_VFP_CMPE,(dreg),(sreg)))
+#define ARM_CMPES(p,dreg,sreg)      ARM_CMPES_COND(p,dreg,sreg,ARMCOND_AL)
+
+
+/* -- CMPZ -- */
+
+
+/* Fd := CMPZ Fm */
+
+#define ARM_CMPZD_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_DOUBLE,ARM_VFP_CMPZ,(dreg),(sreg)))
+#define ARM_CMPZD(p,dreg,sreg)      ARM_CMPZD_COND(p,dreg,sreg,ARMCOND_AL)
+
+#define ARM_CMPZS_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_SINGLE,ARM_VFP_CMPZ,(dreg),(sreg)))
+#define ARM_CMPZS(p,dreg,sreg)      ARM_CMPZS_COND(p,dreg,sreg,ARMCOND_AL)
+
+
+/* -- CMPEZ -- */
+
+
+/* Fd := CMPEZ Fm */
+
+#define ARM_CMPEZD_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_DOUBLE,ARM_VFP_CMPEZ,(dreg),(sreg)))
+#define ARM_CMPEZD(p,dreg,sreg)      ARM_CMPEZD_COND(p,dreg,sreg,ARMCOND_AL)
+
+#define ARM_CMPEZS_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_SINGLE,ARM_VFP_CMPEZ,(dreg),(sreg)))
+#define ARM_CMPEZS(p,dreg,sreg)      ARM_CMPEZS_COND(p,dreg,sreg,ARMCOND_AL)
+
+
+/* -- CVT -- */
+
+
+/* Fd := CVT Fm */
+
+#define ARM_CVTD_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_DOUBLE,ARM_VFP_CVT,(dreg),(sreg)))
+#define ARM_CVTD(p,dreg,sreg)      ARM_CVTD_COND(p,dreg,sreg,ARMCOND_AL)
+
+#define ARM_CVTS_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_SINGLE,ARM_VFP_CVT,(dreg),(sreg)))
+#define ARM_CVTS(p,dreg,sreg)      ARM_CVTS_COND(p,dreg,sreg,ARMCOND_AL)
+
+
+/* -- UITO -- */
+
+
+/* Fd := UITO Fm */
+
+#define ARM_UITOD_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_DOUBLE,ARM_VFP_UITO,(dreg),(sreg)))
+#define ARM_UITOD(p,dreg,sreg)      ARM_UITOD_COND(p,dreg,sreg,ARMCOND_AL)
+
+#define ARM_UITOS_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_SINGLE,ARM_VFP_UITO,(dreg),(sreg)))
+#define ARM_UITOS(p,dreg,sreg)      ARM_UITOS_COND(p,dreg,sreg,ARMCOND_AL)
+
+
+/* -- SITO -- */
+
+
+/* Fd := SITO Fm */
+
+#define ARM_SITOD_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_DOUBLE,ARM_VFP_SITO,(dreg),(sreg)))
+#define ARM_SITOD(p,dreg,sreg)      ARM_SITOD_COND(p,dreg,sreg,ARMCOND_AL)
+
+#define ARM_SITOS_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_SINGLE,ARM_VFP_SITO,(dreg),(sreg)))
+#define ARM_SITOS(p,dreg,sreg)      ARM_SITOS_COND(p,dreg,sreg,ARMCOND_AL)
+
+
+/* -- TOUI -- */
+
+
+/* Fd := TOUI Fm */
+
+#define ARM_TOUID_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_DOUBLE,ARM_VFP_TOUI,(dreg),(sreg)))
+#define ARM_TOUID(p,dreg,sreg)      ARM_TOUID_COND(p,dreg,sreg,ARMCOND_AL)
+
+#define ARM_TOUIS_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_SINGLE,ARM_VFP_TOUI,(dreg),(sreg)))
+#define ARM_TOUIS(p,dreg,sreg)      ARM_TOUIS_COND(p,dreg,sreg,ARMCOND_AL)
+
+
+/* -- TOSI -- */
+
+
+/* Fd := TOSI Fm */
+
+#define ARM_TOSID_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_DOUBLE,ARM_VFP_TOSI,(dreg),(sreg)))
+#define ARM_TOSID(p,dreg,sreg)      ARM_TOSID_COND(p,dreg,sreg,ARMCOND_AL)
+
+#define ARM_TOSIS_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_SINGLE,ARM_VFP_TOSI,(dreg),(sreg)))
+#define ARM_TOSIS(p,dreg,sreg)      ARM_TOSIS_COND(p,dreg,sreg,ARMCOND_AL)
+
+
+/* -- TOUIZ -- */
+
+
+/* Fd := TOUIZ Fm */
+
+#define ARM_TOUIZD_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_DOUBLE,ARM_VFP_TOUIZ,(dreg),(sreg)))
+#define ARM_TOUIZD(p,dreg,sreg)      ARM_TOUIZD_COND(p,dreg,sreg,ARMCOND_AL)
+
+#define ARM_TOUIZS_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_SINGLE,ARM_VFP_TOUIZ,(dreg),(sreg)))
+#define ARM_TOUIZS(p,dreg,sreg)      ARM_TOUIZS_COND(p,dreg,sreg,ARMCOND_AL)
+
+
+/* -- TOSIZ -- */
+
+
+/* Fd := TOSIZ Fm */
+
+#define ARM_TOSIZD_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_DOUBLE,ARM_VFP_TOSIZ,(dreg),(sreg)))
+#define ARM_TOSIZD(p,dreg,sreg)      ARM_TOSIZD_COND(p,dreg,sreg,ARMCOND_AL)
+
+#define ARM_TOSIZS_COND(p,dreg,sreg,cond) \
+        ARM_EMIT((p), ARM_DEF_VFP_MONADIC((cond),ARM_VFP_COPROC_SINGLE,ARM_VFP_TOSIZ,(dreg),(sreg)))
+#define ARM_TOSIZS(p,dreg,sreg)      ARM_TOSIZS_COND(p,dreg,sreg,ARMCOND_AL)
+
+
+
+
+
+
+/* end generated */
+

diff --git a/mono/tests/testing_gac/Makefile.am b/mono/tests/testing_gac/Makefile.am
index 3f4668b0f15b7805274f1abc36dab7442dd41913..d65b359ce5d46194ebf72adb7eb5163027245362 100644 (file)
--- a/mono/tests/testing_gac/Makefile.am
+++ b/mono/tests/testing_gac/Makefile.am
@@ -78,7 +78,7 @@ APP_SIGNED_V1_AOT=$(APP_SIGNED_V1_EXE:.exe=.exe$(PLATFORM_AOT_SUFFIX))
 endif
 
 
-SIGNING_KEY= testkey.snk
+SIGNING_KEY= $(srcdir)/testkey.snk
 
 # prefix for the testing gac.  gacutil will add lib/mono/gac directories
 GACDIR=.

diff --git a/tools/offsets-tool/Makefile b/tools/offsets-tool/Makefile
index 4869bf291724bf41151719a4ca70023d19843e7b..c974d0364aee48fc1e20e8d8a67c82b445c4403e 100644 (file)
--- a/tools/offsets-tool/Makefile
+++ b/tools/offsets-tool/Makefile
@@ -20,7 +20,7 @@ else
        endif
        ifeq ($(UNAME_S),Darwin)
                CPPSHARP_OS=osx
-               CPPSHARP_ARCH=32
+               CPPSHARP_ARCH=64
        endif
 endif
 
@@ -36,7 +36,7 @@ SRC_ROOT = ../..
 
 MONO_OPTIONS_SRC = $(SRC_ROOT)/mcs/class/Mono.Options/Mono.Options/Options.cs
 
-HASH=60f763a9
+HASH=9dc880dd
 .stamp-clone-$(HASH):
        rm -Rf $(CPPSHARP_BASE_DIR)
        git clone -b $(HASH) --depth 1 git://github.com/xamarin/CppSharpBinaries.git $(CPPSHARP_BASE_DIR) && touch $@
@@ -62,4 +62,4 @@ update:
 gen-proj:
        $(CPPSHARP_DIR)/premake5 vs2012
 
-all: MonoAotOffsetsDumper.exe
\ No newline at end of file
+all: MonoAotOffsetsDumper.exe

diff --git a/tools/offsets-tool/MonoAotOffsetsDumper.cs b/tools/offsets-tool/MonoAotOffsetsDumper.cs
index f167566eef3609d121bcb9ebcc3ac6cf0d860d85..54016f99faabf8b5b3d422139a4207878a9c8a82 100644 (file)
--- a/tools/offsets-tool/MonoAotOffsetsDumper.cs
+++ b/tools/offsets-tool/MonoAotOffsetsDumper.cs
@@ -219,8 +219,7 @@ namespace CppSharp
 
                 var options = new DriverOptions();
 
-                var log = new TextDiagnosticPrinter();
-                var driver = new Driver(options, log);
+                var driver = new Driver(options);
 
                 Setup(driver, target);
                 driver.Setup();