3 * x86 backend for the Mono code generator
6 * Paolo Molaro (lupus@ximian.com)
7 * Dietmar Maurer (dietmar@ximian.com)
10 * Copyright 2003 Ximian, Inc.
11 * Copyright 2003-2011 Novell Inc.
12 * Copyright 2011 Xamarin Inc.
13 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
22 #include <mono/metadata/abi-details.h>
23 #include <mono/metadata/appdomain.h>
24 #include <mono/metadata/debug-helpers.h>
25 #include <mono/metadata/threads.h>
26 #include <mono/metadata/profiler-private.h>
27 #include <mono/metadata/mono-debug.h>
28 #include <mono/metadata/gc-internals.h>
29 #include <mono/utils/mono-math.h>
30 #include <mono/utils/mono-counters.h>
31 #include <mono/utils/mono-mmap.h>
32 #include <mono/utils/mono-memory-model.h>
33 #include <mono/utils/mono-hwcap.h>
34 #include <mono/utils/mono-threads.h>
44 static gboolean optimize_for_xen = TRUE;
46 #define optimize_for_xen 0
50 /* The single step trampoline */
51 static gpointer ss_trampoline;
53 /* The breakpoint trampoline */
54 static gpointer bp_trampoline;
56 /* This mutex protects architecture specific caches */
57 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
58 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
59 static mono_mutex_t mini_arch_mutex;
61 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
66 /* Under windows, the default pinvoke calling convention is stdcall */
67 #define CALLCONV_IS_STDCALL(sig) ((sig)->pinvoke && ((sig)->call_convention == MONO_CALL_STDCALL || (sig)->call_convention == MONO_CALL_DEFAULT || (sig)->call_convention == MONO_CALL_THISCALL))
69 #define CALLCONV_IS_STDCALL(sig) ((sig)->pinvoke && ((sig)->call_convention == MONO_CALL_STDCALL || (sig)->call_convention == MONO_CALL_THISCALL))
72 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
74 #define OP_SEQ_POINT_BP_OFFSET 7
77 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
80 mono_arch_regname (int reg)
83 case X86_EAX: return "%eax";
84 case X86_EBX: return "%ebx";
85 case X86_ECX: return "%ecx";
86 case X86_EDX: return "%edx";
87 case X86_ESP: return "%esp";
88 case X86_EBP: return "%ebp";
89 case X86_EDI: return "%edi";
90 case X86_ESI: return "%esi";
96 mono_arch_fregname (int reg)
121 mono_arch_xregname (int reg)
146 mono_x86_patch (unsigned char* code, gpointer target)
148 x86_patch (code, (unsigned char*)target);
151 #define FLOAT_PARAM_REGS 0
153 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
155 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
160 switch (sig->call_convention) {
161 case MONO_CALL_THISCALL:
162 return thiscall_param_regs;
168 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
169 #define SMALL_STRUCTS_IN_REGS
170 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
174 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
176 ainfo->offset = *stack_size;
178 if (!param_regs || param_regs [*gr] == X86_NREG) {
179 ainfo->storage = ArgOnStack;
181 (*stack_size) += sizeof (gpointer);
184 ainfo->storage = ArgInIReg;
185 ainfo->reg = param_regs [*gr];
191 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
193 ainfo->offset = *stack_size;
195 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
197 ainfo->storage = ArgOnStack;
198 (*stack_size) += sizeof (gpointer) * 2;
203 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
205 ainfo->offset = *stack_size;
207 if (*gr >= FLOAT_PARAM_REGS) {
208 ainfo->storage = ArgOnStack;
209 (*stack_size) += is_double ? 8 : 4;
210 ainfo->nslots = is_double ? 2 : 1;
213 /* A double register */
215 ainfo->storage = ArgInDoubleSSEReg;
217 ainfo->storage = ArgInFloatSSEReg;
225 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
227 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
232 klass = mono_class_from_mono_type (type);
233 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
235 #if defined(TARGET_WIN32)
237 * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
238 * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
239 * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
240 * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
241 * it must be represented in call and cannot be dropped.
243 if (size == 0 && MONO_TYPE_ISSTRUCT (type) && sig->pinvoke) {
244 /* Empty structs (1 byte size) needs to be represented in a stack slot */
245 ainfo->pass_empty_struct = TRUE;
250 #ifdef SMALL_STRUCTS_IN_REGS
251 if (sig->pinvoke && is_return) {
252 MonoMarshalType *info;
254 info = mono_marshal_load_type_info (klass);
257 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
259 /* Ignore empty struct return value, if used. */
260 if (info->num_fields == 0 && ainfo->pass_empty_struct) {
261 ainfo->storage = ArgValuetypeInReg;
266 * Windows x86 ABI for returning structs of size 4 or 8 bytes (regardless of type) dictates that
267 * values are passed in EDX:EAX register pairs, https://msdn.microsoft.com/en-us/library/984x0h58.aspx.
268 * This is different compared to for example float or double return types (not in struct) that will be returned
269 * in ST(0), https://msdn.microsoft.com/en-us/library/ha59cbfz.aspx.
271 * Apples OSX x86 ABI for returning structs of size 4 or 8 bytes uses a slightly different approach.
272 * If a struct includes only one scalar value, it will be handled with the same rules as scalar values.
273 * This means that structs with one float or double will be returned in ST(0). For more details,
274 * https://developer.apple.com/library/mac/documentation/DeveloperTools/Conceptual/LowLevelABI/130-IA-32_Function_Calling_Conventions/IA32.html.
276 #if !defined(TARGET_WIN32)
278 /* Special case structs with only a float member */
279 if (info->num_fields == 1) {
280 int ftype = mini_get_underlying_type (info->fields [0].field->type)->type;
281 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
282 ainfo->storage = ArgValuetypeInReg;
283 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
286 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
287 ainfo->storage = ArgValuetypeInReg;
288 ainfo->pair_storage [0] = ArgOnFloatFpStack;
294 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
295 ainfo->storage = ArgValuetypeInReg;
296 ainfo->pair_storage [0] = ArgInIReg;
297 ainfo->pair_regs [0] = return_regs [0];
298 if (info->native_size > 4) {
299 ainfo->pair_storage [1] = ArgInIReg;
300 ainfo->pair_regs [1] = return_regs [1];
307 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
308 g_assert (size <= 4);
309 ainfo->storage = ArgValuetypeInReg;
310 ainfo->reg = param_regs [*gr];
315 ainfo->offset = *stack_size;
316 ainfo->storage = ArgOnStack;
317 *stack_size += ALIGN_TO (size, sizeof (gpointer));
318 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
324 * Obtain information about a call according to the calling convention.
325 * For x86 ELF, see the "System V Application Binary Interface Intel386
326 * Architecture Processor Supplment, Fourth Edition" document for more
328 * For x86 win32, see https://msdn.microsoft.com/en-us/library/984x0h58.aspx.
331 get_call_info_internal (CallInfo *cinfo, MonoMethodSignature *sig)
333 guint32 i, gr, fr, pstart;
334 const guint32 *param_regs;
336 int n = sig->hasthis + sig->param_count;
337 guint32 stack_size = 0;
338 gboolean is_pinvoke = sig->pinvoke;
344 param_regs = callconv_param_regs(sig);
348 ret_type = mini_get_underlying_type (sig->ret);
349 switch (ret_type->type) {
359 case MONO_TYPE_FNPTR:
360 case MONO_TYPE_OBJECT:
361 cinfo->ret.storage = ArgInIReg;
362 cinfo->ret.reg = X86_EAX;
366 cinfo->ret.storage = ArgInIReg;
367 cinfo->ret.reg = X86_EAX;
368 cinfo->ret.is_pair = TRUE;
371 cinfo->ret.storage = ArgOnFloatFpStack;
374 cinfo->ret.storage = ArgOnDoubleFpStack;
376 case MONO_TYPE_GENERICINST:
377 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
378 cinfo->ret.storage = ArgInIReg;
379 cinfo->ret.reg = X86_EAX;
382 if (mini_is_gsharedvt_type (ret_type)) {
383 cinfo->ret.storage = ArgOnStack;
384 cinfo->vtype_retaddr = TRUE;
388 case MONO_TYPE_VALUETYPE:
389 case MONO_TYPE_TYPEDBYREF: {
390 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
392 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
393 if (cinfo->ret.storage == ArgOnStack) {
394 cinfo->vtype_retaddr = TRUE;
395 /* The caller passes the address where the value is stored */
401 g_assert (mini_is_gsharedvt_type (ret_type));
402 cinfo->ret.storage = ArgOnStack;
403 cinfo->vtype_retaddr = TRUE;
406 cinfo->ret.storage = ArgNone;
409 g_error ("Can't handle as return value 0x%x", ret_type->type);
415 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
416 * the first argument, allowing 'this' to be always passed in the first arg reg.
417 * Also do this if the first argument is a reference type, since virtual calls
418 * are sometimes made using calli without sig->hasthis set, like in the delegate
421 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
423 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
425 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
428 cinfo->vret_arg_offset = stack_size;
429 add_general (&gr, NULL, &stack_size, &cinfo->ret);
430 cinfo->vret_arg_index = 1;
434 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
436 if (cinfo->vtype_retaddr)
437 add_general (&gr, NULL, &stack_size, &cinfo->ret);
440 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
441 fr = FLOAT_PARAM_REGS;
443 /* Emit the signature cookie just before the implicit arguments */
444 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
447 for (i = pstart; i < sig->param_count; ++i) {
448 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
451 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
452 /* We allways pass the sig cookie on the stack for simplicity */
454 * Prevent implicit arguments + the sig cookie from being passed
457 fr = FLOAT_PARAM_REGS;
459 /* Emit the signature cookie just before the implicit arguments */
460 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
463 if (sig->params [i]->byref) {
464 add_general (&gr, param_regs, &stack_size, ainfo);
467 ptype = mini_get_underlying_type (sig->params [i]);
468 switch (ptype->type) {
471 add_general (&gr, param_regs, &stack_size, ainfo);
475 add_general (&gr, param_regs, &stack_size, ainfo);
479 add_general (&gr, param_regs, &stack_size, ainfo);
484 case MONO_TYPE_FNPTR:
485 case MONO_TYPE_OBJECT:
486 add_general (&gr, param_regs, &stack_size, ainfo);
488 case MONO_TYPE_GENERICINST:
489 if (!mono_type_generic_inst_is_valuetype (ptype)) {
490 add_general (&gr, param_regs, &stack_size, ainfo);
493 if (mini_is_gsharedvt_type (ptype)) {
494 /* gsharedvt arguments are passed by ref */
495 add_general (&gr, param_regs, &stack_size, ainfo);
496 g_assert (ainfo->storage == ArgOnStack);
497 ainfo->storage = ArgGSharedVt;
501 case MONO_TYPE_VALUETYPE:
502 case MONO_TYPE_TYPEDBYREF:
503 add_valuetype (sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
507 add_general_pair (&gr, param_regs, &stack_size, ainfo);
510 add_float (&fr, &stack_size, ainfo, FALSE);
513 add_float (&fr, &stack_size, ainfo, TRUE);
517 /* gsharedvt arguments are passed by ref */
518 g_assert (mini_is_gsharedvt_type (ptype));
519 add_general (&gr, param_regs, &stack_size, ainfo);
520 g_assert (ainfo->storage == ArgOnStack);
521 ainfo->storage = ArgGSharedVt;
524 g_error ("unexpected type 0x%x", ptype->type);
525 g_assert_not_reached ();
529 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
530 fr = FLOAT_PARAM_REGS;
532 /* Emit the signature cookie just before the implicit arguments */
533 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
536 if (cinfo->vtype_retaddr) {
537 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
538 cinfo->callee_stack_pop = 4;
539 } else if (CALLCONV_IS_STDCALL (sig)) {
540 /* Have to compensate for the stack space popped by the native callee */
541 cinfo->callee_stack_pop = stack_size;
544 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
545 cinfo->need_stack_align = TRUE;
546 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
547 stack_size += cinfo->stack_align_amount;
550 cinfo->stack_usage = stack_size;
551 cinfo->reg_usage = gr;
552 cinfo->freg_usage = fr;
557 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
559 int n = sig->hasthis + sig->param_count;
563 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
565 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
567 return get_call_info_internal (cinfo, sig);
571 * mono_arch_get_argument_info:
572 * @csig: a method signature
573 * @param_count: the number of parameters to consider
574 * @arg_info: an array to store the result infos
576 * Gathers information on parameters such as size, alignment and
577 * padding. arg_info should be large enought to hold param_count + 1 entries.
579 * Returns the size of the argument area on the stack.
580 * This should be signal safe, since it is called from
581 * mono_arch_unwind_frame ().
582 * FIXME: The metadata calls might not be signal safe.
585 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
587 int len, k, args_size = 0;
593 /* Avoid g_malloc as it is not signal safe */
594 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
595 cinfo = (CallInfo*)g_newa (guint8*, len);
596 memset (cinfo, 0, len);
598 cinfo = get_call_info_internal (cinfo, csig);
600 arg_info [0].offset = offset;
602 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
603 args_size += sizeof (gpointer);
608 args_size += sizeof (gpointer);
612 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
613 /* Emitted after this */
614 args_size += sizeof (gpointer);
618 arg_info [0].size = args_size;
620 for (k = 0; k < param_count; k++) {
621 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
623 /* ignore alignment for now */
626 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
627 arg_info [k].pad = pad;
629 arg_info [k + 1].pad = 0;
630 arg_info [k + 1].size = size;
632 arg_info [k + 1].offset = offset;
635 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
636 /* Emitted after the first arg */
637 args_size += sizeof (gpointer);
642 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
643 align = MONO_ARCH_FRAME_ALIGNMENT;
646 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
647 arg_info [k].pad = pad;
653 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
655 MonoType *callee_ret;
659 if (cfg->compile_aot && !cfg->full_aot)
660 /* OP_TAILCALL doesn't work with AOT */
663 c1 = get_call_info (NULL, caller_sig);
664 c2 = get_call_info (NULL, callee_sig);
666 * Tail calls with more callee stack usage than the caller cannot be supported, since
667 * the extra stack space would be left on the stack after the tail call.
669 res = c1->stack_usage >= c2->stack_usage;
670 callee_ret = mini_get_underlying_type (callee_sig->ret);
671 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
672 /* An address on the callee's stack is passed as the first argument */
682 * Initialize the cpu to execute managed code.
685 mono_arch_cpu_init (void)
687 /* spec compliance requires running with double precision */
691 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
692 fpcw &= ~X86_FPCW_PRECC_MASK;
693 fpcw |= X86_FPCW_PREC_DOUBLE;
694 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
695 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
697 _control87 (_PC_53, MCW_PC);
702 * Initialize architecture specific code.
705 mono_arch_init (void)
707 mono_os_mutex_init_recursive (&mini_arch_mutex);
710 bp_trampoline = mini_get_breakpoint_trampoline ();
712 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
713 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
714 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
715 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
720 * Cleanup architecture specific code.
723 mono_arch_cleanup (void)
725 mono_os_mutex_destroy (&mini_arch_mutex);
729 * This function returns the optimizations supported on this cpu.
732 mono_arch_cpu_optimizations (guint32 *exclude_mask)
738 if (mono_hwcap_x86_has_cmov) {
739 opts |= MONO_OPT_CMOV;
741 if (mono_hwcap_x86_has_fcmov)
742 opts |= MONO_OPT_FCMOV;
744 *exclude_mask |= MONO_OPT_FCMOV;
746 *exclude_mask |= MONO_OPT_CMOV;
749 if (mono_hwcap_x86_has_sse2)
750 opts |= MONO_OPT_SSE2;
752 *exclude_mask |= MONO_OPT_SSE2;
754 #ifdef MONO_ARCH_SIMD_INTRINSICS
755 /*SIMD intrinsics require at least SSE2.*/
756 if (!mono_hwcap_x86_has_sse2)
757 *exclude_mask |= MONO_OPT_SIMD;
764 * This function test for all SSE functions supported.
766 * Returns a bitmask corresponding to all supported versions.
770 mono_arch_cpu_enumerate_simd_versions (void)
772 guint32 sse_opts = 0;
774 if (mono_hwcap_x86_has_sse1)
775 sse_opts |= SIMD_VERSION_SSE1;
777 if (mono_hwcap_x86_has_sse2)
778 sse_opts |= SIMD_VERSION_SSE2;
780 if (mono_hwcap_x86_has_sse3)
781 sse_opts |= SIMD_VERSION_SSE3;
783 if (mono_hwcap_x86_has_ssse3)
784 sse_opts |= SIMD_VERSION_SSSE3;
786 if (mono_hwcap_x86_has_sse41)
787 sse_opts |= SIMD_VERSION_SSE41;
789 if (mono_hwcap_x86_has_sse42)
790 sse_opts |= SIMD_VERSION_SSE42;
792 if (mono_hwcap_x86_has_sse4a)
793 sse_opts |= SIMD_VERSION_SSE4a;
799 * Determine whenever the trap whose info is in SIGINFO is caused by
803 mono_arch_is_int_overflow (void *sigctx, void *info)
808 mono_sigctx_to_monoctx (sigctx, &ctx);
810 ip = (guint8*)ctx.eip;
812 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
816 switch (x86_modrm_rm (ip [1])) {
836 g_assert_not_reached ();
848 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
853 for (i = 0; i < cfg->num_varinfo; i++) {
854 MonoInst *ins = cfg->varinfo [i];
855 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
858 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
861 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
862 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
865 /* we dont allocate I1 to registers because there is no simply way to sign extend
866 * 8bit quantities in caller saved registers on x86 */
867 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
868 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
869 g_assert (i == vmv->idx);
870 vars = g_list_prepend (vars, vmv);
874 vars = mono_varlist_sort (cfg, vars, 0);
880 mono_arch_get_global_int_regs (MonoCompile *cfg)
884 /* we can use 3 registers for global allocation */
885 regs = g_list_prepend (regs, (gpointer)X86_EBX);
886 regs = g_list_prepend (regs, (gpointer)X86_ESI);
887 regs = g_list_prepend (regs, (gpointer)X86_EDI);
893 * mono_arch_regalloc_cost:
895 * Return the cost, in number of memory references, of the action of
896 * allocating the variable VMV into a register during global register
900 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
902 MonoInst *ins = cfg->varinfo [vmv->idx];
904 if (cfg->method->save_lmf)
905 /* The register is already saved */
906 return (ins->opcode == OP_ARG) ? 1 : 0;
908 /* push+pop+possible load if it is an argument */
909 return (ins->opcode == OP_ARG) ? 3 : 2;
913 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
915 static int inited = FALSE;
916 static int count = 0;
918 if (cfg->arch.need_stack_frame_inited) {
919 g_assert (cfg->arch.need_stack_frame == flag);
923 cfg->arch.need_stack_frame = flag;
924 cfg->arch.need_stack_frame_inited = TRUE;
930 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
935 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
939 needs_stack_frame (MonoCompile *cfg)
941 MonoMethodSignature *sig;
942 MonoMethodHeader *header;
943 gboolean result = FALSE;
945 #if defined(__APPLE__)
946 /*OSX requires stack frame code to have the correct alignment. */
950 if (cfg->arch.need_stack_frame_inited)
951 return cfg->arch.need_stack_frame;
953 header = cfg->header;
954 sig = mono_method_signature (cfg->method);
956 if (cfg->disable_omit_fp)
958 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
960 else if (cfg->method->save_lmf)
962 else if (cfg->stack_offset)
964 else if (cfg->param_area)
966 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
968 else if (header->num_clauses)
970 else if (sig->param_count + sig->hasthis)
972 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
974 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)))
977 set_needs_stack_frame (cfg, result);
979 return cfg->arch.need_stack_frame;
983 * Set var information according to the calling convention. X86 version.
984 * The locals var stuff should most likely be split in another method.
987 mono_arch_allocate_vars (MonoCompile *cfg)
989 MonoMethodSignature *sig;
990 MonoMethodHeader *header;
992 guint32 locals_stack_size, locals_stack_align;
997 header = cfg->header;
998 sig = mono_method_signature (cfg->method);
1000 if (!cfg->arch.cinfo)
1001 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1002 cinfo = (CallInfo *)cfg->arch.cinfo;
1004 cfg->frame_reg = X86_EBP;
1007 if (cfg->has_atomic_add_i4 || cfg->has_atomic_exchange_i4) {
1008 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1009 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1012 /* Reserve space to save LMF and caller saved registers */
1014 if (cfg->method->save_lmf) {
1015 /* The LMF var is allocated normally */
1017 if (cfg->used_int_regs & (1 << X86_EBX)) {
1021 if (cfg->used_int_regs & (1 << X86_EDI)) {
1025 if (cfg->used_int_regs & (1 << X86_ESI)) {
1030 switch (cinfo->ret.storage) {
1031 case ArgValuetypeInReg:
1032 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1034 cfg->ret->opcode = OP_REGOFFSET;
1035 cfg->ret->inst_basereg = X86_EBP;
1036 cfg->ret->inst_offset = - offset;
1042 /* Allocate locals */
1043 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1044 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1045 char *mname = mono_method_full_name (cfg->method, TRUE);
1046 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1050 if (locals_stack_align) {
1051 int prev_offset = offset;
1053 offset += (locals_stack_align - 1);
1054 offset &= ~(locals_stack_align - 1);
1056 while (prev_offset < offset) {
1058 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1061 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1062 cfg->locals_max_stack_offset = - offset;
1064 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1065 * have locals larger than 8 bytes we need to make sure that
1066 * they have the appropriate offset.
1068 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8) {
1069 int extra_size = MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1070 offset += extra_size;
1071 locals_stack_size += extra_size;
1073 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1074 if (offsets [i] != -1) {
1075 MonoInst *inst = cfg->varinfo [i];
1076 inst->opcode = OP_REGOFFSET;
1077 inst->inst_basereg = X86_EBP;
1078 inst->inst_offset = - (offset + offsets [i]);
1079 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1082 offset += locals_stack_size;
1086 * Allocate arguments+return value
1089 switch (cinfo->ret.storage) {
1091 if (cfg->vret_addr) {
1093 * In the new IR, the cfg->vret_addr variable represents the
1094 * vtype return value.
1096 cfg->vret_addr->opcode = OP_REGOFFSET;
1097 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1098 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1099 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1100 printf ("vret_addr =");
1101 mono_print_ins (cfg->vret_addr);
1104 cfg->ret->opcode = OP_REGOFFSET;
1105 cfg->ret->inst_basereg = X86_EBP;
1106 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1109 case ArgValuetypeInReg:
1112 cfg->ret->opcode = OP_REGVAR;
1113 cfg->ret->inst_c0 = cinfo->ret.reg;
1114 cfg->ret->dreg = cinfo->ret.reg;
1117 case ArgOnFloatFpStack:
1118 case ArgOnDoubleFpStack:
1121 g_assert_not_reached ();
1124 if (sig->call_convention == MONO_CALL_VARARG) {
1125 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1126 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1129 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1130 ArgInfo *ainfo = &cinfo->args [i];
1131 inst = cfg->args [i];
1132 if (inst->opcode != OP_REGVAR) {
1133 inst->opcode = OP_REGOFFSET;
1134 inst->inst_basereg = X86_EBP;
1135 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1139 cfg->stack_offset = offset;
1143 mono_arch_create_vars (MonoCompile *cfg)
1146 MonoMethodSignature *sig;
1149 sig = mono_method_signature (cfg->method);
1151 if (!cfg->arch.cinfo)
1152 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1153 cinfo = (CallInfo *)cfg->arch.cinfo;
1155 sig_ret = mini_get_underlying_type (sig->ret);
1157 if (cinfo->ret.storage == ArgValuetypeInReg)
1158 cfg->ret_var_is_local = TRUE;
1159 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (sig_ret))) {
1160 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1163 if (cfg->gen_sdb_seq_points) {
1166 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1167 ins->flags |= MONO_INST_VOLATILE;
1168 cfg->arch.ss_tramp_var = ins;
1170 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1171 ins->flags |= MONO_INST_VOLATILE;
1172 cfg->arch.bp_tramp_var = ins;
1175 if (cfg->method->save_lmf) {
1176 cfg->create_lmf_var = TRUE;
1180 cfg->arch_eh_jit_info = 1;
1184 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1185 * so we try to do it just once when we have multiple fp arguments in a row.
1186 * We don't use this mechanism generally because for int arguments the generated code
1187 * is slightly bigger and new generation cpus optimize away the dependency chains
1188 * created by push instructions on the esp value.
1189 * fp_arg_setup is the first argument in the execution sequence where the esp register
1192 static G_GNUC_UNUSED int
1193 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1198 for (; start_arg < sig->param_count; ++start_arg) {
1199 t = mini_get_underlying_type (sig->params [start_arg]);
1200 if (!t->byref && t->type == MONO_TYPE_R8) {
1201 fp_space += sizeof (double);
1202 *fp_arg_setup = start_arg;
1211 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1213 MonoMethodSignature *tmp_sig;
1217 * mono_ArgIterator_Setup assumes the signature cookie is
1218 * passed first and all the arguments which were before it are
1219 * passed on the stack after the signature. So compensate by
1220 * passing a different signature.
1222 tmp_sig = mono_metadata_signature_dup (call->signature);
1223 tmp_sig->param_count -= call->signature->sentinelpos;
1224 tmp_sig->sentinelpos = 0;
1225 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1227 if (cfg->compile_aot) {
1228 sig_reg = mono_alloc_ireg (cfg);
1229 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1230 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->sig_cookie.offset, sig_reg);
1232 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg, OP_STORE_MEMBASE_IMM, X86_ESP, cinfo->sig_cookie.offset, tmp_sig);
1238 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1243 LLVMCallInfo *linfo;
1244 MonoType *t, *sig_ret;
1246 n = sig->param_count + sig->hasthis;
1248 cinfo = get_call_info (cfg->mempool, sig);
1251 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1254 * LLVM always uses the native ABI while we use our own ABI, the
1255 * only difference is the handling of vtypes:
1256 * - we only pass/receive them in registers in some cases, and only
1257 * in 1 or 2 integer registers.
1259 if (cinfo->ret.storage == ArgValuetypeInReg) {
1261 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1262 cfg->disable_llvm = TRUE;
1266 cfg->exception_message = g_strdup ("vtype ret in call");
1267 cfg->disable_llvm = TRUE;
1269 linfo->ret.storage = LLVMArgVtypeInReg;
1270 for (j = 0; j < 2; ++j)
1271 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1275 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage == ArgInIReg) {
1276 /* Vtype returned using a hidden argument */
1277 linfo->ret.storage = LLVMArgVtypeRetAddr;
1278 linfo->vret_arg_index = cinfo->vret_arg_index;
1281 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage != ArgInIReg) {
1283 cfg->exception_message = g_strdup ("vtype ret in call");
1284 cfg->disable_llvm = TRUE;
1287 for (i = 0; i < n; ++i) {
1288 ainfo = cinfo->args + i;
1290 if (i >= sig->hasthis)
1291 t = sig->params [i - sig->hasthis];
1293 t = &mono_defaults.int_class->byval_arg;
1295 linfo->args [i].storage = LLVMArgNone;
1297 switch (ainfo->storage) {
1299 linfo->args [i].storage = LLVMArgNormal;
1301 case ArgInDoubleSSEReg:
1302 case ArgInFloatSSEReg:
1303 linfo->args [i].storage = LLVMArgNormal;
1306 if (mini_type_is_vtype (t)) {
1307 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1308 /* LLVM seems to allocate argument space for empty structures too */
1309 linfo->args [i].storage = LLVMArgNone;
1311 linfo->args [i].storage = LLVMArgVtypeByVal;
1313 linfo->args [i].storage = LLVMArgNormal;
1316 case ArgValuetypeInReg:
1318 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1319 cfg->disable_llvm = TRUE;
1323 cfg->exception_message = g_strdup ("vtype arg");
1324 cfg->disable_llvm = TRUE;
1326 linfo->args [i].storage = LLVMArgVtypeInReg;
1327 for (j = 0; j < 2; ++j)
1328 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1332 linfo->args [i].storage = LLVMArgGSharedVt;
1335 cfg->exception_message = g_strdup ("ainfo->storage");
1336 cfg->disable_llvm = TRUE;
1346 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1348 if (cfg->compute_gc_maps) {
1351 /* Needs checking if the feature will be enabled again */
1352 g_assert_not_reached ();
1354 /* On x86, the offsets are from the sp value before the start of the call sequence */
1356 t = &mono_defaults.int_class->byval_arg;
1357 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1362 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1366 MonoMethodSignature *sig;
1369 int sentinelpos = 0, sp_offset = 0;
1371 sig = call->signature;
1372 n = sig->param_count + sig->hasthis;
1373 sig_ret = mini_get_underlying_type (sig->ret);
1375 cinfo = get_call_info (cfg->mempool, sig);
1376 call->call_info = cinfo;
1378 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1379 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1381 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1382 if (cinfo->ret.storage == ArgValuetypeInReg && cinfo->ret.pair_storage[0] != ArgNone ) {
1384 * Tell the JIT to use a more efficient calling convention: call using
1385 * OP_CALL, compute the result location after the call, and save the
1388 call->vret_in_reg = TRUE;
1389 #if defined(__APPLE__)
1390 if (cinfo->ret.pair_storage [0] == ArgOnDoubleFpStack || cinfo->ret.pair_storage [0] == ArgOnFloatFpStack)
1391 call->vret_in_reg_fp = TRUE;
1394 NULLIFY_INS (call->vret_var);
1398 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1400 /* Handle the case where there are no implicit arguments */
1401 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1402 emit_sig_cookie (cfg, call, cinfo);
1403 sp_offset = cinfo->sig_cookie.offset;
1404 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1407 /* Arguments are pushed in the reverse order */
1408 for (i = n - 1; i >= 0; i --) {
1409 ArgInfo *ainfo = cinfo->args + i;
1410 MonoType *orig_type, *t;
1413 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1416 /* Push the vret arg before the first argument */
1417 MONO_INST_NEW (cfg, vtarg, OP_STORE_MEMBASE_REG);
1418 vtarg->type = STACK_MP;
1419 vtarg->inst_destbasereg = X86_ESP;
1420 vtarg->sreg1 = call->vret_var->dreg;
1421 vtarg->inst_offset = cinfo->ret.offset;
1422 MONO_ADD_INS (cfg->cbb, vtarg);
1423 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1426 if (i >= sig->hasthis)
1427 t = sig->params [i - sig->hasthis];
1429 t = &mono_defaults.int_class->byval_arg;
1431 t = mini_get_underlying_type (t);
1433 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1435 in = call->args [i];
1436 arg->cil_code = in->cil_code;
1437 arg->sreg1 = in->dreg;
1438 arg->type = in->type;
1440 g_assert (in->dreg != -1);
1442 if (ainfo->storage == ArgGSharedVt) {
1443 arg->opcode = OP_OUTARG_VT;
1444 arg->sreg1 = in->dreg;
1445 arg->klass = in->klass;
1446 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1447 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1449 MONO_ADD_INS (cfg->cbb, arg);
1450 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1454 g_assert (in->klass);
1456 if (t->type == MONO_TYPE_TYPEDBYREF) {
1457 size = sizeof (MonoTypedRef);
1458 align = sizeof (gpointer);
1461 size = mini_type_stack_size_full (&in->klass->byval_arg, &align, sig->pinvoke);
1464 if (size > 0 || ainfo->pass_empty_struct) {
1465 arg->opcode = OP_OUTARG_VT;
1466 arg->sreg1 = in->dreg;
1467 arg->klass = in->klass;
1468 arg->backend.size = size;
1469 arg->inst_p0 = call;
1470 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1471 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1473 MONO_ADD_INS (cfg->cbb, arg);
1474 if (ainfo->storage != ArgValuetypeInReg) {
1475 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1479 switch (ainfo->storage) {
1482 if (t->type == MONO_TYPE_R4) {
1483 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1485 } else if (t->type == MONO_TYPE_R8) {
1486 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1488 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1489 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset + 4, MONO_LVREG_MS (in->dreg));
1490 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, MONO_LVREG_LS (in->dreg));
1493 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1497 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1502 arg->opcode = OP_MOVE;
1503 arg->dreg = ainfo->reg;
1504 MONO_ADD_INS (cfg->cbb, arg);
1508 g_assert_not_reached ();
1511 if (cfg->compute_gc_maps) {
1513 /* FIXME: The == STACK_OBJ check might be fragile ? */
1514 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1516 if (call->need_unbox_trampoline)
1517 /* The unbox trampoline transforms this into a managed pointer */
1518 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.int_class->this_arg);
1520 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.object_class->byval_arg);
1522 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1526 for (j = 0; j < argsize; j += 4)
1527 emit_gc_param_slot_def (cfg, ainfo->offset + j, NULL);
1532 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1533 /* Emit the signature cookie just before the implicit arguments */
1534 emit_sig_cookie (cfg, call, cinfo);
1535 emit_gc_param_slot_def (cfg, cinfo->sig_cookie.offset, NULL);
1539 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1542 if (cinfo->ret.storage == ArgValuetypeInReg) {
1545 else if (cinfo->ret.storage == ArgInIReg) {
1547 /* The return address is passed in a register */
1548 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1549 vtarg->sreg1 = call->inst.dreg;
1550 vtarg->dreg = mono_alloc_ireg (cfg);
1551 MONO_ADD_INS (cfg->cbb, vtarg);
1553 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1554 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1555 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->ret.offset, call->vret_var->dreg);
1556 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1560 call->stack_usage = cinfo->stack_usage;
1561 call->stack_align_amount = cinfo->stack_align_amount;
1565 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1567 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1568 ArgInfo *ainfo = ins->inst_p1;
1569 int size = ins->backend.size;
1571 if (ainfo->storage == ArgValuetypeInReg) {
1572 int dreg = mono_alloc_ireg (cfg);
1575 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1578 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1581 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1585 g_assert_not_reached ();
1587 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1590 if (cfg->gsharedvt && mini_is_gsharedvt_klass (ins->klass)) {
1592 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, src->dreg);
1593 } else if (size <= 4) {
1594 int dreg = mono_alloc_ireg (cfg);
1595 if (ainfo->pass_empty_struct) {
1596 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
1597 MONO_EMIT_NEW_ICONST (cfg, dreg, 0);
1599 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1601 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, dreg);
1602 } else if (size <= 20) {
1603 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1605 // FIXME: Code growth
1606 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1612 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1614 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
1617 if (ret->type == MONO_TYPE_R4) {
1618 if (COMPILE_LLVM (cfg))
1619 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1622 } else if (ret->type == MONO_TYPE_R8) {
1623 if (COMPILE_LLVM (cfg))
1624 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1627 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1628 if (COMPILE_LLVM (cfg))
1629 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1631 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, MONO_LVREG_LS (val->dreg));
1632 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, MONO_LVREG_MS (val->dreg));
1638 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1642 * Allow tracing to work with this interface (with an optional argument)
1645 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1649 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1650 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1652 /* if some args are passed in registers, we need to save them here */
1653 x86_push_reg (code, X86_EBP);
1655 if (cfg->compile_aot) {
1656 x86_push_imm (code, cfg->method);
1657 x86_mov_reg_imm (code, X86_EAX, func);
1658 x86_call_reg (code, X86_EAX);
1660 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1661 x86_push_imm (code, cfg->method);
1662 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1663 x86_call_code (code, 0);
1665 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1679 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1682 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1683 MonoMethod *method = cfg->method;
1684 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
1686 switch (ret_type->type) {
1687 case MONO_TYPE_VOID:
1688 /* special case string .ctor icall */
1689 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1690 save_mode = SAVE_EAX;
1691 stack_usage = enable_arguments ? 8 : 4;
1693 save_mode = SAVE_NONE;
1697 save_mode = SAVE_EAX_EDX;
1698 stack_usage = enable_arguments ? 16 : 8;
1702 save_mode = SAVE_FP;
1703 stack_usage = enable_arguments ? 16 : 8;
1705 case MONO_TYPE_GENERICINST:
1706 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1707 save_mode = SAVE_EAX;
1708 stack_usage = enable_arguments ? 8 : 4;
1712 case MONO_TYPE_VALUETYPE:
1713 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1714 save_mode = SAVE_STRUCT;
1715 stack_usage = enable_arguments ? 4 : 0;
1718 save_mode = SAVE_EAX;
1719 stack_usage = enable_arguments ? 8 : 4;
1723 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1725 switch (save_mode) {
1727 x86_push_reg (code, X86_EDX);
1728 x86_push_reg (code, X86_EAX);
1729 if (enable_arguments) {
1730 x86_push_reg (code, X86_EDX);
1731 x86_push_reg (code, X86_EAX);
1736 x86_push_reg (code, X86_EAX);
1737 if (enable_arguments) {
1738 x86_push_reg (code, X86_EAX);
1743 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1744 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1745 if (enable_arguments) {
1746 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1747 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1752 if (enable_arguments) {
1753 x86_push_membase (code, X86_EBP, 8);
1762 if (cfg->compile_aot) {
1763 x86_push_imm (code, method);
1764 x86_mov_reg_imm (code, X86_EAX, func);
1765 x86_call_reg (code, X86_EAX);
1767 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1768 x86_push_imm (code, method);
1769 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1770 x86_call_code (code, 0);
1773 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1775 switch (save_mode) {
1777 x86_pop_reg (code, X86_EAX);
1778 x86_pop_reg (code, X86_EDX);
1781 x86_pop_reg (code, X86_EAX);
1784 x86_fld_membase (code, X86_ESP, 0, TRUE);
1785 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1792 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1797 #define EMIT_COND_BRANCH(ins,cond,sign) \
1798 if (ins->inst_true_bb->native_offset) { \
1799 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1801 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1802 if ((cfg->opt & MONO_OPT_BRANCH) && \
1803 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1804 x86_branch8 (code, cond, 0, sign); \
1806 x86_branch32 (code, cond, 0, sign); \
1810 * Emit an exception if condition is fail and
1811 * if possible do a directly branch to target
1813 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1815 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1816 if (tins == NULL) { \
1817 mono_add_patch_info (cfg, code - cfg->native_code, \
1818 MONO_PATCH_INFO_EXC, exc_name); \
1819 x86_branch32 (code, cond, 0, signed); \
1821 EMIT_COND_BRANCH (tins, cond, signed); \
1825 #define EMIT_FPCOMPARE(code) do { \
1826 x86_fcompp (code); \
1827 x86_fnstsw (code); \
1832 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1834 gboolean needs_paddings = TRUE;
1836 MonoJumpInfo *jinfo = NULL;
1838 if (cfg->abs_patches) {
1839 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1840 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1841 needs_paddings = FALSE;
1844 if (cfg->compile_aot)
1845 needs_paddings = FALSE;
1846 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1847 This is required for code patching to be safe on SMP machines.
1849 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1850 if (needs_paddings && pad_size)
1851 x86_padding (code, 4 - pad_size);
1853 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1854 x86_call_code (code, 0);
1859 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1862 * mono_peephole_pass_1:
1864 * Perform peephole opts which should/can be performed before local regalloc
1867 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1871 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1872 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
1874 switch (ins->opcode) {
1877 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1879 * X86_LEA is like ADD, but doesn't have the
1880 * sreg1==dreg restriction.
1882 ins->opcode = OP_X86_LEA_MEMBASE;
1883 ins->inst_basereg = ins->sreg1;
1884 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1885 ins->opcode = OP_X86_INC_REG;
1889 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1890 ins->opcode = OP_X86_LEA_MEMBASE;
1891 ins->inst_basereg = ins->sreg1;
1892 ins->inst_imm = -ins->inst_imm;
1893 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1894 ins->opcode = OP_X86_DEC_REG;
1896 case OP_COMPARE_IMM:
1897 case OP_ICOMPARE_IMM:
1898 /* OP_COMPARE_IMM (reg, 0)
1900 * OP_X86_TEST_NULL (reg)
1903 ins->opcode = OP_X86_TEST_NULL;
1905 case OP_X86_COMPARE_MEMBASE_IMM:
1907 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1908 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1910 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1911 * OP_COMPARE_IMM reg, imm
1913 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1915 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1916 ins->inst_basereg == last_ins->inst_destbasereg &&
1917 ins->inst_offset == last_ins->inst_offset) {
1918 ins->opcode = OP_COMPARE_IMM;
1919 ins->sreg1 = last_ins->sreg1;
1921 /* check if we can remove cmp reg,0 with test null */
1923 ins->opcode = OP_X86_TEST_NULL;
1927 case OP_X86_PUSH_MEMBASE:
1928 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1929 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1930 ins->inst_basereg == last_ins->inst_destbasereg &&
1931 ins->inst_offset == last_ins->inst_offset) {
1932 ins->opcode = OP_X86_PUSH;
1933 ins->sreg1 = last_ins->sreg1;
1938 mono_peephole_ins (bb, ins);
1943 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1947 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1948 switch (ins->opcode) {
1950 /* reg = 0 -> XOR (reg, reg) */
1951 /* XOR sets cflags on x86, so we cant do it always */
1952 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
1955 ins->opcode = OP_IXOR;
1956 ins->sreg1 = ins->dreg;
1957 ins->sreg2 = ins->dreg;
1960 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
1961 * since it takes 3 bytes instead of 7.
1963 for (ins2 = mono_inst_next (ins, FILTER_IL_SEQ_POINT); ins2; ins2 = ins2->next) {
1964 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1965 ins2->opcode = OP_STORE_MEMBASE_REG;
1966 ins2->sreg1 = ins->dreg;
1968 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1969 ins2->opcode = OP_STOREI4_MEMBASE_REG;
1970 ins2->sreg1 = ins->dreg;
1972 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
1973 /* Continue iteration */
1982 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1983 ins->opcode = OP_X86_INC_REG;
1987 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1988 ins->opcode = OP_X86_DEC_REG;
1992 mono_peephole_ins (bb, ins);
1996 #define NEW_INS(cfg,ins,dest,op) do { \
1997 MONO_INST_NEW ((cfg), (dest), (op)); \
1998 (dest)->cil_code = (ins)->cil_code; \
1999 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2003 * mono_arch_lowering_pass:
2005 * Converts complex opcodes into simpler ones so that each IR instruction
2006 * corresponds to one machine instruction.
2009 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2011 MonoInst *ins, *next;
2014 * FIXME: Need to add more instructions, but the current machine
2015 * description can't model some parts of the composite instructions like
2018 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2019 switch (ins->opcode) {
2022 case OP_IDIV_UN_IMM:
2023 case OP_IREM_UN_IMM:
2025 * Keep the cases where we could generated optimized code, otherwise convert
2026 * to the non-imm variant.
2028 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2030 mono_decompose_op_imm (cfg, bb, ins);
2032 #ifdef MONO_ARCH_SIMD_INTRINSICS
2033 case OP_EXPAND_I1: {
2035 int temp_reg1 = mono_alloc_ireg (cfg);
2036 int temp_reg2 = mono_alloc_ireg (cfg);
2037 int original_reg = ins->sreg1;
2039 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
2040 temp->sreg1 = original_reg;
2041 temp->dreg = temp_reg1;
2043 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
2044 temp->sreg1 = temp_reg1;
2045 temp->dreg = temp_reg2;
2048 NEW_INS (cfg, ins, temp, OP_IOR);
2049 temp->sreg1 = temp->dreg = temp_reg2;
2050 temp->sreg2 = temp_reg1;
2052 ins->opcode = OP_EXPAND_I2;
2053 ins->sreg1 = temp_reg2;
2062 bb->max_vreg = cfg->next_vreg;
2066 branch_cc_table [] = {
2067 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2068 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2069 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2072 /* Maps CMP_... constants to X86_CC_... constants */
2075 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2076 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2080 cc_signed_table [] = {
2081 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2082 FALSE, FALSE, FALSE, FALSE
2085 static unsigned char*
2086 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2088 #define XMM_TEMP_REG 0
2089 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2090 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2091 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2092 /* optimize by assigning a local var for this use so we avoid
2093 * the stack manipulations */
2094 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2095 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2096 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2097 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2098 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2100 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2102 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2105 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2106 x86_fnstcw_membase(code, X86_ESP, 0);
2107 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2108 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2109 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2110 x86_fldcw_membase (code, X86_ESP, 2);
2112 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2113 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2114 x86_pop_reg (code, dreg);
2115 /* FIXME: need the high register
2116 * x86_pop_reg (code, dreg_high);
2119 x86_push_reg (code, X86_EAX); // SP = SP - 4
2120 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2121 x86_pop_reg (code, dreg);
2123 x86_fldcw_membase (code, X86_ESP, 0);
2124 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2127 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2129 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2133 static unsigned char*
2134 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2136 int sreg = tree->sreg1;
2137 int need_touch = FALSE;
2139 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2148 * If requested stack size is larger than one page,
2149 * perform stack-touch operation
2152 * Generate stack probe code.
2153 * Under Windows, it is necessary to allocate one page at a time,
2154 * "touching" stack after each successful sub-allocation. This is
2155 * because of the way stack growth is implemented - there is a
2156 * guard page before the lowest stack page that is currently commited.
2157 * Stack normally grows sequentially so OS traps access to the
2158 * guard page and commits more pages when needed.
2160 x86_test_reg_imm (code, sreg, ~0xFFF);
2161 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2163 br[2] = code; /* loop */
2164 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2165 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2168 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2169 * that follows only initializes the last part of the area.
2171 /* Same as the init code below with size==0x1000 */
2172 if (tree->flags & MONO_INST_INIT) {
2173 x86_push_reg (code, X86_EAX);
2174 x86_push_reg (code, X86_ECX);
2175 x86_push_reg (code, X86_EDI);
2176 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2177 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2178 if (cfg->param_area)
2179 x86_lea_membase (code, X86_EDI, X86_ESP, 12 + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2181 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2183 x86_prefix (code, X86_REP_PREFIX);
2185 x86_pop_reg (code, X86_EDI);
2186 x86_pop_reg (code, X86_ECX);
2187 x86_pop_reg (code, X86_EAX);
2190 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2191 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2192 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2193 x86_patch (br[3], br[2]);
2194 x86_test_reg_reg (code, sreg, sreg);
2195 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2196 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2198 br[1] = code; x86_jump8 (code, 0);
2200 x86_patch (br[0], code);
2201 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2202 x86_patch (br[1], code);
2203 x86_patch (br[4], code);
2206 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2208 if (tree->flags & MONO_INST_INIT) {
2210 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2211 x86_push_reg (code, X86_EAX);
2214 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2215 x86_push_reg (code, X86_ECX);
2218 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2219 x86_push_reg (code, X86_EDI);
2223 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2224 if (sreg != X86_ECX)
2225 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2226 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2228 if (cfg->param_area)
2229 x86_lea_membase (code, X86_EDI, X86_ESP, offset + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2231 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2233 x86_prefix (code, X86_REP_PREFIX);
2236 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2237 x86_pop_reg (code, X86_EDI);
2238 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2239 x86_pop_reg (code, X86_ECX);
2240 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2241 x86_pop_reg (code, X86_EAX);
2248 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2250 /* Move return value to the target register */
2251 switch (ins->opcode) {
2254 case OP_CALL_MEMBASE:
2255 if (ins->dreg != X86_EAX)
2256 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2266 static int tls_gs_offset;
2270 mono_arch_have_fast_tls (void)
2273 static gboolean have_fast_tls = FALSE;
2274 static gboolean inited = FALSE;
2277 if (mini_get_debug_options ()->use_fallback_tls)
2280 return have_fast_tls;
2282 ins = (guint32*)pthread_getspecific;
2284 * We're looking for these two instructions:
2286 * mov 0x4(%esp),%eax
2287 * mov %gs:[offset](,%eax,4),%eax
2289 have_fast_tls = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2290 tls_gs_offset = ins [2];
2293 return have_fast_tls;
2294 #elif defined(TARGET_ANDROID)
2297 if (mini_get_debug_options ()->use_fallback_tls)
2304 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2306 #if defined(TARGET_MACH)
2307 x86_prefix (code, X86_GS_PREFIX);
2308 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2309 #elif defined(TARGET_WIN32)
2311 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2312 * Journal and/or a disassembly of the TlsGet () function.
2314 x86_prefix (code, X86_FS_PREFIX);
2315 x86_mov_reg_mem (code, dreg, 0x18, 4);
2316 if (tls_offset < 64) {
2317 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2321 g_assert (tls_offset < 0x440);
2322 /* Load TEB->TlsExpansionSlots */
2323 x86_mov_reg_membase (code, dreg, dreg, 0xf94, 4);
2324 x86_test_reg_reg (code, dreg, dreg);
2326 x86_branch (code, X86_CC_EQ, code, TRUE);
2327 x86_mov_reg_membase (code, dreg, dreg, (tls_offset * 4) - 0x100, 4);
2328 x86_patch (buf [0], code);
2331 if (optimize_for_xen) {
2332 x86_prefix (code, X86_GS_PREFIX);
2333 x86_mov_reg_mem (code, dreg, 0, 4);
2334 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2336 x86_prefix (code, X86_GS_PREFIX);
2337 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2344 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2346 #if defined(TARGET_MACH)
2347 x86_prefix (code, X86_GS_PREFIX);
2348 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2349 #elif defined(TARGET_WIN32)
2350 g_assert_not_reached ();
2352 x86_prefix (code, X86_GS_PREFIX);
2353 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2361 * Emit code to initialize an LMF structure at LMF_OFFSET.
2364 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2366 /* save all caller saved regs */
2367 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2368 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx));
2369 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2370 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi));
2371 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2372 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi));
2373 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2375 /* save the current IP */
2376 if (cfg->compile_aot) {
2377 /* This pushes the current ip */
2378 x86_call_imm (code, 0);
2379 x86_pop_reg (code, X86_EAX);
2381 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2382 x86_mov_reg_imm (code, X86_EAX, 0);
2384 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2386 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2387 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2388 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2389 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2390 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2391 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2392 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2393 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2394 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2399 /* benchmark and set based on cpu */
2400 #define LOOP_ALIGNMENT 8
2401 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2405 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2410 guint8 *code = cfg->native_code + cfg->code_len;
2413 if (cfg->opt & MONO_OPT_LOOP) {
2414 int pad, align = LOOP_ALIGNMENT;
2415 /* set alignment depending on cpu */
2416 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2418 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2419 x86_padding (code, pad);
2420 cfg->code_len += pad;
2421 bb->native_offset = cfg->code_len;
2425 if (cfg->verbose_level > 2)
2426 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2428 cpos = bb->max_offset;
2430 offset = code - cfg->native_code;
2432 mono_debug_open_block (cfg, bb, offset);
2434 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2435 x86_breakpoint (code);
2437 MONO_BB_FOR_EACH_INS (bb, ins) {
2438 offset = code - cfg->native_code;
2440 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2442 #define EXTRA_CODE_SPACE (16)
2444 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2445 cfg->code_size *= 2;
2446 cfg->native_code = mono_realloc_native_code(cfg);
2447 code = cfg->native_code + offset;
2448 cfg->stat_code_reallocs++;
2451 if (cfg->debug_info)
2452 mono_debug_record_line_number (cfg, ins, offset);
2454 switch (ins->opcode) {
2456 x86_mul_reg (code, ins->sreg2, TRUE);
2459 x86_mul_reg (code, ins->sreg2, FALSE);
2461 case OP_X86_SETEQ_MEMBASE:
2462 case OP_X86_SETNE_MEMBASE:
2463 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2464 ins->inst_basereg, ins->inst_offset, TRUE);
2466 case OP_STOREI1_MEMBASE_IMM:
2467 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2469 case OP_STOREI2_MEMBASE_IMM:
2470 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2472 case OP_STORE_MEMBASE_IMM:
2473 case OP_STOREI4_MEMBASE_IMM:
2474 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2476 case OP_STOREI1_MEMBASE_REG:
2477 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2479 case OP_STOREI2_MEMBASE_REG:
2480 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2482 case OP_STORE_MEMBASE_REG:
2483 case OP_STOREI4_MEMBASE_REG:
2484 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2486 case OP_STORE_MEM_IMM:
2487 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2490 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2494 /* These are created by the cprop pass so they use inst_imm as the source */
2495 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2498 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2501 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2503 case OP_LOAD_MEMBASE:
2504 case OP_LOADI4_MEMBASE:
2505 case OP_LOADU4_MEMBASE:
2506 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2508 case OP_LOADU1_MEMBASE:
2509 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2511 case OP_LOADI1_MEMBASE:
2512 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2514 case OP_LOADU2_MEMBASE:
2515 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2517 case OP_LOADI2_MEMBASE:
2518 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2520 case OP_ICONV_TO_I1:
2522 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2524 case OP_ICONV_TO_I2:
2526 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2528 case OP_ICONV_TO_U1:
2529 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2531 case OP_ICONV_TO_U2:
2532 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2536 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2538 case OP_COMPARE_IMM:
2539 case OP_ICOMPARE_IMM:
2540 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2542 case OP_X86_COMPARE_MEMBASE_REG:
2543 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2545 case OP_X86_COMPARE_MEMBASE_IMM:
2546 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2548 case OP_X86_COMPARE_MEMBASE8_IMM:
2549 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2551 case OP_X86_COMPARE_REG_MEMBASE:
2552 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2554 case OP_X86_COMPARE_MEM_IMM:
2555 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2557 case OP_X86_TEST_NULL:
2558 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2560 case OP_X86_ADD_MEMBASE_IMM:
2561 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2563 case OP_X86_ADD_REG_MEMBASE:
2564 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2566 case OP_X86_SUB_MEMBASE_IMM:
2567 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2569 case OP_X86_SUB_REG_MEMBASE:
2570 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2572 case OP_X86_AND_MEMBASE_IMM:
2573 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2575 case OP_X86_OR_MEMBASE_IMM:
2576 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2578 case OP_X86_XOR_MEMBASE_IMM:
2579 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2581 case OP_X86_ADD_MEMBASE_REG:
2582 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2584 case OP_X86_SUB_MEMBASE_REG:
2585 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2587 case OP_X86_AND_MEMBASE_REG:
2588 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2590 case OP_X86_OR_MEMBASE_REG:
2591 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2593 case OP_X86_XOR_MEMBASE_REG:
2594 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2596 case OP_X86_INC_MEMBASE:
2597 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2599 case OP_X86_INC_REG:
2600 x86_inc_reg (code, ins->dreg);
2602 case OP_X86_DEC_MEMBASE:
2603 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2605 case OP_X86_DEC_REG:
2606 x86_dec_reg (code, ins->dreg);
2608 case OP_X86_MUL_REG_MEMBASE:
2609 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2611 case OP_X86_AND_REG_MEMBASE:
2612 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2614 case OP_X86_OR_REG_MEMBASE:
2615 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2617 case OP_X86_XOR_REG_MEMBASE:
2618 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2621 x86_breakpoint (code);
2623 case OP_RELAXED_NOP:
2624 x86_prefix (code, X86_REP_PREFIX);
2632 case OP_DUMMY_STORE:
2633 case OP_DUMMY_ICONST:
2634 case OP_DUMMY_R8CONST:
2635 case OP_NOT_REACHED:
2638 case OP_IL_SEQ_POINT:
2639 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2641 case OP_SEQ_POINT: {
2644 if (cfg->compile_aot)
2647 /* Have to use ecx as a temp reg since this can occur after OP_SETRET */
2650 * We do this _before_ the breakpoint, so single stepping after
2651 * a breakpoint is hit will step to the next IL offset.
2653 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
2654 MonoInst *var = cfg->arch.ss_tramp_var;
2658 g_assert (var->opcode == OP_REGOFFSET);
2659 /* Load ss_tramp_var */
2660 /* This is equal to &ss_trampoline */
2661 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, sizeof (mgreg_t));
2662 x86_mov_reg_membase (code, X86_ECX, X86_ECX, 0, sizeof (mgreg_t));
2663 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
2664 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2665 x86_call_reg (code, X86_ECX);
2666 x86_patch (br [0], code);
2670 * Many parts of sdb depend on the ip after the single step trampoline call to be equal to the seq point offset.
2671 * This means we have to put the loading of bp_tramp_var after the offset.
2674 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2676 MonoInst *var = cfg->arch.bp_tramp_var;
2679 g_assert (var->opcode == OP_REGOFFSET);
2680 /* Load the address of the bp trampoline */
2681 /* This needs to be constant size */
2682 guint8 *start = code;
2683 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, 4);
2684 if (code < start + OP_SEQ_POINT_BP_OFFSET) {
2685 int size = start + OP_SEQ_POINT_BP_OFFSET - code;
2686 x86_padding (code, size);
2689 * A placeholder for a possible breakpoint inserted by
2690 * mono_arch_set_breakpoint ().
2692 for (i = 0; i < 2; ++i)
2695 * Add an additional nop so skipping the bp doesn't cause the ip to point
2696 * to another IL offset.
2704 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2708 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2713 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2717 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2722 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2726 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2731 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2735 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2738 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2742 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2747 * The code is the same for div/rem, the allocator will allocate dreg
2748 * to RAX/RDX as appropriate.
2750 if (ins->sreg2 == X86_EDX) {
2751 /* cdq clobbers this */
2752 x86_push_reg (code, ins->sreg2);
2754 x86_div_membase (code, X86_ESP, 0, TRUE);
2755 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2758 x86_div_reg (code, ins->sreg2, TRUE);
2763 if (ins->sreg2 == X86_EDX) {
2764 x86_push_reg (code, ins->sreg2);
2765 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2766 x86_div_membase (code, X86_ESP, 0, FALSE);
2767 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2769 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2770 x86_div_reg (code, ins->sreg2, FALSE);
2774 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2776 x86_div_reg (code, ins->sreg2, TRUE);
2779 int power = mono_is_power_of_two (ins->inst_imm);
2781 g_assert (ins->sreg1 == X86_EAX);
2782 g_assert (ins->dreg == X86_EAX);
2783 g_assert (power >= 0);
2786 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2788 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2790 * If the divident is >= 0, this does not nothing. If it is positive, it
2791 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2793 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2794 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2795 } else if (power == 0) {
2796 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2798 /* Based on gcc code */
2800 /* Add compensation for negative dividents */
2802 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2803 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2804 /* Compute remainder */
2805 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2806 /* Remove compensation */
2807 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2812 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2816 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2819 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2823 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2826 g_assert (ins->sreg2 == X86_ECX);
2827 x86_shift_reg (code, X86_SHL, ins->dreg);
2830 g_assert (ins->sreg2 == X86_ECX);
2831 x86_shift_reg (code, X86_SAR, ins->dreg);
2835 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2838 case OP_ISHR_UN_IMM:
2839 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2842 g_assert (ins->sreg2 == X86_ECX);
2843 x86_shift_reg (code, X86_SHR, ins->dreg);
2847 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2850 guint8 *jump_to_end;
2852 /* handle shifts below 32 bits */
2853 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2854 x86_shift_reg (code, X86_SHL, ins->sreg1);
2856 x86_test_reg_imm (code, X86_ECX, 32);
2857 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2859 /* handle shift over 32 bit */
2860 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2861 x86_clear_reg (code, ins->sreg1);
2863 x86_patch (jump_to_end, code);
2867 guint8 *jump_to_end;
2869 /* handle shifts below 32 bits */
2870 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2871 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2873 x86_test_reg_imm (code, X86_ECX, 32);
2874 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2876 /* handle shifts over 31 bits */
2877 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2878 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2880 x86_patch (jump_to_end, code);
2884 guint8 *jump_to_end;
2886 /* handle shifts below 32 bits */
2887 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2888 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2890 x86_test_reg_imm (code, X86_ECX, 32);
2891 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2893 /* handle shifts over 31 bits */
2894 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2895 x86_clear_reg (code, ins->backend.reg3);
2897 x86_patch (jump_to_end, code);
2901 if (ins->inst_imm >= 32) {
2902 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2903 x86_clear_reg (code, ins->sreg1);
2904 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2906 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2907 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2911 if (ins->inst_imm >= 32) {
2912 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2913 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2914 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2916 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2917 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2920 case OP_LSHR_UN_IMM:
2921 if (ins->inst_imm >= 32) {
2922 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2923 x86_clear_reg (code, ins->backend.reg3);
2924 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2926 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2927 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
2931 x86_not_reg (code, ins->sreg1);
2934 x86_neg_reg (code, ins->sreg1);
2938 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2942 switch (ins->inst_imm) {
2946 if (ins->dreg != ins->sreg1)
2947 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2948 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2951 /* LEA r1, [r2 + r2*2] */
2952 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2955 /* LEA r1, [r2 + r2*4] */
2956 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2959 /* LEA r1, [r2 + r2*2] */
2961 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2962 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2965 /* LEA r1, [r2 + r2*8] */
2966 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2969 /* LEA r1, [r2 + r2*4] */
2971 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2972 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2975 /* LEA r1, [r2 + r2*2] */
2977 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2978 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2981 /* LEA r1, [r2 + r2*4] */
2982 /* LEA r1, [r1 + r1*4] */
2983 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2984 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2987 /* LEA r1, [r2 + r2*4] */
2989 /* LEA r1, [r1 + r1*4] */
2990 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2991 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2992 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2995 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3000 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3001 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3003 case OP_IMUL_OVF_UN: {
3004 /* the mul operation and the exception check should most likely be split */
3005 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3006 /*g_assert (ins->sreg2 == X86_EAX);
3007 g_assert (ins->dreg == X86_EAX);*/
3008 if (ins->sreg2 == X86_EAX) {
3009 non_eax_reg = ins->sreg1;
3010 } else if (ins->sreg1 == X86_EAX) {
3011 non_eax_reg = ins->sreg2;
3013 /* no need to save since we're going to store to it anyway */
3014 if (ins->dreg != X86_EAX) {
3016 x86_push_reg (code, X86_EAX);
3018 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3019 non_eax_reg = ins->sreg2;
3021 if (ins->dreg == X86_EDX) {
3024 x86_push_reg (code, X86_EAX);
3028 x86_push_reg (code, X86_EDX);
3030 x86_mul_reg (code, non_eax_reg, FALSE);
3031 /* save before the check since pop and mov don't change the flags */
3032 if (ins->dreg != X86_EAX)
3033 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3035 x86_pop_reg (code, X86_EDX);
3037 x86_pop_reg (code, X86_EAX);
3038 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3042 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3045 g_assert_not_reached ();
3046 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3047 x86_mov_reg_imm (code, ins->dreg, 0);
3050 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3051 x86_mov_reg_imm (code, ins->dreg, 0);
3053 case OP_LOAD_GOTADDR:
3054 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3055 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3058 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3059 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3061 case OP_X86_PUSH_GOT_ENTRY:
3062 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3063 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3066 if (ins->dreg != ins->sreg1)
3067 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3070 MonoCallInst *call = (MonoCallInst*)ins;
3073 ins->flags |= MONO_INST_GC_CALLSITE;
3074 ins->backend.pc_offset = code - cfg->native_code;
3076 /* reset offset to make max_len work */
3077 offset = code - cfg->native_code;
3079 g_assert (!cfg->method->save_lmf);
3081 /* restore callee saved registers */
3082 for (i = 0; i < X86_NREG; ++i)
3083 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3085 if (cfg->used_int_regs & (1 << X86_ESI)) {
3086 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3089 if (cfg->used_int_regs & (1 << X86_EDI)) {
3090 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3093 if (cfg->used_int_regs & (1 << X86_EBX)) {
3094 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3098 /* Copy arguments on the stack to our argument area */
3099 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3100 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3101 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3104 /* restore ESP/EBP */
3106 offset = code - cfg->native_code;
3107 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3108 x86_jump32 (code, 0);
3110 ins->flags |= MONO_INST_GC_CALLSITE;
3111 cfg->disable_aot = TRUE;
3115 /* ensure ins->sreg1 is not NULL
3116 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3117 * cmp DWORD PTR [eax], 0
3119 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3122 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3123 x86_push_reg (code, hreg);
3124 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3125 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3126 x86_pop_reg (code, hreg);
3139 case OP_VOIDCALL_REG:
3141 case OP_FCALL_MEMBASE:
3142 case OP_LCALL_MEMBASE:
3143 case OP_VCALL_MEMBASE:
3144 case OP_VCALL2_MEMBASE:
3145 case OP_VOIDCALL_MEMBASE:
3146 case OP_CALL_MEMBASE: {
3149 call = (MonoCallInst*)ins;
3150 cinfo = (CallInfo*)call->call_info;
3152 switch (ins->opcode) {
3159 if (ins->flags & MONO_INST_HAS_METHOD)
3160 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3162 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3168 case OP_VOIDCALL_REG:
3170 x86_call_reg (code, ins->sreg1);
3172 case OP_FCALL_MEMBASE:
3173 case OP_LCALL_MEMBASE:
3174 case OP_VCALL_MEMBASE:
3175 case OP_VCALL2_MEMBASE:
3176 case OP_VOIDCALL_MEMBASE:
3177 case OP_CALL_MEMBASE:
3178 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3181 g_assert_not_reached ();
3184 ins->flags |= MONO_INST_GC_CALLSITE;
3185 ins->backend.pc_offset = code - cfg->native_code;
3186 if (cinfo->callee_stack_pop) {
3187 /* Have to compensate for the stack space popped by the callee */
3188 x86_alu_reg_imm (code, X86_SUB, X86_ESP, cinfo->callee_stack_pop);
3190 code = emit_move_return_value (cfg, ins, code);
3194 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3196 case OP_X86_LEA_MEMBASE:
3197 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3200 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3203 /* keep alignment */
3204 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3205 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3206 code = mono_emit_stack_alloc (cfg, code, ins);
3207 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3208 if (cfg->param_area)
3209 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3211 case OP_LOCALLOC_IMM: {
3212 guint32 size = ins->inst_imm;
3213 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3215 if (ins->flags & MONO_INST_INIT) {
3216 /* FIXME: Optimize this */
3217 x86_mov_reg_imm (code, ins->dreg, size);
3218 ins->sreg1 = ins->dreg;
3220 code = mono_emit_stack_alloc (cfg, code, ins);
3221 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3223 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3224 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3226 if (cfg->param_area)
3227 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3231 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3232 x86_push_reg (code, ins->sreg1);
3233 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3234 (gpointer)"mono_arch_throw_exception");
3235 ins->flags |= MONO_INST_GC_CALLSITE;
3236 ins->backend.pc_offset = code - cfg->native_code;
3240 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3241 x86_push_reg (code, ins->sreg1);
3242 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3243 (gpointer)"mono_arch_rethrow_exception");
3244 ins->flags |= MONO_INST_GC_CALLSITE;
3245 ins->backend.pc_offset = code - cfg->native_code;
3248 case OP_CALL_HANDLER:
3249 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3250 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3251 x86_call_imm (code, 0);
3252 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3253 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3255 case OP_START_HANDLER: {
3256 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3257 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3258 if (cfg->param_area)
3259 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3262 case OP_ENDFINALLY: {
3263 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3264 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3268 case OP_ENDFILTER: {
3269 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3270 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3271 /* The local allocator will put the result into EAX */
3276 if (ins->dreg != X86_EAX)
3277 x86_mov_reg_reg (code, ins->dreg, X86_EAX, sizeof (gpointer));
3281 ins->inst_c0 = code - cfg->native_code;
3284 if (ins->inst_target_bb->native_offset) {
3285 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3287 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3288 if ((cfg->opt & MONO_OPT_BRANCH) &&
3289 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3290 x86_jump8 (code, 0);
3292 x86_jump32 (code, 0);
3296 x86_jump_reg (code, ins->sreg1);
3315 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3316 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3318 case OP_COND_EXC_EQ:
3319 case OP_COND_EXC_NE_UN:
3320 case OP_COND_EXC_LT:
3321 case OP_COND_EXC_LT_UN:
3322 case OP_COND_EXC_GT:
3323 case OP_COND_EXC_GT_UN:
3324 case OP_COND_EXC_GE:
3325 case OP_COND_EXC_GE_UN:
3326 case OP_COND_EXC_LE:
3327 case OP_COND_EXC_LE_UN:
3328 case OP_COND_EXC_IEQ:
3329 case OP_COND_EXC_INE_UN:
3330 case OP_COND_EXC_ILT:
3331 case OP_COND_EXC_ILT_UN:
3332 case OP_COND_EXC_IGT:
3333 case OP_COND_EXC_IGT_UN:
3334 case OP_COND_EXC_IGE:
3335 case OP_COND_EXC_IGE_UN:
3336 case OP_COND_EXC_ILE:
3337 case OP_COND_EXC_ILE_UN:
3338 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3340 case OP_COND_EXC_OV:
3341 case OP_COND_EXC_NO:
3343 case OP_COND_EXC_NC:
3344 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3346 case OP_COND_EXC_IOV:
3347 case OP_COND_EXC_INO:
3348 case OP_COND_EXC_IC:
3349 case OP_COND_EXC_INC:
3350 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3362 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3370 case OP_CMOV_INE_UN:
3371 case OP_CMOV_IGE_UN:
3372 case OP_CMOV_IGT_UN:
3373 case OP_CMOV_ILE_UN:
3374 case OP_CMOV_ILT_UN:
3375 g_assert (ins->dreg == ins->sreg1);
3376 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3379 /* floating point opcodes */
3381 double d = *(double *)ins->inst_p0;
3383 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3385 } else if (d == 1.0) {
3388 if (cfg->compile_aot) {
3389 guint32 *val = (guint32*)&d;
3390 x86_push_imm (code, val [1]);
3391 x86_push_imm (code, val [0]);
3392 x86_fld_membase (code, X86_ESP, 0, TRUE);
3393 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3396 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3397 x86_fld (code, NULL, TRUE);
3403 float f = *(float *)ins->inst_p0;
3405 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3407 } else if (f == 1.0) {
3410 if (cfg->compile_aot) {
3411 guint32 val = *(guint32*)&f;
3412 x86_push_imm (code, val);
3413 x86_fld_membase (code, X86_ESP, 0, FALSE);
3414 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3417 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3418 x86_fld (code, NULL, FALSE);
3423 case OP_STORER8_MEMBASE_REG:
3424 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3426 case OP_LOADR8_MEMBASE:
3427 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3429 case OP_STORER4_MEMBASE_REG:
3430 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3432 case OP_LOADR4_MEMBASE:
3433 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3435 case OP_ICONV_TO_R4:
3436 x86_push_reg (code, ins->sreg1);
3437 x86_fild_membase (code, X86_ESP, 0, FALSE);
3438 /* Change precision */
3439 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3440 x86_fld_membase (code, X86_ESP, 0, FALSE);
3441 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3443 case OP_ICONV_TO_R8:
3444 x86_push_reg (code, ins->sreg1);
3445 x86_fild_membase (code, X86_ESP, 0, FALSE);
3446 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3448 case OP_ICONV_TO_R_UN:
3449 x86_push_imm (code, 0);
3450 x86_push_reg (code, ins->sreg1);
3451 x86_fild_membase (code, X86_ESP, 0, TRUE);
3452 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3454 case OP_X86_FP_LOAD_I8:
3455 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3457 case OP_X86_FP_LOAD_I4:
3458 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3460 case OP_FCONV_TO_R4:
3461 /* Change precision */
3462 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3463 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3464 x86_fld_membase (code, X86_ESP, 0, FALSE);
3465 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3467 case OP_FCONV_TO_I1:
3468 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3470 case OP_FCONV_TO_U1:
3471 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3473 case OP_FCONV_TO_I2:
3474 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3476 case OP_FCONV_TO_U2:
3477 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3479 case OP_FCONV_TO_I4:
3481 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3483 case OP_FCONV_TO_I8:
3484 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3485 x86_fnstcw_membase(code, X86_ESP, 0);
3486 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3487 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3488 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3489 x86_fldcw_membase (code, X86_ESP, 2);
3490 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3491 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3492 x86_pop_reg (code, ins->dreg);
3493 x86_pop_reg (code, ins->backend.reg3);
3494 x86_fldcw_membase (code, X86_ESP, 0);
3495 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3497 case OP_LCONV_TO_R8_2:
3498 x86_push_reg (code, ins->sreg2);
3499 x86_push_reg (code, ins->sreg1);
3500 x86_fild_membase (code, X86_ESP, 0, TRUE);
3501 /* Change precision */
3502 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3503 x86_fld_membase (code, X86_ESP, 0, TRUE);
3504 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3506 case OP_LCONV_TO_R4_2:
3507 x86_push_reg (code, ins->sreg2);
3508 x86_push_reg (code, ins->sreg1);
3509 x86_fild_membase (code, X86_ESP, 0, TRUE);
3510 /* Change precision */
3511 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3512 x86_fld_membase (code, X86_ESP, 0, FALSE);
3513 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3515 case OP_LCONV_TO_R_UN_2: {
3516 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3519 /* load 64bit integer to FP stack */
3520 x86_push_reg (code, ins->sreg2);
3521 x86_push_reg (code, ins->sreg1);
3522 x86_fild_membase (code, X86_ESP, 0, TRUE);
3524 /* test if lreg is negative */
3525 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3526 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3528 /* add correction constant mn */
3529 if (cfg->compile_aot) {
3530 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3531 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3532 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3533 x86_fld80_membase (code, X86_ESP, 2);
3534 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3536 x86_fld80_mem (code, mn);
3538 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3540 x86_patch (br, code);
3542 /* Change precision */
3543 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3544 x86_fld_membase (code, X86_ESP, 0, TRUE);
3546 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3550 case OP_LCONV_TO_OVF_I:
3551 case OP_LCONV_TO_OVF_I4_2: {
3552 guint8 *br [3], *label [1];
3556 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3558 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3560 /* If the low word top bit is set, see if we are negative */
3561 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3562 /* We are not negative (no top bit set, check for our top word to be zero */
3563 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3564 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3567 /* throw exception */
3568 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3570 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3571 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3572 x86_jump8 (code, 0);
3574 x86_jump32 (code, 0);
3576 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3577 x86_jump32 (code, 0);
3581 x86_patch (br [0], code);
3582 /* our top bit is set, check that top word is 0xfffffff */
3583 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3585 x86_patch (br [1], code);
3586 /* nope, emit exception */
3587 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3588 x86_patch (br [2], label [0]);
3590 if (ins->dreg != ins->sreg1)
3591 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3595 /* Not needed on the fp stack */
3597 case OP_MOVE_F_TO_I4:
3598 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
3599 x86_mov_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, 4);
3601 case OP_MOVE_I4_TO_F:
3602 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
3603 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
3606 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3609 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3612 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3615 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3623 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3628 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3635 * it really doesn't make sense to inline all this code,
3636 * it's here just to show that things may not be as simple
3639 guchar *check_pos, *end_tan, *pop_jump;
3640 x86_push_reg (code, X86_EAX);
3643 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3645 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3646 x86_fstp (code, 0); /* pop the 1.0 */
3648 x86_jump8 (code, 0);
3650 x86_fp_op (code, X86_FADD, 0);
3654 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3656 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3659 x86_patch (pop_jump, code);
3660 x86_fstp (code, 0); /* pop the 1.0 */
3661 x86_patch (check_pos, code);
3662 x86_patch (end_tan, code);
3664 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3665 x86_pop_reg (code, X86_EAX);
3672 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3681 g_assert (cfg->opt & MONO_OPT_CMOV);
3682 g_assert (ins->dreg == ins->sreg1);
3683 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3684 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3687 g_assert (cfg->opt & MONO_OPT_CMOV);
3688 g_assert (ins->dreg == ins->sreg1);
3689 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3690 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3693 g_assert (cfg->opt & MONO_OPT_CMOV);
3694 g_assert (ins->dreg == ins->sreg1);
3695 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3696 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3699 g_assert (cfg->opt & MONO_OPT_CMOV);
3700 g_assert (ins->dreg == ins->sreg1);
3701 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3702 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3708 x86_fxch (code, ins->inst_imm);
3713 x86_push_reg (code, X86_EAX);
3714 /* we need to exchange ST(0) with ST(1) */
3717 /* this requires a loop, because fprem somtimes
3718 * returns a partial remainder */
3720 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3721 /* x86_fprem1 (code); */
3724 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3726 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3732 x86_pop_reg (code, X86_EAX);
3736 if (cfg->opt & MONO_OPT_FCMOV) {
3737 x86_fcomip (code, 1);
3741 /* this overwrites EAX */
3742 EMIT_FPCOMPARE(code);
3743 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3747 if (cfg->opt & MONO_OPT_FCMOV) {
3748 /* zeroing the register at the start results in
3749 * shorter and faster code (we can also remove the widening op)
3751 guchar *unordered_check;
3752 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3753 x86_fcomip (code, 1);
3755 unordered_check = code;
3756 x86_branch8 (code, X86_CC_P, 0, FALSE);
3757 if (ins->opcode == OP_FCEQ) {
3758 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3759 x86_patch (unordered_check, code);
3761 guchar *jump_to_end;
3762 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3764 x86_jump8 (code, 0);
3765 x86_patch (unordered_check, code);
3766 x86_inc_reg (code, ins->dreg);
3767 x86_patch (jump_to_end, code);
3772 if (ins->dreg != X86_EAX)
3773 x86_push_reg (code, X86_EAX);
3775 EMIT_FPCOMPARE(code);
3776 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3777 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3778 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3779 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3781 if (ins->dreg != X86_EAX)
3782 x86_pop_reg (code, X86_EAX);
3786 if (cfg->opt & MONO_OPT_FCMOV) {
3787 /* zeroing the register at the start results in
3788 * shorter and faster code (we can also remove the widening op)
3790 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3791 x86_fcomip (code, 1);
3793 if (ins->opcode == OP_FCLT_UN) {
3794 guchar *unordered_check = code;
3795 guchar *jump_to_end;
3796 x86_branch8 (code, X86_CC_P, 0, FALSE);
3797 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3799 x86_jump8 (code, 0);
3800 x86_patch (unordered_check, code);
3801 x86_inc_reg (code, ins->dreg);
3802 x86_patch (jump_to_end, code);
3804 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3808 if (ins->dreg != X86_EAX)
3809 x86_push_reg (code, X86_EAX);
3811 EMIT_FPCOMPARE(code);
3812 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3813 if (ins->opcode == OP_FCLT_UN) {
3814 guchar *is_not_zero_check, *end_jump;
3815 is_not_zero_check = code;
3816 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3818 x86_jump8 (code, 0);
3819 x86_patch (is_not_zero_check, code);
3820 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3822 x86_patch (end_jump, code);
3824 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3825 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3827 if (ins->dreg != X86_EAX)
3828 x86_pop_reg (code, X86_EAX);
3831 guchar *unordered_check;
3832 guchar *jump_to_end;
3833 if (cfg->opt & MONO_OPT_FCMOV) {
3834 /* zeroing the register at the start results in
3835 * shorter and faster code (we can also remove the widening op)
3837 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3838 x86_fcomip (code, 1);
3840 unordered_check = code;
3841 x86_branch8 (code, X86_CC_P, 0, FALSE);
3842 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
3843 x86_patch (unordered_check, code);
3846 if (ins->dreg != X86_EAX)
3847 x86_push_reg (code, X86_EAX);
3849 EMIT_FPCOMPARE(code);
3850 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3851 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3852 unordered_check = code;
3853 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3855 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3856 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
3857 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3859 x86_jump8 (code, 0);
3860 x86_patch (unordered_check, code);
3861 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3862 x86_patch (jump_to_end, code);
3864 if (ins->dreg != X86_EAX)
3865 x86_pop_reg (code, X86_EAX);
3870 if (cfg->opt & MONO_OPT_FCMOV) {
3871 /* zeroing the register at the start results in
3872 * shorter and faster code (we can also remove the widening op)
3874 guchar *unordered_check;
3875 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3876 x86_fcomip (code, 1);
3878 if (ins->opcode == OP_FCGT) {
3879 unordered_check = code;
3880 x86_branch8 (code, X86_CC_P, 0, FALSE);
3881 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3882 x86_patch (unordered_check, code);
3884 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3888 if (ins->dreg != X86_EAX)
3889 x86_push_reg (code, X86_EAX);
3891 EMIT_FPCOMPARE(code);
3892 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3893 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3894 if (ins->opcode == OP_FCGT_UN) {
3895 guchar *is_not_zero_check, *end_jump;
3896 is_not_zero_check = code;
3897 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3899 x86_jump8 (code, 0);
3900 x86_patch (is_not_zero_check, code);
3901 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3903 x86_patch (end_jump, code);
3905 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3906 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3908 if (ins->dreg != X86_EAX)
3909 x86_pop_reg (code, X86_EAX);
3912 guchar *unordered_check;
3913 guchar *jump_to_end;
3914 if (cfg->opt & MONO_OPT_FCMOV) {
3915 /* zeroing the register at the start results in
3916 * shorter and faster code (we can also remove the widening op)
3918 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3919 x86_fcomip (code, 1);
3921 unordered_check = code;
3922 x86_branch8 (code, X86_CC_P, 0, FALSE);
3923 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
3924 x86_patch (unordered_check, code);
3927 if (ins->dreg != X86_EAX)
3928 x86_push_reg (code, X86_EAX);
3930 EMIT_FPCOMPARE(code);
3931 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3932 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3933 unordered_check = code;
3934 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3936 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3937 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
3938 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3940 x86_jump8 (code, 0);
3941 x86_patch (unordered_check, code);
3942 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3943 x86_patch (jump_to_end, code);
3945 if (ins->dreg != X86_EAX)
3946 x86_pop_reg (code, X86_EAX);
3950 if (cfg->opt & MONO_OPT_FCMOV) {
3951 guchar *jump = code;
3952 x86_branch8 (code, X86_CC_P, 0, TRUE);
3953 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3954 x86_patch (jump, code);
3957 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3958 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3961 /* Branch if C013 != 100 */
3962 if (cfg->opt & MONO_OPT_FCMOV) {
3963 /* branch if !ZF or (PF|CF) */
3964 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3965 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3966 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3969 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3970 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3973 if (cfg->opt & MONO_OPT_FCMOV) {
3974 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3977 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3980 if (cfg->opt & MONO_OPT_FCMOV) {
3981 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3982 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3985 if (ins->opcode == OP_FBLT_UN) {
3986 guchar *is_not_zero_check, *end_jump;
3987 is_not_zero_check = code;
3988 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3990 x86_jump8 (code, 0);
3991 x86_patch (is_not_zero_check, code);
3992 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3994 x86_patch (end_jump, code);
3996 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4000 if (cfg->opt & MONO_OPT_FCMOV) {
4001 if (ins->opcode == OP_FBGT) {
4004 /* skip branch if C1=1 */
4006 x86_branch8 (code, X86_CC_P, 0, FALSE);
4007 /* branch if (C0 | C3) = 1 */
4008 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4009 x86_patch (br1, code);
4011 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4015 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4016 if (ins->opcode == OP_FBGT_UN) {
4017 guchar *is_not_zero_check, *end_jump;
4018 is_not_zero_check = code;
4019 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4021 x86_jump8 (code, 0);
4022 x86_patch (is_not_zero_check, code);
4023 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4025 x86_patch (end_jump, code);
4027 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4030 /* Branch if C013 == 100 or 001 */
4031 if (cfg->opt & MONO_OPT_FCMOV) {
4034 /* skip branch if C1=1 */
4036 x86_branch8 (code, X86_CC_P, 0, FALSE);
4037 /* branch if (C0 | C3) = 1 */
4038 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4039 x86_patch (br1, code);
4042 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4043 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4044 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4045 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4048 /* Branch if C013 == 000 */
4049 if (cfg->opt & MONO_OPT_FCMOV) {
4050 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4053 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4056 /* Branch if C013=000 or 100 */
4057 if (cfg->opt & MONO_OPT_FCMOV) {
4060 /* skip branch if C1=1 */
4062 x86_branch8 (code, X86_CC_P, 0, FALSE);
4063 /* branch if C0=0 */
4064 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4065 x86_patch (br1, code);
4068 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4069 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4070 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4073 /* Branch if C013 != 001 */
4074 if (cfg->opt & MONO_OPT_FCMOV) {
4075 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4076 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4079 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4080 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4084 x86_push_reg (code, X86_EAX);
4087 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4088 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4089 x86_pop_reg (code, X86_EAX);
4091 /* Have to clean up the fp stack before throwing the exception */
4093 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4096 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
4098 x86_patch (br1, code);
4102 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4106 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4109 case OP_MEMORY_BARRIER: {
4110 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ) {
4111 x86_prefix (code, X86_LOCK_PREFIX);
4112 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4116 case OP_ATOMIC_ADD_I4: {
4117 int dreg = ins->dreg;
4119 g_assert (cfg->has_atomic_add_i4);
4121 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4122 if (ins->sreg2 == dreg) {
4123 if (dreg == X86_EBX) {
4125 if (ins->inst_basereg == X86_EDI)
4129 if (ins->inst_basereg == X86_EBX)
4132 } else if (ins->inst_basereg == dreg) {
4133 if (dreg == X86_EBX) {
4135 if (ins->sreg2 == X86_EDI)
4139 if (ins->sreg2 == X86_EBX)
4144 if (dreg != ins->dreg) {
4145 x86_push_reg (code, dreg);
4148 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4149 x86_prefix (code, X86_LOCK_PREFIX);
4150 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4151 /* dreg contains the old value, add with sreg2 value */
4152 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4154 if (ins->dreg != dreg) {
4155 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4156 x86_pop_reg (code, dreg);
4161 case OP_ATOMIC_EXCHANGE_I4: {
4163 int sreg2 = ins->sreg2;
4164 int breg = ins->inst_basereg;
4166 g_assert (cfg->has_atomic_exchange_i4);
4168 /* cmpxchg uses eax as comperand, need to make sure we can use it
4169 * hack to overcome limits in x86 reg allocator
4170 * (req: dreg == eax and sreg2 != eax and breg != eax)
4172 g_assert (ins->dreg == X86_EAX);
4174 /* We need the EAX reg for the cmpxchg */
4175 if (ins->sreg2 == X86_EAX) {
4176 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4177 x86_push_reg (code, sreg2);
4178 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4181 if (breg == X86_EAX) {
4182 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4183 x86_push_reg (code, breg);
4184 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4187 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4189 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4190 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4191 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4192 x86_patch (br [1], br [0]);
4194 if (breg != ins->inst_basereg)
4195 x86_pop_reg (code, breg);
4197 if (ins->sreg2 != sreg2)
4198 x86_pop_reg (code, sreg2);
4202 case OP_ATOMIC_CAS_I4: {
4203 g_assert (ins->dreg == X86_EAX);
4204 g_assert (ins->sreg3 == X86_EAX);
4205 g_assert (ins->sreg1 != X86_EAX);
4206 g_assert (ins->sreg1 != ins->sreg2);
4208 x86_prefix (code, X86_LOCK_PREFIX);
4209 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4212 case OP_ATOMIC_LOAD_I1: {
4213 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4216 case OP_ATOMIC_LOAD_U1: {
4217 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
4220 case OP_ATOMIC_LOAD_I2: {
4221 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4224 case OP_ATOMIC_LOAD_U2: {
4225 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
4228 case OP_ATOMIC_LOAD_I4:
4229 case OP_ATOMIC_LOAD_U4: {
4230 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4233 case OP_ATOMIC_LOAD_R4:
4234 case OP_ATOMIC_LOAD_R8: {
4235 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_R8);
4238 case OP_ATOMIC_STORE_I1:
4239 case OP_ATOMIC_STORE_U1:
4240 case OP_ATOMIC_STORE_I2:
4241 case OP_ATOMIC_STORE_U2:
4242 case OP_ATOMIC_STORE_I4:
4243 case OP_ATOMIC_STORE_U4: {
4246 switch (ins->opcode) {
4247 case OP_ATOMIC_STORE_I1:
4248 case OP_ATOMIC_STORE_U1:
4251 case OP_ATOMIC_STORE_I2:
4252 case OP_ATOMIC_STORE_U2:
4255 case OP_ATOMIC_STORE_I4:
4256 case OP_ATOMIC_STORE_U4:
4261 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
4263 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4267 case OP_ATOMIC_STORE_R4:
4268 case OP_ATOMIC_STORE_R8: {
4269 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, ins->opcode == OP_ATOMIC_STORE_R8, TRUE);
4271 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4275 case OP_CARD_TABLE_WBARRIER: {
4276 int ptr = ins->sreg1;
4277 int value = ins->sreg2;
4279 int nursery_shift, card_table_shift;
4280 gpointer card_table_mask;
4281 size_t nursery_size;
4282 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4283 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4284 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4287 * We need one register we can clobber, we choose EDX and make sreg1
4288 * fixed EAX to work around limitations in the local register allocator.
4289 * sreg2 might get allocated to EDX, but that is not a problem since
4290 * we use it before clobbering EDX.
4292 g_assert (ins->sreg1 == X86_EAX);
4295 * This is the code we produce:
4298 * edx >>= nursery_shift
4299 * cmp edx, (nursery_start >> nursery_shift)
4302 * edx >>= card_table_shift
4303 * card_table[edx] = 1
4307 if (card_table_nursery_check) {
4308 if (value != X86_EDX)
4309 x86_mov_reg_reg (code, X86_EDX, value, 4);
4310 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4311 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4312 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4314 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4315 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4316 if (card_table_mask)
4317 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4318 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4319 if (card_table_nursery_check)
4320 x86_patch (br, code);
4323 #ifdef MONO_ARCH_SIMD_INTRINSICS
4325 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4328 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4331 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4334 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4337 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4340 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4343 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4344 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4347 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4350 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4353 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4356 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4359 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4362 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4365 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4368 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4371 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4374 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4377 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4380 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4383 case OP_PSHUFLEW_HIGH:
4384 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4385 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4387 case OP_PSHUFLEW_LOW:
4388 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4389 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4392 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4393 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4396 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4397 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4400 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4401 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4405 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4408 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4411 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4414 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4417 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4420 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4423 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4424 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4427 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4430 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4433 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4436 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4439 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4442 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4445 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4448 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4451 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4454 case OP_EXTRACT_MASK:
4455 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4459 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4462 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4465 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4469 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4472 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4475 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4478 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4482 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4485 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4488 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4491 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4495 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4498 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4501 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4505 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4508 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4511 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4515 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4518 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4522 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4525 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4528 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4532 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4535 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4538 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4542 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4545 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4548 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4551 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4555 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4558 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4561 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4564 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4567 case OP_PSUM_ABS_DIFF:
4568 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4571 case OP_UNPACK_LOWB:
4572 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4574 case OP_UNPACK_LOWW:
4575 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4577 case OP_UNPACK_LOWD:
4578 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4580 case OP_UNPACK_LOWQ:
4581 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4583 case OP_UNPACK_LOWPS:
4584 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4586 case OP_UNPACK_LOWPD:
4587 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4590 case OP_UNPACK_HIGHB:
4591 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4593 case OP_UNPACK_HIGHW:
4594 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4596 case OP_UNPACK_HIGHD:
4597 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4599 case OP_UNPACK_HIGHQ:
4600 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4602 case OP_UNPACK_HIGHPS:
4603 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4605 case OP_UNPACK_HIGHPD:
4606 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4610 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4613 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4616 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4619 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4622 case OP_PADDB_SAT_UN:
4623 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4625 case OP_PSUBB_SAT_UN:
4626 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4628 case OP_PADDW_SAT_UN:
4629 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4631 case OP_PSUBW_SAT_UN:
4632 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4636 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4639 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4642 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4645 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4649 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4652 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4655 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4657 case OP_PMULW_HIGH_UN:
4658 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4661 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4665 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4668 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4672 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4675 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4679 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4682 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4686 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4689 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4693 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4696 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4700 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4703 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4707 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4710 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4714 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4717 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4721 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4724 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4728 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4730 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4731 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4735 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4737 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4738 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4742 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4744 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4745 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4749 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4751 case OP_EXTRACTX_U2:
4752 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4754 case OP_INSERTX_U1_SLOW:
4755 /*sreg1 is the extracted ireg (scratch)
4756 /sreg2 is the to be inserted ireg (scratch)
4757 /dreg is the xreg to receive the value*/
4759 /*clear the bits from the extracted word*/
4760 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4761 /*shift the value to insert if needed*/
4762 if (ins->inst_c0 & 1)
4763 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4764 /*join them together*/
4765 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4766 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4768 case OP_INSERTX_I4_SLOW:
4769 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4770 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4771 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4774 case OP_INSERTX_R4_SLOW:
4775 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4776 /*TODO if inst_c0 == 0 use movss*/
4777 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4778 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4780 case OP_INSERTX_R8_SLOW:
4781 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4782 if (cfg->verbose_level)
4783 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4785 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4787 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4790 case OP_STOREX_MEMBASE_REG:
4791 case OP_STOREX_MEMBASE:
4792 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4794 case OP_LOADX_MEMBASE:
4795 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4797 case OP_LOADX_ALIGNED_MEMBASE:
4798 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4800 case OP_STOREX_ALIGNED_MEMBASE_REG:
4801 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4803 case OP_STOREX_NTA_MEMBASE_REG:
4804 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4806 case OP_PREFETCH_MEMBASE:
4807 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4811 /*FIXME the peephole pass should have killed this*/
4812 if (ins->dreg != ins->sreg1)
4813 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4816 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4819 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->dreg, ins->dreg);
4822 case OP_FCONV_TO_R8_X:
4823 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4824 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4827 case OP_XCONV_R8_TO_I4:
4828 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4829 switch (ins->backend.source_opcode) {
4830 case OP_FCONV_TO_I1:
4831 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4833 case OP_FCONV_TO_U1:
4834 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4836 case OP_FCONV_TO_I2:
4837 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4839 case OP_FCONV_TO_U2:
4840 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4846 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4847 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4848 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4851 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4852 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4855 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4856 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4857 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4860 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4861 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4862 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4866 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4869 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4872 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4875 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4878 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4881 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
4884 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
4887 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
4891 case OP_LIVERANGE_START: {
4892 if (cfg->verbose_level > 1)
4893 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4894 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4897 case OP_LIVERANGE_END: {
4898 if (cfg->verbose_level > 1)
4899 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4900 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4903 case OP_GC_SAFE_POINT: {
4906 g_assert (mono_threads_is_coop_enabled ());
4908 x86_test_membase_imm (code, ins->sreg1, 0, 1);
4909 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4910 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
4911 x86_patch (br [0], code);
4915 case OP_GC_LIVENESS_DEF:
4916 case OP_GC_LIVENESS_USE:
4917 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4918 ins->backend.pc_offset = code - cfg->native_code;
4920 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4921 ins->backend.pc_offset = code - cfg->native_code;
4922 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4925 x86_mov_reg_reg (code, ins->dreg, X86_ESP, sizeof (mgreg_t));
4928 x86_mov_reg_reg (code, X86_ESP, ins->sreg1, sizeof (mgreg_t));
4930 case OP_FILL_PROF_CALL_CTX:
4931 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, esp), X86_ESP, sizeof (mgreg_t));
4932 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, ebp), X86_EBP, sizeof (mgreg_t));
4933 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, ebx), X86_EBX, sizeof (mgreg_t));
4934 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, esi), X86_ESI, sizeof (mgreg_t));
4935 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, edi), X86_EDI, sizeof (mgreg_t));
4938 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4939 g_assert_not_reached ();
4942 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4943 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4944 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4945 g_assert_not_reached ();
4951 cfg->code_len = code - cfg->native_code;
4954 #endif /* DISABLE_JIT */
4957 mono_arch_register_lowlevel_calls (void)
4962 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
4964 unsigned char *ip = ji->ip.i + code;
4967 case MONO_PATCH_INFO_IP:
4968 *((gconstpointer *)(ip)) = target;
4970 case MONO_PATCH_INFO_ABS:
4971 case MONO_PATCH_INFO_METHOD:
4972 case MONO_PATCH_INFO_METHOD_JUMP:
4973 case MONO_PATCH_INFO_INTERNAL_METHOD:
4974 case MONO_PATCH_INFO_BB:
4975 case MONO_PATCH_INFO_LABEL:
4976 case MONO_PATCH_INFO_RGCTX_FETCH:
4977 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
4978 x86_patch (ip, (unsigned char*)target);
4980 case MONO_PATCH_INFO_NONE:
4982 case MONO_PATCH_INFO_R4:
4983 case MONO_PATCH_INFO_R8: {
4984 guint32 offset = mono_arch_get_patch_offset (ip);
4985 *((gconstpointer *)(ip + offset)) = target;
4989 guint32 offset = mono_arch_get_patch_offset (ip);
4990 *((gconstpointer *)(ip + offset)) = target;
4996 static G_GNUC_UNUSED void
4997 stack_unaligned (MonoMethod *m, gpointer caller)
4999 printf ("%s\n", mono_method_full_name (m, TRUE));
5000 g_assert_not_reached ();
5004 mono_arch_emit_prolog (MonoCompile *cfg)
5006 MonoMethod *method = cfg->method;
5008 MonoMethodSignature *sig;
5012 int alloc_size, pos, max_offset, i, cfa_offset;
5014 gboolean need_stack_frame;
5016 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5018 code = cfg->native_code = g_malloc (cfg->code_size);
5024 /* Check that the stack is aligned on osx */
5025 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5026 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5027 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5029 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5030 x86_push_membase (code, X86_ESP, 0);
5031 x86_push_imm (code, cfg->method);
5032 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5033 x86_call_reg (code, X86_EAX);
5034 x86_patch (br [0], code);
5038 /* Offset between RSP and the CFA */
5042 cfa_offset = sizeof (gpointer);
5043 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5044 // IP saved at CFA - 4
5045 /* There is no IP reg on x86 */
5046 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5047 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5049 need_stack_frame = needs_stack_frame (cfg);
5051 if (need_stack_frame) {
5052 x86_push_reg (code, X86_EBP);
5053 cfa_offset += sizeof (gpointer);
5054 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5055 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5056 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5057 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5058 /* These are handled automatically by the stack marking code */
5059 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5061 cfg->frame_reg = X86_ESP;
5064 cfg->stack_offset += cfg->param_area;
5065 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5067 alloc_size = cfg->stack_offset;
5070 if (!method->save_lmf) {
5071 if (cfg->used_int_regs & (1 << X86_EBX)) {
5072 x86_push_reg (code, X86_EBX);
5074 cfa_offset += sizeof (gpointer);
5075 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5076 /* These are handled automatically by the stack marking code */
5077 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5080 if (cfg->used_int_regs & (1 << X86_EDI)) {
5081 x86_push_reg (code, X86_EDI);
5083 cfa_offset += sizeof (gpointer);
5084 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5085 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5088 if (cfg->used_int_regs & (1 << X86_ESI)) {
5089 x86_push_reg (code, X86_ESI);
5091 cfa_offset += sizeof (gpointer);
5092 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5093 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5099 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5100 if (mono_do_x86_stack_align && need_stack_frame) {
5101 int tot = alloc_size + pos + 4; /* ret ip */
5102 if (need_stack_frame)
5104 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5106 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5107 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5108 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5112 cfg->arch.sp_fp_offset = alloc_size + pos;
5115 /* See mono_emit_stack_alloc */
5116 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5117 guint32 remaining_size = alloc_size;
5118 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5119 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5120 guint32 offset = code - cfg->native_code;
5121 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5122 while (required_code_size >= (cfg->code_size - offset))
5123 cfg->code_size *= 2;
5124 cfg->native_code = mono_realloc_native_code(cfg);
5125 code = cfg->native_code + offset;
5126 cfg->stat_code_reallocs++;
5128 while (remaining_size >= 0x1000) {
5129 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5130 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5131 remaining_size -= 0x1000;
5134 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5136 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5139 g_assert (need_stack_frame);
5142 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5143 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5144 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5147 #if DEBUG_STACK_ALIGNMENT
5148 /* check the stack is aligned */
5149 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5150 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5151 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5152 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5153 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5154 x86_breakpoint (code);
5158 /* compute max_offset in order to use short forward jumps */
5160 if (cfg->opt & MONO_OPT_BRANCH) {
5161 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5163 bb->max_offset = max_offset;
5165 /* max alignment for loops */
5166 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5167 max_offset += LOOP_ALIGNMENT;
5168 MONO_BB_FOR_EACH_INS (bb, ins) {
5169 if (ins->opcode == OP_LABEL)
5170 ins->inst_c1 = max_offset;
5171 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5176 /* store runtime generic context */
5177 if (cfg->rgctx_var) {
5178 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5180 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5183 if (method->save_lmf)
5184 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5186 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5187 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5192 if (cfg->arch.ss_tramp_var) {
5193 /* Initialize ss_tramp_var */
5194 ins = cfg->arch.ss_tramp_var;
5195 g_assert (ins->opcode == OP_REGOFFSET);
5197 g_assert (!cfg->compile_aot);
5198 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&ss_trampoline, 4);
5201 if (cfg->arch.bp_tramp_var) {
5202 /* Initialize bp_tramp_var */
5203 ins = cfg->arch.bp_tramp_var;
5204 g_assert (ins->opcode == OP_REGOFFSET);
5206 g_assert (!cfg->compile_aot);
5207 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&bp_trampoline, 4);
5211 /* load arguments allocated to register from the stack */
5212 sig = mono_method_signature (method);
5215 cinfo = (CallInfo *)cfg->arch.cinfo;
5217 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5218 inst = cfg->args [pos];
5219 ainfo = &cinfo->args [pos];
5220 if (inst->opcode == OP_REGVAR) {
5221 g_assert (need_stack_frame);
5222 x86_mov_reg_membase (code, inst->dreg, X86_EBP, ainfo->offset + ARGS_OFFSET, 4);
5223 if (cfg->verbose_level > 2)
5224 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5229 cfg->code_len = code - cfg->native_code;
5231 g_assert (cfg->code_len < cfg->code_size);
5237 mono_arch_emit_epilog (MonoCompile *cfg)
5239 MonoMethod *method = cfg->method;
5240 MonoMethodSignature *sig = mono_method_signature (method);
5242 guint32 stack_to_pop;
5244 int max_epilog_size = 16;
5246 gboolean need_stack_frame = needs_stack_frame (cfg);
5248 if (cfg->method->save_lmf)
5249 max_epilog_size += 128;
5251 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5252 cfg->code_size *= 2;
5253 cfg->native_code = mono_realloc_native_code(cfg);
5254 cfg->stat_code_reallocs++;
5257 code = cfg->native_code + cfg->code_len;
5259 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5260 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5262 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5265 if (method->save_lmf) {
5266 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5269 /* check if we need to restore protection of the stack after a stack overflow */
5270 if (!cfg->compile_aot && mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_JIT_TLS) != -1) {
5271 code = mono_x86_emit_tls_get (code, X86_ECX, mono_tls_get_tls_offset (TLS_KEY_JIT_TLS));
5273 /* we load the value in a separate instruction: this mechanism may be
5274 * used later as a safer way to do thread interruption
5276 x86_mov_reg_membase (code, X86_ECX, X86_ECX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5277 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5279 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5280 /* note that the call trampoline will preserve eax/edx */
5281 x86_call_reg (code, X86_ECX);
5282 x86_patch (patch, code);
5285 /* restore caller saved regs */
5286 if (cfg->used_int_regs & (1 << X86_EBX)) {
5287 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), 4);
5290 if (cfg->used_int_regs & (1 << X86_EDI)) {
5291 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), 4);
5293 if (cfg->used_int_regs & (1 << X86_ESI)) {
5294 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), 4);
5297 /* EBP is restored by LEAVE */
5299 for (i = 0; i < X86_NREG; ++i) {
5300 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5306 g_assert (need_stack_frame);
5307 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5311 g_assert (need_stack_frame);
5312 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5315 if (cfg->used_int_regs & (1 << X86_ESI)) {
5316 x86_pop_reg (code, X86_ESI);
5318 if (cfg->used_int_regs & (1 << X86_EDI)) {
5319 x86_pop_reg (code, X86_EDI);
5321 if (cfg->used_int_regs & (1 << X86_EBX)) {
5322 x86_pop_reg (code, X86_EBX);
5326 /* Load returned vtypes into registers if needed */
5327 cinfo = (CallInfo *)cfg->arch.cinfo;
5328 if (cinfo->ret.storage == ArgValuetypeInReg) {
5329 for (quad = 0; quad < 2; quad ++) {
5330 switch (cinfo->ret.pair_storage [quad]) {
5332 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5334 case ArgOnFloatFpStack:
5335 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5337 case ArgOnDoubleFpStack:
5338 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5343 g_assert_not_reached ();
5348 if (need_stack_frame)
5351 if (CALLCONV_IS_STDCALL (sig)) {
5352 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5354 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
5355 } else if (cinfo->callee_stack_pop)
5356 stack_to_pop = cinfo->callee_stack_pop;
5361 g_assert (need_stack_frame);
5362 x86_ret_imm (code, stack_to_pop);
5367 cfg->code_len = code - cfg->native_code;
5369 g_assert (cfg->code_len < cfg->code_size);
5373 mono_arch_emit_exceptions (MonoCompile *cfg)
5375 MonoJumpInfo *patch_info;
5378 MonoClass *exc_classes [16];
5379 guint8 *exc_throw_start [16], *exc_throw_end [16];
5383 /* Compute needed space */
5384 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5385 if (patch_info->type == MONO_PATCH_INFO_EXC)
5390 * make sure we have enough space for exceptions
5391 * 16 is the size of two push_imm instructions and a call
5393 if (cfg->compile_aot)
5394 code_size = exc_count * 32;
5396 code_size = exc_count * 16;
5398 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5399 cfg->code_size *= 2;
5400 cfg->native_code = mono_realloc_native_code(cfg);
5401 cfg->stat_code_reallocs++;
5404 code = cfg->native_code + cfg->code_len;
5407 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5408 switch (patch_info->type) {
5409 case MONO_PATCH_INFO_EXC: {
5410 MonoClass *exc_class;
5414 x86_patch (patch_info->ip.i + cfg->native_code, code);
5416 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5417 throw_ip = patch_info->ip.i;
5419 /* Find a throw sequence for the same exception class */
5420 for (i = 0; i < nthrows; ++i)
5421 if (exc_classes [i] == exc_class)
5424 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5425 x86_jump_code (code, exc_throw_start [i]);
5426 patch_info->type = MONO_PATCH_INFO_NONE;
5431 /* Compute size of code following the push <OFFSET> */
5434 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5436 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5437 /* Use the shorter form */
5439 x86_push_imm (code, 0);
5443 x86_push_imm (code, 0xf0f0f0f0);
5448 exc_classes [nthrows] = exc_class;
5449 exc_throw_start [nthrows] = code;
5452 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5453 patch_info->data.name = "mono_arch_throw_corlib_exception";
5454 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5455 patch_info->ip.i = code - cfg->native_code;
5456 x86_call_code (code, 0);
5457 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5462 exc_throw_end [nthrows] = code;
5474 cfg->code_len = code - cfg->native_code;
5476 g_assert (cfg->code_len < cfg->code_size);
5480 mono_arch_flush_icache (guint8 *code, gint size)
5486 mono_arch_flush_register_windows (void)
5491 mono_arch_is_inst_imm (gint64 imm)
5497 mono_arch_finish_init (void)
5499 char *mono_no_tls = g_getenv ("MONO_NO_TLS");
5501 #ifndef TARGET_WIN32
5503 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5507 g_free (mono_no_tls);
5512 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5516 // Linear handler, the bsearch head compare is shorter
5517 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5518 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5519 // x86_patch(ins,target)
5520 //[1 + 5] x86_jump_mem(inst,mem)
5523 #define BR_SMALL_SIZE 2
5524 #define BR_LARGE_SIZE 5
5525 #define JUMP_IMM_SIZE 6
5526 #define ENABLE_WRONG_METHOD_CHECK 0
5530 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5532 int i, distance = 0;
5533 for (i = start; i < target; ++i)
5534 distance += imt_entries [i]->chunk_size;
5539 * LOCKING: called with the domain lock held
5542 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5543 gpointer fail_tramp)
5547 guint8 *code, *start;
5550 for (i = 0; i < count; ++i) {
5551 MonoIMTCheckItem *item = imt_entries [i];
5552 if (item->is_equals) {
5553 if (item->check_target_idx) {
5554 if (!item->compare_done)
5555 item->chunk_size += CMP_SIZE;
5556 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5559 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5561 item->chunk_size += JUMP_IMM_SIZE;
5562 #if ENABLE_WRONG_METHOD_CHECK
5563 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5568 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5569 imt_entries [item->check_target_idx]->compare_done = TRUE;
5571 size += item->chunk_size;
5574 code = mono_method_alloc_generic_virtual_trampoline (domain, size);
5576 code = mono_domain_code_reserve (domain, size);
5579 unwind_ops = mono_arch_get_cie_program ();
5581 for (i = 0; i < count; ++i) {
5582 MonoIMTCheckItem *item = imt_entries [i];
5583 item->code_target = code;
5584 if (item->is_equals) {
5585 if (item->check_target_idx) {
5586 if (!item->compare_done)
5587 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5588 item->jmp_code = code;
5589 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5590 if (item->has_target_code)
5591 x86_jump_code (code, item->value.target_code);
5593 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5596 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5597 item->jmp_code = code;
5598 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5599 if (item->has_target_code)
5600 x86_jump_code (code, item->value.target_code);
5602 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5603 x86_patch (item->jmp_code, code);
5604 x86_jump_code (code, fail_tramp);
5605 item->jmp_code = NULL;
5607 /* enable the commented code to assert on wrong method */
5608 #if ENABLE_WRONG_METHOD_CHECK
5609 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5610 item->jmp_code = code;
5611 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5613 if (item->has_target_code)
5614 x86_jump_code (code, item->value.target_code);
5616 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5617 #if ENABLE_WRONG_METHOD_CHECK
5618 x86_patch (item->jmp_code, code);
5619 x86_breakpoint (code);
5620 item->jmp_code = NULL;
5625 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5626 item->jmp_code = code;
5627 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5628 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5630 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5633 /* patch the branches to get to the target items */
5634 for (i = 0; i < count; ++i) {
5635 MonoIMTCheckItem *item = imt_entries [i];
5636 if (item->jmp_code) {
5637 if (item->check_target_idx) {
5638 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5644 mono_stats.imt_trampolines_size += code - start;
5645 g_assert (code - start <= size);
5649 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5650 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5654 if (mono_jit_map_is_enabled ()) {
5657 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5659 buff = g_strdup_printf ("imt_trampoline_entries_%d", count);
5660 mono_emit_jit_tramp (start, code - start, buff);
5664 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL));
5666 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
5672 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5674 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5678 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5680 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5684 mono_arch_get_cie_program (void)
5688 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5689 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5695 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5697 MonoInst *ins = NULL;
5700 if (cmethod->klass == mono_defaults.math_class) {
5701 if (strcmp (cmethod->name, "Sin") == 0) {
5703 } else if (strcmp (cmethod->name, "Cos") == 0) {
5705 } else if (strcmp (cmethod->name, "Tan") == 0) {
5707 } else if (strcmp (cmethod->name, "Atan") == 0) {
5709 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5711 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5713 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5717 if (opcode && fsig->param_count == 1) {
5718 MONO_INST_NEW (cfg, ins, opcode);
5719 ins->type = STACK_R8;
5720 ins->dreg = mono_alloc_freg (cfg);
5721 ins->sreg1 = args [0]->dreg;
5722 MONO_ADD_INS (cfg->cbb, ins);
5725 if (cfg->opt & MONO_OPT_CMOV) {
5728 if (strcmp (cmethod->name, "Min") == 0) {
5729 if (fsig->params [0]->type == MONO_TYPE_I4)
5731 } else if (strcmp (cmethod->name, "Max") == 0) {
5732 if (fsig->params [0]->type == MONO_TYPE_I4)
5736 if (opcode && fsig->param_count == 2) {
5737 MONO_INST_NEW (cfg, ins, opcode);
5738 ins->type = STACK_I4;
5739 ins->dreg = mono_alloc_ireg (cfg);
5740 ins->sreg1 = args [0]->dreg;
5741 ins->sreg2 = args [1]->dreg;
5742 MONO_ADD_INS (cfg->cbb, ins);
5747 /* OP_FREM is not IEEE compatible */
5748 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
5749 MONO_INST_NEW (cfg, ins, OP_FREM);
5750 ins->inst_i0 = args [0];
5751 ins->inst_i1 = args [1];
5760 mono_arch_print_tree (MonoInst *tree, int arity)
5766 mono_arch_get_patch_offset (guint8 *code)
5768 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5770 else if (code [0] == 0xba)
5772 else if (code [0] == 0x68)
5775 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5776 /* push <OFFSET>(<REG>) */
5778 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5779 /* call *<OFFSET>(<REG>) */
5781 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5784 else if ((code [0] == 0x58) && (code [1] == 0x05))
5785 /* pop %eax; add <OFFSET>, %eax */
5787 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5788 /* pop <REG>; add <OFFSET>, <REG> */
5790 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5791 /* mov <REG>, imm */
5794 g_assert_not_reached ();
5800 * \return TRUE if no sw breakpoint was present.
5802 * Copy \p size bytes from \p code - \p offset to the buffer \p buf. If the debugger inserted software
5803 * breakpoints in the original code, they are removed in the copy.
5806 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5809 * If method_start is non-NULL we need to perform bound checks, since we access memory
5810 * at code - offset we could go before the start of the method and end up in a different
5811 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5814 if (!method_start || code - offset >= method_start) {
5815 memcpy (buf, code - offset, size);
5817 int diff = code - method_start;
5818 memset (buf, 0, size);
5819 memcpy (buf + offset - diff, method_start, diff + size - offset);
5825 * mono_x86_get_this_arg_offset:
5827 * Return the offset of the stack location where this is passed during a virtual
5831 mono_x86_get_this_arg_offset (MonoMethodSignature *sig)
5837 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
5839 guint32 esp = regs [X86_ESP];
5846 * The stack looks like:
5850 res = ((MonoObject**)esp) [0];
5854 #define MAX_ARCH_DELEGATE_PARAMS 10
5857 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
5859 guint8 *code, *start;
5860 int code_reserve = 64;
5863 unwind_ops = mono_arch_get_cie_program ();
5866 * The stack contains:
5872 start = code = mono_global_codeman_reserve (code_reserve);
5874 /* Replace the this argument with the target */
5875 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5876 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
5877 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5878 x86_jump_membase (code, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
5880 g_assert ((code - start) < code_reserve);
5883 /* 8 for mov_reg and jump, plus 8 for each parameter */
5884 code_reserve = 8 + (param_count * 8);
5886 * The stack contains:
5887 * <args in reverse order>
5892 * <args in reverse order>
5895 * without unbalancing the stack.
5896 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
5897 * and leaving original spot of first arg as placeholder in stack so
5898 * when callee pops stack everything works.
5901 start = code = mono_global_codeman_reserve (code_reserve);
5903 /* store delegate for access to method_ptr */
5904 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
5907 for (i = 0; i < param_count; ++i) {
5908 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
5909 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
5912 x86_jump_membase (code, X86_ECX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
5914 g_assert ((code - start) < code_reserve);
5918 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
5920 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
5921 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
5925 if (mono_jit_map_is_enabled ()) {
5928 buff = (char*)"delegate_invoke_has_target";
5930 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
5931 mono_emit_jit_tramp (start, code - start, buff);
5935 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
5940 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
5943 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
5945 guint8 *code, *start;
5950 if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
5954 * The stack contains:
5958 start = code = mono_global_codeman_reserve (size);
5960 unwind_ops = mono_arch_get_cie_program ();
5962 /* Replace the this argument with the target */
5963 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5964 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
5965 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5968 /* Load the IMT reg */
5969 x86_mov_reg_membase (code, MONO_ARCH_IMT_REG, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 4);
5972 /* Load the vtable */
5973 x86_mov_reg_membase (code, X86_EAX, X86_ECX, MONO_STRUCT_OFFSET (MonoObject, vtable), 4);
5974 x86_jump_membase (code, X86_EAX, offset);
5975 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
5977 tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
5978 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
5979 g_free (tramp_name);
5986 mono_arch_get_delegate_invoke_impls (void)
5989 MonoTrampInfo *info;
5992 get_delegate_invoke_impl (&info, TRUE, 0);
5993 res = g_slist_prepend (res, info);
5995 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
5996 get_delegate_invoke_impl (&info, FALSE, i);
5997 res = g_slist_prepend (res, info);
6000 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
6001 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
6002 res = g_slist_prepend (res, info);
6004 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
6005 res = g_slist_prepend (res, info);
6012 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6014 guint8 *code, *start;
6016 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6019 /* FIXME: Support more cases */
6020 if (MONO_TYPE_ISSTRUCT (sig->ret))
6024 * The stack contains:
6030 static guint8* cached = NULL;
6034 if (mono_aot_only) {
6035 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6037 MonoTrampInfo *info;
6038 start = get_delegate_invoke_impl (&info, TRUE, 0);
6039 mono_tramp_info_register (info, NULL);
6042 mono_memory_barrier ();
6046 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6049 for (i = 0; i < sig->param_count; ++i)
6050 if (!mono_is_regsize_var (sig->params [i]))
6053 code = cache [sig->param_count];
6057 if (mono_aot_only) {
6058 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6059 start = mono_aot_get_trampoline (name);
6062 MonoTrampInfo *info;
6063 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
6064 mono_tramp_info_register (info, NULL);
6067 mono_memory_barrier ();
6069 cache [sig->param_count] = start;
6076 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
6078 MonoTrampInfo *info;
6081 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
6083 mono_tramp_info_register (info, NULL);
6088 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6091 case X86_EAX: return ctx->eax;
6092 case X86_EBX: return ctx->ebx;
6093 case X86_ECX: return ctx->ecx;
6094 case X86_EDX: return ctx->edx;
6095 case X86_ESP: return ctx->esp;
6096 case X86_EBP: return ctx->ebp;
6097 case X86_ESI: return ctx->esi;
6098 case X86_EDI: return ctx->edi;
6100 g_assert_not_reached ();
6106 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6134 g_assert_not_reached ();
6138 #ifdef MONO_ARCH_SIMD_INTRINSICS
6141 get_float_to_x_spill_area (MonoCompile *cfg)
6143 if (!cfg->fconv_to_r8_x_var) {
6144 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6145 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6147 return cfg->fconv_to_r8_x_var;
6151 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6154 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6157 int dreg, src_opcode;
6159 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6162 switch (src_opcode = ins->opcode) {
6163 case OP_FCONV_TO_I1:
6164 case OP_FCONV_TO_U1:
6165 case OP_FCONV_TO_I2:
6166 case OP_FCONV_TO_U2:
6167 case OP_FCONV_TO_I4:
6174 /* dreg is the IREG and sreg1 is the FREG */
6175 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6176 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6177 fconv->sreg1 = ins->sreg1;
6178 fconv->dreg = mono_alloc_ireg (cfg);
6179 fconv->type = STACK_VTYPE;
6180 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6182 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6186 ins->opcode = OP_XCONV_R8_TO_I4;
6188 ins->klass = mono_defaults.int32_class;
6189 ins->sreg1 = fconv->dreg;
6191 ins->type = STACK_I4;
6192 ins->backend.source_opcode = src_opcode;
6195 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6198 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6203 if (long_ins->opcode == OP_LNEG) {
6205 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
6206 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
6207 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->dreg));
6212 #ifdef MONO_ARCH_SIMD_INTRINSICS
6214 if (!(cfg->opt & MONO_OPT_SIMD))
6217 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6218 switch (long_ins->opcode) {
6220 vreg = long_ins->sreg1;
6222 if (long_ins->inst_c0) {
6223 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6224 ins->klass = long_ins->klass;
6225 ins->sreg1 = long_ins->sreg1;
6227 ins->type = STACK_VTYPE;
6228 ins->dreg = vreg = alloc_ireg (cfg);
6229 MONO_ADD_INS (cfg->cbb, ins);
6232 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6233 ins->klass = mono_defaults.int32_class;
6235 ins->type = STACK_I4;
6236 ins->dreg = MONO_LVREG_LS (long_ins->dreg);
6237 MONO_ADD_INS (cfg->cbb, ins);
6239 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6240 ins->klass = long_ins->klass;
6241 ins->sreg1 = long_ins->sreg1;
6242 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6243 ins->type = STACK_VTYPE;
6244 ins->dreg = vreg = alloc_ireg (cfg);
6245 MONO_ADD_INS (cfg->cbb, ins);
6247 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6248 ins->klass = mono_defaults.int32_class;
6250 ins->type = STACK_I4;
6251 ins->dreg = MONO_LVREG_MS (long_ins->dreg);
6252 MONO_ADD_INS (cfg->cbb, ins);
6254 long_ins->opcode = OP_NOP;
6256 case OP_INSERTX_I8_SLOW:
6257 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6258 ins->dreg = long_ins->dreg;
6259 ins->sreg1 = long_ins->dreg;
6260 ins->sreg2 = MONO_LVREG_LS (long_ins->sreg2);
6261 ins->inst_c0 = long_ins->inst_c0 * 2;
6262 MONO_ADD_INS (cfg->cbb, ins);
6264 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6265 ins->dreg = long_ins->dreg;
6266 ins->sreg1 = long_ins->dreg;
6267 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg2);
6268 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6269 MONO_ADD_INS (cfg->cbb, ins);
6271 long_ins->opcode = OP_NOP;
6274 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6275 ins->dreg = long_ins->dreg;
6276 ins->sreg1 = MONO_LVREG_LS (long_ins->sreg1);
6277 ins->klass = long_ins->klass;
6278 ins->type = STACK_VTYPE;
6279 MONO_ADD_INS (cfg->cbb, ins);
6281 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6282 ins->dreg = long_ins->dreg;
6283 ins->sreg1 = long_ins->dreg;
6284 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg1);
6286 ins->klass = long_ins->klass;
6287 ins->type = STACK_VTYPE;
6288 MONO_ADD_INS (cfg->cbb, ins);
6290 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6291 ins->dreg = long_ins->dreg;
6292 ins->sreg1 = long_ins->dreg;;
6293 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6294 ins->klass = long_ins->klass;
6295 ins->type = STACK_VTYPE;
6296 MONO_ADD_INS (cfg->cbb, ins);
6298 long_ins->opcode = OP_NOP;
6301 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6305 * mono_aot_emit_load_got_addr:
6307 * Emit code to load the got address.
6308 * On x86, the result is placed into EBX.
6311 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6313 x86_call_imm (code, 0);
6315 * The patch needs to point to the pop, since the GOT offset needs
6316 * to be added to that address.
6319 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6321 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6322 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6323 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6329 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6332 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6334 g_assert_not_reached ();
6335 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6340 * mono_arch_emit_load_aotconst:
6342 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6343 * TARGET from the mscorlib GOT in full-aot code.
6344 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6348 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
6350 /* Load the mscorlib got address */
6351 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6352 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6353 /* arch_emit_got_access () patches this */
6354 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6359 /* Can't put this into mini-x86.h */
6361 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6364 mono_arch_get_trampolines (gboolean aot)
6366 MonoTrampInfo *info;
6367 GSList *tramps = NULL;
6369 mono_x86_get_signal_exception_trampoline (&info, aot);
6371 tramps = g_slist_append (tramps, info);
6376 /* Soft Debug support */
6377 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6380 * mono_arch_set_breakpoint:
6382 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6383 * The location should contain code emitted by OP_SEQ_POINT.
6386 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6388 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6390 g_assert (code [0] == 0x90);
6391 x86_call_membase (code, X86_ECX, 0);
6395 * mono_arch_clear_breakpoint:
6397 * Clear the breakpoint at IP.
6400 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6402 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6405 for (i = 0; i < 2; ++i)
6410 * mono_arch_start_single_stepping:
6412 * Start single stepping.
6415 mono_arch_start_single_stepping (void)
6417 ss_trampoline = mini_get_single_step_trampoline ();
6421 * mono_arch_stop_single_stepping:
6423 * Stop single stepping.
6426 mono_arch_stop_single_stepping (void)
6428 ss_trampoline = NULL;
6432 * mono_arch_is_single_step_event:
6434 * Return whenever the machine state in SIGCTX corresponds to a single
6438 mono_arch_is_single_step_event (void *info, void *sigctx)
6440 /* We use soft breakpoints */
6445 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6447 /* We use soft breakpoints */
6451 #define BREAKPOINT_SIZE 2
6454 * mono_arch_skip_breakpoint:
6456 * See mini-amd64.c for docs.
6459 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6461 g_assert_not_reached ();
6465 * mono_arch_skip_single_step:
6467 * See mini-amd64.c for docs.
6470 mono_arch_skip_single_step (MonoContext *ctx)
6472 g_assert_not_reached ();
6476 * mono_arch_get_seq_point_info:
6478 * See mini-amd64.c for docs.
6481 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6488 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6490 ext->lmf.previous_lmf = (gsize)prev_lmf;
6491 /* Mark that this is a MonoLMFExt */
6492 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6493 ext->lmf.ebp = (gssize)ext;
6499 mono_arch_opcode_supported (int opcode)
6502 case OP_ATOMIC_ADD_I4:
6503 case OP_ATOMIC_EXCHANGE_I4:
6504 case OP_ATOMIC_CAS_I4:
6505 case OP_ATOMIC_LOAD_I1:
6506 case OP_ATOMIC_LOAD_I2:
6507 case OP_ATOMIC_LOAD_I4:
6508 case OP_ATOMIC_LOAD_U1:
6509 case OP_ATOMIC_LOAD_U2:
6510 case OP_ATOMIC_LOAD_U4:
6511 case OP_ATOMIC_LOAD_R4:
6512 case OP_ATOMIC_LOAD_R8:
6513 case OP_ATOMIC_STORE_I1:
6514 case OP_ATOMIC_STORE_I2:
6515 case OP_ATOMIC_STORE_I4:
6516 case OP_ATOMIC_STORE_U1:
6517 case OP_ATOMIC_STORE_U2:
6518 case OP_ATOMIC_STORE_U4:
6519 case OP_ATOMIC_STORE_R4:
6520 case OP_ATOMIC_STORE_R8:
6528 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
6530 return get_call_info (mp, sig);