2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * (C) 2003 Ximian, Inc.
18 #include <mono/metadata/appdomain.h>
19 #include <mono/metadata/debug-helpers.h>
20 #include <mono/metadata/threads.h>
21 #include <mono/metadata/profiler-private.h>
22 #include <mono/metadata/mono-debug.h>
23 #include <mono/metadata/gc-internal.h>
24 #include <mono/utils/mono-math.h>
25 #include <mono/utils/mono-counters.h>
26 #include <mono/utils/mono-mmap.h>
33 /* On windows, these hold the key returned by TlsAlloc () */
34 static gint lmf_tls_offset = -1;
35 static gint lmf_addr_tls_offset = -1;
36 static gint appdomain_tls_offset = -1;
39 static gboolean optimize_for_xen = TRUE;
41 #define optimize_for_xen 0
45 static gboolean is_win32 = TRUE;
47 static gboolean is_win32 = FALSE;
50 /* This mutex protects architecture specific caches */
51 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
52 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
53 static CRITICAL_SECTION mini_arch_mutex;
55 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
60 /* Under windows, the default pinvoke calling convention is stdcall */
61 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT))
63 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL)
66 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
72 #ifdef __native_client_codegen__
73 const guint kNaClAlignment = kNaClAlignmentX86;
74 const guint kNaClAlignmentMask = kNaClAlignmentMaskX86;
76 /* Default alignment for Native Client is 32-byte. */
77 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
79 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
80 /* Check that alignment doesn't cross an alignment boundary. */
82 mono_arch_nacl_pad (guint8 *code, int pad)
84 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
86 if (pad == 0) return code;
87 /* assertion: alignment cannot cross a block boundary */
88 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
89 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
90 while (pad >= kMaxPadding) {
91 x86_padding (code, kMaxPadding);
94 if (pad != 0) x86_padding (code, pad);
99 mono_arch_nacl_skip_nops (guint8 *code)
101 x86_skip_nops (code);
105 #endif /* __native_client_codegen__ */
108 * The code generated for sequence points reads from this location, which is
109 * made read-only when single stepping is enabled.
111 static gpointer ss_trigger_page;
113 /* Enabled breakpoints read from this trigger page */
114 static gpointer bp_trigger_page;
117 mono_arch_regname (int reg)
120 case X86_EAX: return "%eax";
121 case X86_EBX: return "%ebx";
122 case X86_ECX: return "%ecx";
123 case X86_EDX: return "%edx";
124 case X86_ESP: return "%esp";
125 case X86_EBP: return "%ebp";
126 case X86_EDI: return "%edi";
127 case X86_ESI: return "%esi";
133 mono_arch_fregname (int reg)
158 mono_arch_xregname (int reg)
183 mono_x86_patch (unsigned char* code, gpointer target)
185 x86_patch (code, (unsigned char*)target);
204 /* Only if storage == ArgValuetypeInReg */
205 ArgStorage pair_storage [2];
214 gboolean need_stack_align;
215 guint32 stack_align_amount;
216 gboolean vtype_retaddr;
217 /* The index of the vret arg in the argument list */
226 #define FLOAT_PARAM_REGS 0
228 static X86_Reg_No param_regs [] = { 0 };
230 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
231 #define SMALL_STRUCTS_IN_REGS
232 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
236 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
238 ainfo->offset = *stack_size;
240 if (*gr >= PARAM_REGS) {
241 ainfo->storage = ArgOnStack;
242 (*stack_size) += sizeof (gpointer);
245 ainfo->storage = ArgInIReg;
246 ainfo->reg = param_regs [*gr];
252 add_general_pair (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
254 ainfo->offset = *stack_size;
256 g_assert (PARAM_REGS == 0);
258 ainfo->storage = ArgOnStack;
259 (*stack_size) += sizeof (gpointer) * 2;
263 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
265 ainfo->offset = *stack_size;
267 if (*gr >= FLOAT_PARAM_REGS) {
268 ainfo->storage = ArgOnStack;
269 (*stack_size) += is_double ? 8 : 4;
272 /* A double register */
274 ainfo->storage = ArgInDoubleSSEReg;
276 ainfo->storage = ArgInFloatSSEReg;
284 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
286 guint32 *gr, guint32 *fr, guint32 *stack_size)
291 klass = mono_class_from_mono_type (type);
292 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
294 #ifdef SMALL_STRUCTS_IN_REGS
295 if (sig->pinvoke && is_return) {
296 MonoMarshalType *info;
299 * the exact rules are not very well documented, the code below seems to work with the
300 * code generated by gcc 3.3.3 -mno-cygwin.
302 info = mono_marshal_load_type_info (klass);
305 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
307 /* Special case structs with only a float member */
308 if ((info->native_size == 8) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R8)) {
309 ainfo->storage = ArgValuetypeInReg;
310 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
313 if ((info->native_size == 4) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R4)) {
314 ainfo->storage = ArgValuetypeInReg;
315 ainfo->pair_storage [0] = ArgOnFloatFpStack;
318 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
319 ainfo->storage = ArgValuetypeInReg;
320 ainfo->pair_storage [0] = ArgInIReg;
321 ainfo->pair_regs [0] = return_regs [0];
322 if (info->native_size > 4) {
323 ainfo->pair_storage [1] = ArgInIReg;
324 ainfo->pair_regs [1] = return_regs [1];
331 ainfo->offset = *stack_size;
332 ainfo->storage = ArgOnStack;
333 *stack_size += ALIGN_TO (size, sizeof (gpointer));
339 * Obtain information about a call according to the calling convention.
340 * For x86 ELF, see the "System V Application Binary Interface Intel386
341 * Architecture Processor Supplment, Fourth Edition" document for more
343 * For x86 win32, see ???.
346 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
348 guint32 i, gr, fr, pstart;
350 int n = sig->hasthis + sig->param_count;
351 guint32 stack_size = 0;
352 gboolean is_pinvoke = sig->pinvoke;
359 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
360 switch (ret_type->type) {
361 case MONO_TYPE_BOOLEAN:
372 case MONO_TYPE_FNPTR:
373 case MONO_TYPE_CLASS:
374 case MONO_TYPE_OBJECT:
375 case MONO_TYPE_SZARRAY:
376 case MONO_TYPE_ARRAY:
377 case MONO_TYPE_STRING:
378 cinfo->ret.storage = ArgInIReg;
379 cinfo->ret.reg = X86_EAX;
383 cinfo->ret.storage = ArgInIReg;
384 cinfo->ret.reg = X86_EAX;
387 cinfo->ret.storage = ArgOnFloatFpStack;
390 cinfo->ret.storage = ArgOnDoubleFpStack;
392 case MONO_TYPE_GENERICINST:
393 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
394 cinfo->ret.storage = ArgInIReg;
395 cinfo->ret.reg = X86_EAX;
399 case MONO_TYPE_VALUETYPE: {
400 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
402 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
403 if (cinfo->ret.storage == ArgOnStack) {
404 cinfo->vtype_retaddr = TRUE;
405 /* The caller passes the address where the value is stored */
409 case MONO_TYPE_TYPEDBYREF:
410 /* Same as a valuetype with size 12 */
411 cinfo->vtype_retaddr = TRUE;
414 cinfo->ret.storage = ArgNone;
417 g_error ("Can't handle as return value 0x%x", sig->ret->type);
423 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
424 * the first argument, allowing 'this' to be always passed in the first arg reg.
425 * Also do this if the first argument is a reference type, since virtual calls
426 * are sometimes made using calli without sig->hasthis set, like in the delegate
429 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
431 add_general (&gr, &stack_size, cinfo->args + 0);
433 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
436 add_general (&gr, &stack_size, &cinfo->ret);
437 cinfo->vret_arg_index = 1;
441 add_general (&gr, &stack_size, cinfo->args + 0);
443 if (cinfo->vtype_retaddr)
444 add_general (&gr, &stack_size, &cinfo->ret);
447 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
449 fr = FLOAT_PARAM_REGS;
451 /* Emit the signature cookie just before the implicit arguments */
452 add_general (&gr, &stack_size, &cinfo->sig_cookie);
455 for (i = pstart; i < sig->param_count; ++i) {
456 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
459 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
460 /* We allways pass the sig cookie on the stack for simplicity */
462 * Prevent implicit arguments + the sig cookie from being passed
466 fr = FLOAT_PARAM_REGS;
468 /* Emit the signature cookie just before the implicit arguments */
469 add_general (&gr, &stack_size, &cinfo->sig_cookie);
472 if (sig->params [i]->byref) {
473 add_general (&gr, &stack_size, ainfo);
476 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
477 switch (ptype->type) {
478 case MONO_TYPE_BOOLEAN:
481 add_general (&gr, &stack_size, ainfo);
486 add_general (&gr, &stack_size, ainfo);
490 add_general (&gr, &stack_size, ainfo);
495 case MONO_TYPE_FNPTR:
496 case MONO_TYPE_CLASS:
497 case MONO_TYPE_OBJECT:
498 case MONO_TYPE_STRING:
499 case MONO_TYPE_SZARRAY:
500 case MONO_TYPE_ARRAY:
501 add_general (&gr, &stack_size, ainfo);
503 case MONO_TYPE_GENERICINST:
504 if (!mono_type_generic_inst_is_valuetype (ptype)) {
505 add_general (&gr, &stack_size, ainfo);
509 case MONO_TYPE_VALUETYPE:
510 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
512 case MONO_TYPE_TYPEDBYREF:
513 stack_size += sizeof (MonoTypedRef);
514 ainfo->storage = ArgOnStack;
518 add_general_pair (&gr, &stack_size, ainfo);
521 add_float (&fr, &stack_size, ainfo, FALSE);
524 add_float (&fr, &stack_size, ainfo, TRUE);
527 g_error ("unexpected type 0x%x", ptype->type);
528 g_assert_not_reached ();
532 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
534 fr = FLOAT_PARAM_REGS;
536 /* Emit the signature cookie just before the implicit arguments */
537 add_general (&gr, &stack_size, &cinfo->sig_cookie);
540 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
541 cinfo->need_stack_align = TRUE;
542 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
543 stack_size += cinfo->stack_align_amount;
546 cinfo->stack_usage = stack_size;
547 cinfo->reg_usage = gr;
548 cinfo->freg_usage = fr;
553 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
555 int n = sig->hasthis + sig->param_count;
559 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
561 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
563 return get_call_info_internal (gsctx, cinfo, sig);
567 * mono_arch_get_argument_info:
568 * @csig: a method signature
569 * @param_count: the number of parameters to consider
570 * @arg_info: an array to store the result infos
572 * Gathers information on parameters such as size, alignment and
573 * padding. arg_info should be large enought to hold param_count + 1 entries.
575 * Returns the size of the argument area on the stack.
576 * This should be signal safe, since it is called from
577 * mono_arch_find_jit_info ().
578 * FIXME: The metadata calls might not be signal safe.
581 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
583 int len, k, args_size = 0;
589 /* Avoid g_malloc as it is not signal safe */
590 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
591 cinfo = (CallInfo*)g_newa (guint8*, len);
592 memset (cinfo, 0, len);
594 cinfo = get_call_info_internal (NULL, cinfo, csig);
596 arg_info [0].offset = offset;
598 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
599 args_size += sizeof (gpointer);
604 args_size += sizeof (gpointer);
608 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
609 /* Emitted after this */
610 args_size += sizeof (gpointer);
614 arg_info [0].size = args_size;
616 for (k = 0; k < param_count; k++) {
617 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
619 /* ignore alignment for now */
622 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
623 arg_info [k].pad = pad;
625 arg_info [k + 1].pad = 0;
626 arg_info [k + 1].size = size;
628 arg_info [k + 1].offset = offset;
631 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
632 /* Emitted after the first arg */
633 args_size += sizeof (gpointer);
638 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
639 align = MONO_ARCH_FRAME_ALIGNMENT;
642 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
643 arg_info [k].pad = pad;
649 mono_x86_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
654 c1 = get_call_info (NULL, NULL, caller_sig);
655 c2 = get_call_info (NULL, NULL, callee_sig);
656 res = c1->stack_usage >= c2->stack_usage;
657 if (callee_sig->ret && MONO_TYPE_ISSTRUCT (callee_sig->ret) && c2->ret.storage != ArgValuetypeInReg)
658 /* An address on the callee's stack is passed as the first argument */
667 static const guchar cpuid_impl [] = {
668 0x55, /* push %ebp */
669 0x89, 0xe5, /* mov %esp,%ebp */
670 0x53, /* push %ebx */
671 0x8b, 0x45, 0x08, /* mov 0x8(%ebp),%eax */
672 0x0f, 0xa2, /* cpuid */
673 0x50, /* push %eax */
674 0x8b, 0x45, 0x10, /* mov 0x10(%ebp),%eax */
675 0x89, 0x18, /* mov %ebx,(%eax) */
676 0x8b, 0x45, 0x14, /* mov 0x14(%ebp),%eax */
677 0x89, 0x08, /* mov %ecx,(%eax) */
678 0x8b, 0x45, 0x18, /* mov 0x18(%ebp),%eax */
679 0x89, 0x10, /* mov %edx,(%eax) */
681 0x8b, 0x55, 0x0c, /* mov 0xc(%ebp),%edx */
682 0x89, 0x02, /* mov %eax,(%edx) */
688 typedef void (*CpuidFunc) (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx);
691 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
693 #if defined(__native_client__)
694 /* Taken from below, the bug listed in the comment is */
695 /* only valid for non-static cases. */
696 __asm__ __volatile__ ("cpuid"
697 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
703 __asm__ __volatile__ (
706 "movl %%eax, %%edx\n"
707 "xorl $0x200000, %%eax\n"
712 "xorl %%edx, %%eax\n"
713 "andl $0x200000, %%eax\n"
735 /* Have to use the code manager to get around WinXP DEP */
736 static CpuidFunc func = NULL;
739 ptr = mono_global_codeman_reserve (sizeof (cpuid_impl));
740 memcpy (ptr, cpuid_impl, sizeof (cpuid_impl));
741 func = (CpuidFunc)ptr;
743 func (id, p_eax, p_ebx, p_ecx, p_edx);
746 * We use this approach because of issues with gcc and pic code, see:
747 * http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=7329
748 __asm__ __volatile__ ("cpuid"
749 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
759 * Initialize the cpu to execute managed code.
762 mono_arch_cpu_init (void)
764 /* spec compliance requires running with double precision */
768 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
769 fpcw &= ~X86_FPCW_PRECC_MASK;
770 fpcw |= X86_FPCW_PREC_DOUBLE;
771 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
772 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
774 _control87 (_PC_53, MCW_PC);
779 * Initialize architecture specific code.
782 mono_arch_init (void)
784 InitializeCriticalSection (&mini_arch_mutex);
786 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
787 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
788 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
790 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
791 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
795 * Cleanup architecture specific code.
798 mono_arch_cleanup (void)
800 DeleteCriticalSection (&mini_arch_mutex);
804 * This function returns the optimizations supported on this cpu.
807 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
809 #if !defined(__native_client__)
810 int eax, ebx, ecx, edx;
816 /* The cpuid function allocates from the global codeman */
819 /* Feature Flags function, flags returned in EDX. */
820 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
821 if (edx & (1 << 15)) {
822 opts |= MONO_OPT_CMOV;
824 opts |= MONO_OPT_FCMOV;
826 *exclude_mask |= MONO_OPT_FCMOV;
828 *exclude_mask |= MONO_OPT_CMOV;
830 opts |= MONO_OPT_SSE2;
832 *exclude_mask |= MONO_OPT_SSE2;
834 #ifdef MONO_ARCH_SIMD_INTRINSICS
835 /*SIMD intrinsics require at least SSE2.*/
836 if (!(opts & MONO_OPT_SSE2))
837 *exclude_mask |= MONO_OPT_SIMD;
842 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
847 * This function test for all SSE functions supported.
849 * Returns a bitmask corresponding to all supported versions.
853 mono_arch_cpu_enumerate_simd_versions (void)
855 int eax, ebx, ecx, edx;
856 guint32 sse_opts = 0;
859 /* The cpuid function allocates from the global codeman */
862 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
864 sse_opts |= SIMD_VERSION_SSE1;
866 sse_opts |= SIMD_VERSION_SSE2;
868 sse_opts |= SIMD_VERSION_SSE3;
870 sse_opts |= SIMD_VERSION_SSSE3;
872 sse_opts |= SIMD_VERSION_SSE41;
874 sse_opts |= SIMD_VERSION_SSE42;
877 /* Yes, all this needs to be done to check for sse4a.
878 See: "Amd: CPUID Specification"
880 if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
881 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
882 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
883 cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
885 sse_opts |= SIMD_VERSION_SSE4a;
894 * Determine whenever the trap whose info is in SIGINFO is caused by
898 mono_arch_is_int_overflow (void *sigctx, void *info)
903 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
905 ip = (guint8*)ctx.eip;
907 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
911 switch (x86_modrm_rm (ip [1])) {
931 g_assert_not_reached ();
943 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
948 for (i = 0; i < cfg->num_varinfo; i++) {
949 MonoInst *ins = cfg->varinfo [i];
950 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
953 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
956 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
957 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
960 /* we dont allocate I1 to registers because there is no simply way to sign extend
961 * 8bit quantities in caller saved registers on x86 */
962 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
963 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
964 g_assert (i == vmv->idx);
965 vars = g_list_prepend (vars, vmv);
969 vars = mono_varlist_sort (cfg, vars, 0);
975 mono_arch_get_global_int_regs (MonoCompile *cfg)
979 /* we can use 3 registers for global allocation */
980 regs = g_list_prepend (regs, (gpointer)X86_EBX);
981 regs = g_list_prepend (regs, (gpointer)X86_ESI);
982 regs = g_list_prepend (regs, (gpointer)X86_EDI);
988 * mono_arch_regalloc_cost:
990 * Return the cost, in number of memory references, of the action of
991 * allocating the variable VMV into a register during global register
995 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
997 MonoInst *ins = cfg->varinfo [vmv->idx];
999 if (cfg->method->save_lmf)
1000 /* The register is already saved */
1001 return (ins->opcode == OP_ARG) ? 1 : 0;
1003 /* push+pop+possible load if it is an argument */
1004 return (ins->opcode == OP_ARG) ? 3 : 2;
1008 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
1010 static int inited = FALSE;
1011 static int count = 0;
1013 if (cfg->arch.need_stack_frame_inited) {
1014 g_assert (cfg->arch.need_stack_frame == flag);
1018 cfg->arch.need_stack_frame = flag;
1019 cfg->arch.need_stack_frame_inited = TRUE;
1025 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
1030 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
1034 needs_stack_frame (MonoCompile *cfg)
1036 MonoMethodSignature *sig;
1037 MonoMethodHeader *header;
1038 gboolean result = FALSE;
1040 #if defined(__APPLE__)
1041 /*OSX requires stack frame code to have the correct alignment. */
1045 if (cfg->arch.need_stack_frame_inited)
1046 return cfg->arch.need_stack_frame;
1048 header = cfg->header;
1049 sig = mono_method_signature (cfg->method);
1051 if (cfg->disable_omit_fp)
1053 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1055 else if (cfg->method->save_lmf)
1057 else if (cfg->stack_offset)
1059 else if (cfg->param_area)
1061 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1063 else if (header->num_clauses)
1065 else if (sig->param_count + sig->hasthis)
1067 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1069 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1070 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1073 set_needs_stack_frame (cfg, result);
1075 return cfg->arch.need_stack_frame;
1079 * Set var information according to the calling convention. X86 version.
1080 * The locals var stuff should most likely be split in another method.
1083 mono_arch_allocate_vars (MonoCompile *cfg)
1085 MonoMethodSignature *sig;
1086 MonoMethodHeader *header;
1088 guint32 locals_stack_size, locals_stack_align;
1093 header = cfg->header;
1094 sig = mono_method_signature (cfg->method);
1096 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1098 cfg->frame_reg = X86_EBP;
1101 /* Reserve space to save LMF and caller saved registers */
1103 if (cfg->method->save_lmf) {
1104 offset += sizeof (MonoLMF);
1106 if (cfg->used_int_regs & (1 << X86_EBX)) {
1110 if (cfg->used_int_regs & (1 << X86_EDI)) {
1114 if (cfg->used_int_regs & (1 << X86_ESI)) {
1119 switch (cinfo->ret.storage) {
1120 case ArgValuetypeInReg:
1121 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1123 cfg->ret->opcode = OP_REGOFFSET;
1124 cfg->ret->inst_basereg = X86_EBP;
1125 cfg->ret->inst_offset = - offset;
1131 /* Allocate locals */
1132 offsets = mono_allocate_stack_slots (cfg, &locals_stack_size, &locals_stack_align);
1133 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1134 char *mname = mono_method_full_name (cfg->method, TRUE);
1135 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1136 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1140 if (locals_stack_align) {
1141 offset += (locals_stack_align - 1);
1142 offset &= ~(locals_stack_align - 1);
1144 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1145 cfg->locals_max_stack_offset = - offset;
1147 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1148 * have locals larger than 8 bytes we need to make sure that
1149 * they have the appropriate offset.
1151 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1152 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1153 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1154 if (offsets [i] != -1) {
1155 MonoInst *inst = cfg->varinfo [i];
1156 inst->opcode = OP_REGOFFSET;
1157 inst->inst_basereg = X86_EBP;
1158 inst->inst_offset = - (offset + offsets [i]);
1159 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1162 offset += locals_stack_size;
1166 * Allocate arguments+return value
1169 switch (cinfo->ret.storage) {
1171 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1173 * In the new IR, the cfg->vret_addr variable represents the
1174 * vtype return value.
1176 cfg->vret_addr->opcode = OP_REGOFFSET;
1177 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1178 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1179 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1180 printf ("vret_addr =");
1181 mono_print_ins (cfg->vret_addr);
1184 cfg->ret->opcode = OP_REGOFFSET;
1185 cfg->ret->inst_basereg = X86_EBP;
1186 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1189 case ArgValuetypeInReg:
1192 cfg->ret->opcode = OP_REGVAR;
1193 cfg->ret->inst_c0 = cinfo->ret.reg;
1194 cfg->ret->dreg = cinfo->ret.reg;
1197 case ArgOnFloatFpStack:
1198 case ArgOnDoubleFpStack:
1201 g_assert_not_reached ();
1204 if (sig->call_convention == MONO_CALL_VARARG) {
1205 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1206 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1209 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1210 ArgInfo *ainfo = &cinfo->args [i];
1211 inst = cfg->args [i];
1212 if (inst->opcode != OP_REGVAR) {
1213 inst->opcode = OP_REGOFFSET;
1214 inst->inst_basereg = X86_EBP;
1216 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1219 cfg->stack_offset = offset;
1223 mono_arch_create_vars (MonoCompile *cfg)
1225 MonoMethodSignature *sig;
1228 sig = mono_method_signature (cfg->method);
1230 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1232 if (cinfo->ret.storage == ArgValuetypeInReg)
1233 cfg->ret_var_is_local = TRUE;
1234 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1235 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1240 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1241 * so we try to do it just once when we have multiple fp arguments in a row.
1242 * We don't use this mechanism generally because for int arguments the generated code
1243 * is slightly bigger and new generation cpus optimize away the dependency chains
1244 * created by push instructions on the esp value.
1245 * fp_arg_setup is the first argument in the execution sequence where the esp register
1248 static G_GNUC_UNUSED int
1249 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1254 for (; start_arg < sig->param_count; ++start_arg) {
1255 t = mini_type_get_underlying_type (NULL, sig->params [start_arg]);
1256 if (!t->byref && t->type == MONO_TYPE_R8) {
1257 fp_space += sizeof (double);
1258 *fp_arg_setup = start_arg;
1267 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1269 MonoMethodSignature *tmp_sig;
1271 /* FIXME: Add support for signature tokens to AOT */
1272 cfg->disable_aot = TRUE;
1275 * mono_ArgIterator_Setup assumes the signature cookie is
1276 * passed first and all the arguments which were before it are
1277 * passed on the stack after the signature. So compensate by
1278 * passing a different signature.
1280 tmp_sig = mono_metadata_signature_dup (call->signature);
1281 tmp_sig->param_count -= call->signature->sentinelpos;
1282 tmp_sig->sentinelpos = 0;
1283 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1285 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1290 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1295 LLVMCallInfo *linfo;
1298 n = sig->param_count + sig->hasthis;
1300 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1302 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1305 * LLVM always uses the native ABI while we use our own ABI, the
1306 * only difference is the handling of vtypes:
1307 * - we only pass/receive them in registers in some cases, and only
1308 * in 1 or 2 integer registers.
1310 if (cinfo->ret.storage == ArgValuetypeInReg) {
1312 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1313 cfg->disable_llvm = TRUE;
1317 cfg->exception_message = g_strdup ("vtype ret in call");
1318 cfg->disable_llvm = TRUE;
1320 linfo->ret.storage = LLVMArgVtypeInReg;
1321 for (j = 0; j < 2; ++j)
1322 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1326 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1327 /* Vtype returned using a hidden argument */
1328 linfo->ret.storage = LLVMArgVtypeRetAddr;
1329 linfo->vret_arg_index = cinfo->vret_arg_index;
1332 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != ArgInIReg) {
1334 cfg->exception_message = g_strdup ("vtype ret in call");
1335 cfg->disable_llvm = TRUE;
1338 for (i = 0; i < n; ++i) {
1339 ainfo = cinfo->args + i;
1341 if (i >= sig->hasthis)
1342 t = sig->params [i - sig->hasthis];
1344 t = &mono_defaults.int_class->byval_arg;
1346 linfo->args [i].storage = LLVMArgNone;
1348 switch (ainfo->storage) {
1350 linfo->args [i].storage = LLVMArgInIReg;
1352 case ArgInDoubleSSEReg:
1353 case ArgInFloatSSEReg:
1354 linfo->args [i].storage = LLVMArgInFPReg;
1357 if (MONO_TYPE_ISSTRUCT (t)) {
1358 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1359 /* LLVM seems to allocate argument space for empty structures too */
1360 linfo->args [i].storage = LLVMArgNone;
1362 linfo->args [i].storage = LLVMArgVtypeByVal;
1364 linfo->args [i].storage = LLVMArgInIReg;
1366 if (t->type == MONO_TYPE_R4)
1367 linfo->args [i].storage = LLVMArgInFPReg;
1368 else if (t->type == MONO_TYPE_R8)
1369 linfo->args [i].storage = LLVMArgInFPReg;
1373 case ArgValuetypeInReg:
1375 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1376 cfg->disable_llvm = TRUE;
1380 cfg->exception_message = g_strdup ("vtype arg");
1381 cfg->disable_llvm = TRUE;
1383 linfo->args [i].storage = LLVMArgVtypeInReg;
1384 for (j = 0; j < 2; ++j)
1385 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1389 cfg->exception_message = g_strdup ("ainfo->storage");
1390 cfg->disable_llvm = TRUE;
1400 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1403 MonoMethodSignature *sig;
1406 int sentinelpos = 0;
1408 sig = call->signature;
1409 n = sig->param_count + sig->hasthis;
1411 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1413 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1414 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1416 if (cinfo->need_stack_align) {
1417 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1418 arg->dreg = X86_ESP;
1419 arg->sreg1 = X86_ESP;
1420 arg->inst_imm = cinfo->stack_align_amount;
1421 MONO_ADD_INS (cfg->cbb, arg);
1424 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1425 if (cinfo->ret.storage == ArgValuetypeInReg) {
1427 * Tell the JIT to use a more efficient calling convention: call using
1428 * OP_CALL, compute the result location after the call, and save the
1431 call->vret_in_reg = TRUE;
1433 NULLIFY_INS (call->vret_var);
1437 /* Handle the case where there are no implicit arguments */
1438 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1439 emit_sig_cookie (cfg, call, cinfo);
1442 /* Arguments are pushed in the reverse order */
1443 for (i = n - 1; i >= 0; i --) {
1444 ArgInfo *ainfo = cinfo->args + i;
1447 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1448 /* Push the vret arg before the first argument */
1450 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1451 vtarg->type = STACK_MP;
1452 vtarg->sreg1 = call->vret_var->dreg;
1453 MONO_ADD_INS (cfg->cbb, vtarg);
1456 if (i >= sig->hasthis)
1457 t = sig->params [i - sig->hasthis];
1459 t = &mono_defaults.int_class->byval_arg;
1460 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1462 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1464 in = call->args [i];
1465 arg->cil_code = in->cil_code;
1466 arg->sreg1 = in->dreg;
1467 arg->type = in->type;
1469 g_assert (in->dreg != -1);
1471 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1475 g_assert (in->klass);
1477 if (t->type == MONO_TYPE_TYPEDBYREF) {
1478 size = sizeof (MonoTypedRef);
1479 align = sizeof (gpointer);
1482 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1486 arg->opcode = OP_OUTARG_VT;
1487 arg->sreg1 = in->dreg;
1488 arg->klass = in->klass;
1489 arg->backend.size = size;
1491 MONO_ADD_INS (cfg->cbb, arg);
1495 switch (ainfo->storage) {
1497 arg->opcode = OP_X86_PUSH;
1499 if (t->type == MONO_TYPE_R4) {
1500 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1501 arg->opcode = OP_STORER4_MEMBASE_REG;
1502 arg->inst_destbasereg = X86_ESP;
1503 arg->inst_offset = 0;
1504 } else if (t->type == MONO_TYPE_R8) {
1505 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1506 arg->opcode = OP_STORER8_MEMBASE_REG;
1507 arg->inst_destbasereg = X86_ESP;
1508 arg->inst_offset = 0;
1509 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1511 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1516 g_assert_not_reached ();
1519 MONO_ADD_INS (cfg->cbb, arg);
1522 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1523 /* Emit the signature cookie just before the implicit arguments */
1524 emit_sig_cookie (cfg, call, cinfo);
1528 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1531 if (cinfo->ret.storage == ArgValuetypeInReg) {
1534 else if (cinfo->ret.storage == ArgInIReg) {
1536 /* The return address is passed in a register */
1537 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1538 vtarg->sreg1 = call->inst.dreg;
1539 vtarg->dreg = mono_alloc_ireg (cfg);
1540 MONO_ADD_INS (cfg->cbb, vtarg);
1542 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1543 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1545 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1546 vtarg->type = STACK_MP;
1547 vtarg->sreg1 = call->vret_var->dreg;
1548 MONO_ADD_INS (cfg->cbb, vtarg);
1551 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
1552 if (cinfo->ret.storage != ArgValuetypeInReg)
1553 cinfo->stack_usage -= 4;
1556 call->stack_usage = cinfo->stack_usage;
1560 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1563 int size = ins->backend.size;
1566 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1567 arg->sreg1 = src->dreg;
1569 MONO_ADD_INS (cfg->cbb, arg);
1570 } else if (size <= 20) {
1571 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1572 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1574 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1575 arg->inst_basereg = src->dreg;
1576 arg->inst_offset = 0;
1577 arg->inst_imm = size;
1579 MONO_ADD_INS (cfg->cbb, arg);
1584 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1586 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1589 if (ret->type == MONO_TYPE_R4) {
1590 if (COMPILE_LLVM (cfg))
1591 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1594 } else if (ret->type == MONO_TYPE_R8) {
1595 if (COMPILE_LLVM (cfg))
1596 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1599 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1600 if (COMPILE_LLVM (cfg))
1601 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1603 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1604 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1610 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1614 * Allow tracing to work with this interface (with an optional argument)
1617 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1621 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1622 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1624 /* if some args are passed in registers, we need to save them here */
1625 x86_push_reg (code, X86_EBP);
1627 if (cfg->compile_aot) {
1628 x86_push_imm (code, cfg->method);
1629 x86_mov_reg_imm (code, X86_EAX, func);
1630 x86_call_reg (code, X86_EAX);
1632 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1633 x86_push_imm (code, cfg->method);
1634 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1635 x86_call_code (code, 0);
1637 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1651 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1654 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1655 MonoMethod *method = cfg->method;
1656 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1658 switch (ret_type->type) {
1659 case MONO_TYPE_VOID:
1660 /* special case string .ctor icall */
1661 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1662 save_mode = SAVE_EAX;
1663 stack_usage = enable_arguments ? 8 : 4;
1665 save_mode = SAVE_NONE;
1669 save_mode = SAVE_EAX_EDX;
1670 stack_usage = enable_arguments ? 16 : 8;
1674 save_mode = SAVE_FP;
1675 stack_usage = enable_arguments ? 16 : 8;
1677 case MONO_TYPE_GENERICINST:
1678 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1679 save_mode = SAVE_EAX;
1680 stack_usage = enable_arguments ? 8 : 4;
1684 case MONO_TYPE_VALUETYPE:
1685 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1686 save_mode = SAVE_STRUCT;
1687 stack_usage = enable_arguments ? 4 : 0;
1690 save_mode = SAVE_EAX;
1691 stack_usage = enable_arguments ? 8 : 4;
1695 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1697 switch (save_mode) {
1699 x86_push_reg (code, X86_EDX);
1700 x86_push_reg (code, X86_EAX);
1701 if (enable_arguments) {
1702 x86_push_reg (code, X86_EDX);
1703 x86_push_reg (code, X86_EAX);
1708 x86_push_reg (code, X86_EAX);
1709 if (enable_arguments) {
1710 x86_push_reg (code, X86_EAX);
1715 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1716 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1717 if (enable_arguments) {
1718 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1719 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1724 if (enable_arguments) {
1725 x86_push_membase (code, X86_EBP, 8);
1734 if (cfg->compile_aot) {
1735 x86_push_imm (code, method);
1736 x86_mov_reg_imm (code, X86_EAX, func);
1737 x86_call_reg (code, X86_EAX);
1739 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1740 x86_push_imm (code, method);
1741 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1742 x86_call_code (code, 0);
1745 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1747 switch (save_mode) {
1749 x86_pop_reg (code, X86_EAX);
1750 x86_pop_reg (code, X86_EDX);
1753 x86_pop_reg (code, X86_EAX);
1756 x86_fld_membase (code, X86_ESP, 0, TRUE);
1757 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1764 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1769 #define EMIT_COND_BRANCH(ins,cond,sign) \
1770 if (ins->inst_true_bb->native_offset) { \
1771 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1773 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1774 if ((cfg->opt & MONO_OPT_BRANCH) && \
1775 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1776 x86_branch8 (code, cond, 0, sign); \
1778 x86_branch32 (code, cond, 0, sign); \
1782 * Emit an exception if condition is fail and
1783 * if possible do a directly branch to target
1785 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1787 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1788 if (tins == NULL) { \
1789 mono_add_patch_info (cfg, code - cfg->native_code, \
1790 MONO_PATCH_INFO_EXC, exc_name); \
1791 x86_branch32 (code, cond, 0, signed); \
1793 EMIT_COND_BRANCH (tins, cond, signed); \
1797 #define EMIT_FPCOMPARE(code) do { \
1798 x86_fcompp (code); \
1799 x86_fnstsw (code); \
1804 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1806 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1807 x86_call_code (code, 0);
1812 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1815 * mono_peephole_pass_1:
1817 * Perform peephole opts which should/can be performed before local regalloc
1820 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1824 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1825 MonoInst *last_ins = ins->prev;
1827 switch (ins->opcode) {
1830 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1832 * X86_LEA is like ADD, but doesn't have the
1833 * sreg1==dreg restriction.
1835 ins->opcode = OP_X86_LEA_MEMBASE;
1836 ins->inst_basereg = ins->sreg1;
1837 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1838 ins->opcode = OP_X86_INC_REG;
1842 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1843 ins->opcode = OP_X86_LEA_MEMBASE;
1844 ins->inst_basereg = ins->sreg1;
1845 ins->inst_imm = -ins->inst_imm;
1846 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1847 ins->opcode = OP_X86_DEC_REG;
1849 case OP_COMPARE_IMM:
1850 case OP_ICOMPARE_IMM:
1851 /* OP_COMPARE_IMM (reg, 0)
1853 * OP_X86_TEST_NULL (reg)
1856 ins->opcode = OP_X86_TEST_NULL;
1858 case OP_X86_COMPARE_MEMBASE_IMM:
1860 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1861 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1863 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1864 * OP_COMPARE_IMM reg, imm
1866 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1868 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1869 ins->inst_basereg == last_ins->inst_destbasereg &&
1870 ins->inst_offset == last_ins->inst_offset) {
1871 ins->opcode = OP_COMPARE_IMM;
1872 ins->sreg1 = last_ins->sreg1;
1874 /* check if we can remove cmp reg,0 with test null */
1876 ins->opcode = OP_X86_TEST_NULL;
1880 case OP_X86_PUSH_MEMBASE:
1881 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1882 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1883 ins->inst_basereg == last_ins->inst_destbasereg &&
1884 ins->inst_offset == last_ins->inst_offset) {
1885 ins->opcode = OP_X86_PUSH;
1886 ins->sreg1 = last_ins->sreg1;
1891 mono_peephole_ins (bb, ins);
1896 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1900 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1901 switch (ins->opcode) {
1903 /* reg = 0 -> XOR (reg, reg) */
1904 /* XOR sets cflags on x86, so we cant do it always */
1905 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
1908 ins->opcode = OP_IXOR;
1909 ins->sreg1 = ins->dreg;
1910 ins->sreg2 = ins->dreg;
1913 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
1914 * since it takes 3 bytes instead of 7.
1916 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
1917 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1918 ins2->opcode = OP_STORE_MEMBASE_REG;
1919 ins2->sreg1 = ins->dreg;
1921 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1922 ins2->opcode = OP_STOREI4_MEMBASE_REG;
1923 ins2->sreg1 = ins->dreg;
1925 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
1926 /* Continue iteration */
1935 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1936 ins->opcode = OP_X86_INC_REG;
1940 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1941 ins->opcode = OP_X86_DEC_REG;
1945 mono_peephole_ins (bb, ins);
1950 * mono_arch_lowering_pass:
1952 * Converts complex opcodes into simpler ones so that each IR instruction
1953 * corresponds to one machine instruction.
1956 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1958 MonoInst *ins, *next;
1961 * FIXME: Need to add more instructions, but the current machine
1962 * description can't model some parts of the composite instructions like
1965 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
1966 switch (ins->opcode) {
1969 case OP_IDIV_UN_IMM:
1970 case OP_IREM_UN_IMM:
1972 * Keep the cases where we could generated optimized code, otherwise convert
1973 * to the non-imm variant.
1975 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
1977 mono_decompose_op_imm (cfg, bb, ins);
1984 bb->max_vreg = cfg->next_vreg;
1988 branch_cc_table [] = {
1989 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1990 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1991 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
1994 /* Maps CMP_... constants to X86_CC_... constants */
1997 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
1998 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2002 cc_signed_table [] = {
2003 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2004 FALSE, FALSE, FALSE, FALSE
2007 static unsigned char*
2008 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2010 #define XMM_TEMP_REG 0
2011 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2012 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2013 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2014 /* optimize by assigning a local var for this use so we avoid
2015 * the stack manipulations */
2016 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2017 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2018 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2019 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2020 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2022 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2024 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2027 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2028 x86_fnstcw_membase(code, X86_ESP, 0);
2029 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2030 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2031 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2032 x86_fldcw_membase (code, X86_ESP, 2);
2034 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2035 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2036 x86_pop_reg (code, dreg);
2037 /* FIXME: need the high register
2038 * x86_pop_reg (code, dreg_high);
2041 x86_push_reg (code, X86_EAX); // SP = SP - 4
2042 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2043 x86_pop_reg (code, dreg);
2045 x86_fldcw_membase (code, X86_ESP, 0);
2046 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2049 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2051 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2055 static unsigned char*
2056 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2058 int sreg = tree->sreg1;
2059 int need_touch = FALSE;
2061 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2070 * If requested stack size is larger than one page,
2071 * perform stack-touch operation
2074 * Generate stack probe code.
2075 * Under Windows, it is necessary to allocate one page at a time,
2076 * "touching" stack after each successful sub-allocation. This is
2077 * because of the way stack growth is implemented - there is a
2078 * guard page before the lowest stack page that is currently commited.
2079 * Stack normally grows sequentially so OS traps access to the
2080 * guard page and commits more pages when needed.
2082 x86_test_reg_imm (code, sreg, ~0xFFF);
2083 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2085 br[2] = code; /* loop */
2086 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2087 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2090 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2091 * that follows only initializes the last part of the area.
2093 /* Same as the init code below with size==0x1000 */
2094 if (tree->flags & MONO_INST_INIT) {
2095 x86_push_reg (code, X86_EAX);
2096 x86_push_reg (code, X86_ECX);
2097 x86_push_reg (code, X86_EDI);
2098 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2099 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2100 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2102 x86_prefix (code, X86_REP_PREFIX);
2104 x86_pop_reg (code, X86_EDI);
2105 x86_pop_reg (code, X86_ECX);
2106 x86_pop_reg (code, X86_EAX);
2109 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2110 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2111 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2112 x86_patch (br[3], br[2]);
2113 x86_test_reg_reg (code, sreg, sreg);
2114 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2115 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2117 br[1] = code; x86_jump8 (code, 0);
2119 x86_patch (br[0], code);
2120 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2121 x86_patch (br[1], code);
2122 x86_patch (br[4], code);
2125 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2127 if (tree->flags & MONO_INST_INIT) {
2129 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2130 x86_push_reg (code, X86_EAX);
2133 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2134 x86_push_reg (code, X86_ECX);
2137 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2138 x86_push_reg (code, X86_EDI);
2142 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2143 if (sreg != X86_ECX)
2144 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2145 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2147 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2149 x86_prefix (code, X86_REP_PREFIX);
2152 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2153 x86_pop_reg (code, X86_EDI);
2154 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2155 x86_pop_reg (code, X86_ECX);
2156 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2157 x86_pop_reg (code, X86_EAX);
2164 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2166 /* Move return value to the target register */
2167 switch (ins->opcode) {
2170 case OP_CALL_MEMBASE:
2171 if (ins->dreg != X86_EAX)
2172 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2182 mono_x86_have_tls_get (void)
2185 guint32 *ins = (guint32*)pthread_getspecific;
2187 * We're looking for these two instructions:
2189 * mov 0x4(%esp),%eax
2190 * mov %gs:0x48(,%eax,4),%eax
2192 return ins [0] == 0x0424448b && ins [1] == 0x85048b65 && ins [2] == 0x00000048;
2199 * mono_x86_emit_tls_get:
2200 * @code: buffer to store code to
2201 * @dreg: hard register where to place the result
2202 * @tls_offset: offset info
2204 * mono_x86_emit_tls_get emits in @code the native code that puts in
2205 * the dreg register the item in the thread local storage identified
2208 * Returns: a pointer to the end of the stored code
2211 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2213 #if defined(__APPLE__)
2214 x86_prefix (code, X86_GS_PREFIX);
2215 x86_mov_reg_mem (code, dreg, 0x48 + tls_offset * 4, 4);
2216 #elif defined(TARGET_WIN32)
2218 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2219 * Journal and/or a disassembly of the TlsGet () function.
2221 g_assert (tls_offset < 64);
2222 x86_prefix (code, X86_FS_PREFIX);
2223 x86_mov_reg_mem (code, dreg, 0x18, 4);
2224 /* Dunno what this does but TlsGetValue () contains it */
2225 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
2226 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2228 if (optimize_for_xen) {
2229 x86_prefix (code, X86_GS_PREFIX);
2230 x86_mov_reg_mem (code, dreg, 0, 4);
2231 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2233 x86_prefix (code, X86_GS_PREFIX);
2234 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2241 * emit_load_volatile_arguments:
2243 * Load volatile arguments from the stack to the original input registers.
2244 * Required before a tail call.
2247 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2249 MonoMethod *method = cfg->method;
2250 MonoMethodSignature *sig;
2255 /* FIXME: Generate intermediate code instead */
2257 sig = mono_method_signature (method);
2259 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2261 /* This is the opposite of the code in emit_prolog */
2263 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2264 ArgInfo *ainfo = cinfo->args + i;
2266 inst = cfg->args [i];
2268 if (sig->hasthis && (i == 0))
2269 arg_type = &mono_defaults.object_class->byval_arg;
2271 arg_type = sig->params [i - sig->hasthis];
2274 * On x86, the arguments are either in their original stack locations, or in
2277 if (inst->opcode == OP_REGVAR) {
2278 g_assert (ainfo->storage == ArgOnStack);
2280 x86_mov_membase_reg (code, X86_EBP, inst->inst_offset, inst->dreg, 4);
2287 #define REAL_PRINT_REG(text,reg) \
2288 mono_assert (reg >= 0); \
2289 x86_push_reg (code, X86_EAX); \
2290 x86_push_reg (code, X86_EDX); \
2291 x86_push_reg (code, X86_ECX); \
2292 x86_push_reg (code, reg); \
2293 x86_push_imm (code, reg); \
2294 x86_push_imm (code, text " %d %p\n"); \
2295 x86_mov_reg_imm (code, X86_EAX, printf); \
2296 x86_call_reg (code, X86_EAX); \
2297 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2298 x86_pop_reg (code, X86_ECX); \
2299 x86_pop_reg (code, X86_EDX); \
2300 x86_pop_reg (code, X86_EAX);
2302 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2303 #ifdef __native__client_codegen__
2304 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2307 /* benchmark and set based on cpu */
2308 #define LOOP_ALIGNMENT 8
2309 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2313 #if defined(__native_client__) || defined(__native_client_codegen__)
2317 #ifdef __native_client_gc__
2318 __nacl_suspend_thread_if_needed();
2324 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2329 guint8 *code = cfg->native_code + cfg->code_len;
2332 if (cfg->opt & MONO_OPT_LOOP) {
2333 int pad, align = LOOP_ALIGNMENT;
2334 /* set alignment depending on cpu */
2335 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2337 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2338 x86_padding (code, pad);
2339 cfg->code_len += pad;
2340 bb->native_offset = cfg->code_len;
2343 #ifdef __native_client_codegen__
2345 /* For Native Client, all indirect call/jump targets must be */
2346 /* 32-byte aligned. Exception handler blocks are jumped to */
2347 /* indirectly as well. */
2348 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2349 (bb->flags & BB_EXCEPTION_HANDLER);
2351 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2352 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2353 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2354 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2355 cfg->code_len += pad;
2356 bb->native_offset = cfg->code_len;
2359 #endif /* __native_client_codegen__ */
2360 if (cfg->verbose_level > 2)
2361 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2363 cpos = bb->max_offset;
2365 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2366 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2367 g_assert (!cfg->compile_aot);
2370 cov->data [bb->dfn].cil_code = bb->cil_code;
2371 /* this is not thread save, but good enough */
2372 x86_inc_mem (code, &cov->data [bb->dfn].count);
2375 offset = code - cfg->native_code;
2377 mono_debug_open_block (cfg, bb, offset);
2379 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2380 x86_breakpoint (code);
2382 MONO_BB_FOR_EACH_INS (bb, ins) {
2383 offset = code - cfg->native_code;
2385 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2387 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2389 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2390 cfg->code_size *= 2;
2391 cfg->native_code = mono_realloc_native_code(cfg);
2392 code = cfg->native_code + offset;
2393 mono_jit_stats.code_reallocs++;
2396 if (cfg->debug_info)
2397 mono_debug_record_line_number (cfg, ins, offset);
2399 switch (ins->opcode) {
2401 x86_mul_reg (code, ins->sreg2, TRUE);
2404 x86_mul_reg (code, ins->sreg2, FALSE);
2406 case OP_X86_SETEQ_MEMBASE:
2407 case OP_X86_SETNE_MEMBASE:
2408 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2409 ins->inst_basereg, ins->inst_offset, TRUE);
2411 case OP_STOREI1_MEMBASE_IMM:
2412 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2414 case OP_STOREI2_MEMBASE_IMM:
2415 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2417 case OP_STORE_MEMBASE_IMM:
2418 case OP_STOREI4_MEMBASE_IMM:
2419 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2421 case OP_STOREI1_MEMBASE_REG:
2422 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2424 case OP_STOREI2_MEMBASE_REG:
2425 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2427 case OP_STORE_MEMBASE_REG:
2428 case OP_STOREI4_MEMBASE_REG:
2429 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2431 case OP_STORE_MEM_IMM:
2432 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2435 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2439 /* These are created by the cprop pass so they use inst_imm as the source */
2440 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2443 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2446 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2448 case OP_LOAD_MEMBASE:
2449 case OP_LOADI4_MEMBASE:
2450 case OP_LOADU4_MEMBASE:
2451 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2453 case OP_LOADU1_MEMBASE:
2454 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2456 case OP_LOADI1_MEMBASE:
2457 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2459 case OP_LOADU2_MEMBASE:
2460 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2462 case OP_LOADI2_MEMBASE:
2463 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2465 case OP_ICONV_TO_I1:
2467 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2469 case OP_ICONV_TO_I2:
2471 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2473 case OP_ICONV_TO_U1:
2474 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2476 case OP_ICONV_TO_U2:
2477 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2481 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2483 case OP_COMPARE_IMM:
2484 case OP_ICOMPARE_IMM:
2485 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2487 case OP_X86_COMPARE_MEMBASE_REG:
2488 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2490 case OP_X86_COMPARE_MEMBASE_IMM:
2491 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2493 case OP_X86_COMPARE_MEMBASE8_IMM:
2494 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2496 case OP_X86_COMPARE_REG_MEMBASE:
2497 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2499 case OP_X86_COMPARE_MEM_IMM:
2500 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2502 case OP_X86_TEST_NULL:
2503 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2505 case OP_X86_ADD_MEMBASE_IMM:
2506 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2508 case OP_X86_ADD_REG_MEMBASE:
2509 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2511 case OP_X86_SUB_MEMBASE_IMM:
2512 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2514 case OP_X86_SUB_REG_MEMBASE:
2515 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2517 case OP_X86_AND_MEMBASE_IMM:
2518 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2520 case OP_X86_OR_MEMBASE_IMM:
2521 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2523 case OP_X86_XOR_MEMBASE_IMM:
2524 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2526 case OP_X86_ADD_MEMBASE_REG:
2527 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2529 case OP_X86_SUB_MEMBASE_REG:
2530 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2532 case OP_X86_AND_MEMBASE_REG:
2533 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2535 case OP_X86_OR_MEMBASE_REG:
2536 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2538 case OP_X86_XOR_MEMBASE_REG:
2539 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2541 case OP_X86_INC_MEMBASE:
2542 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2544 case OP_X86_INC_REG:
2545 x86_inc_reg (code, ins->dreg);
2547 case OP_X86_DEC_MEMBASE:
2548 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2550 case OP_X86_DEC_REG:
2551 x86_dec_reg (code, ins->dreg);
2553 case OP_X86_MUL_REG_MEMBASE:
2554 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2556 case OP_X86_AND_REG_MEMBASE:
2557 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2559 case OP_X86_OR_REG_MEMBASE:
2560 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2562 case OP_X86_XOR_REG_MEMBASE:
2563 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2566 x86_breakpoint (code);
2568 case OP_RELAXED_NOP:
2569 x86_prefix (code, X86_REP_PREFIX);
2577 case OP_DUMMY_STORE:
2578 case OP_NOT_REACHED:
2581 case OP_SEQ_POINT: {
2584 if (cfg->compile_aot)
2588 * Read from the single stepping trigger page. This will cause a
2589 * SIGSEGV when single stepping is enabled.
2590 * We do this _before_ the breakpoint, so single stepping after
2591 * a breakpoint is hit will step to the next IL offset.
2593 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2594 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2596 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2599 * A placeholder for a possible breakpoint inserted by
2600 * mono_arch_set_breakpoint ().
2602 for (i = 0; i < 6; ++i)
2609 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2613 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2618 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2622 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2627 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2631 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2636 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2640 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2643 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2647 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2652 * The code is the same for div/rem, the allocator will allocate dreg
2653 * to RAX/RDX as appropriate.
2655 if (ins->sreg2 == X86_EDX) {
2656 /* cdq clobbers this */
2657 x86_push_reg (code, ins->sreg2);
2659 x86_div_membase (code, X86_ESP, 0, TRUE);
2660 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2663 x86_div_reg (code, ins->sreg2, TRUE);
2668 if (ins->sreg2 == X86_EDX) {
2669 x86_push_reg (code, ins->sreg2);
2670 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2671 x86_div_membase (code, X86_ESP, 0, FALSE);
2672 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2674 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2675 x86_div_reg (code, ins->sreg2, FALSE);
2679 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2681 x86_div_reg (code, ins->sreg2, TRUE);
2684 int power = mono_is_power_of_two (ins->inst_imm);
2686 g_assert (ins->sreg1 == X86_EAX);
2687 g_assert (ins->dreg == X86_EAX);
2688 g_assert (power >= 0);
2691 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2693 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2695 * If the divident is >= 0, this does not nothing. If it is positive, it
2696 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2698 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2699 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2700 } else if (power == 0) {
2701 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2703 /* Based on gcc code */
2705 /* Add compensation for negative dividents */
2707 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2708 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2709 /* Compute remainder */
2710 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2711 /* Remove compensation */
2712 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2717 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2721 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2724 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2728 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2731 g_assert (ins->sreg2 == X86_ECX);
2732 x86_shift_reg (code, X86_SHL, ins->dreg);
2735 g_assert (ins->sreg2 == X86_ECX);
2736 x86_shift_reg (code, X86_SAR, ins->dreg);
2740 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2743 case OP_ISHR_UN_IMM:
2744 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2747 g_assert (ins->sreg2 == X86_ECX);
2748 x86_shift_reg (code, X86_SHR, ins->dreg);
2752 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2755 guint8 *jump_to_end;
2757 /* handle shifts below 32 bits */
2758 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2759 x86_shift_reg (code, X86_SHL, ins->sreg1);
2761 x86_test_reg_imm (code, X86_ECX, 32);
2762 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2764 /* handle shift over 32 bit */
2765 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2766 x86_clear_reg (code, ins->sreg1);
2768 x86_patch (jump_to_end, code);
2772 guint8 *jump_to_end;
2774 /* handle shifts below 32 bits */
2775 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2776 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2778 x86_test_reg_imm (code, X86_ECX, 32);
2779 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2781 /* handle shifts over 31 bits */
2782 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2783 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2785 x86_patch (jump_to_end, code);
2789 guint8 *jump_to_end;
2791 /* handle shifts below 32 bits */
2792 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2793 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2795 x86_test_reg_imm (code, X86_ECX, 32);
2796 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2798 /* handle shifts over 31 bits */
2799 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2800 x86_clear_reg (code, ins->backend.reg3);
2802 x86_patch (jump_to_end, code);
2806 if (ins->inst_imm >= 32) {
2807 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2808 x86_clear_reg (code, ins->sreg1);
2809 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2811 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2812 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2816 if (ins->inst_imm >= 32) {
2817 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2818 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2819 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2821 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2822 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2825 case OP_LSHR_UN_IMM:
2826 if (ins->inst_imm >= 32) {
2827 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2828 x86_clear_reg (code, ins->backend.reg3);
2829 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2831 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2832 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
2836 x86_not_reg (code, ins->sreg1);
2839 x86_neg_reg (code, ins->sreg1);
2843 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2847 switch (ins->inst_imm) {
2851 if (ins->dreg != ins->sreg1)
2852 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2853 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2856 /* LEA r1, [r2 + r2*2] */
2857 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2860 /* LEA r1, [r2 + r2*4] */
2861 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2864 /* LEA r1, [r2 + r2*2] */
2866 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2867 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2870 /* LEA r1, [r2 + r2*8] */
2871 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2874 /* LEA r1, [r2 + r2*4] */
2876 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2877 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2880 /* LEA r1, [r2 + r2*2] */
2882 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2883 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2886 /* LEA r1, [r2 + r2*4] */
2887 /* LEA r1, [r1 + r1*4] */
2888 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2889 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2892 /* LEA r1, [r2 + r2*4] */
2894 /* LEA r1, [r1 + r1*4] */
2895 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2896 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2897 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2900 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2905 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2906 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2908 case OP_IMUL_OVF_UN: {
2909 /* the mul operation and the exception check should most likely be split */
2910 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2911 /*g_assert (ins->sreg2 == X86_EAX);
2912 g_assert (ins->dreg == X86_EAX);*/
2913 if (ins->sreg2 == X86_EAX) {
2914 non_eax_reg = ins->sreg1;
2915 } else if (ins->sreg1 == X86_EAX) {
2916 non_eax_reg = ins->sreg2;
2918 /* no need to save since we're going to store to it anyway */
2919 if (ins->dreg != X86_EAX) {
2921 x86_push_reg (code, X86_EAX);
2923 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
2924 non_eax_reg = ins->sreg2;
2926 if (ins->dreg == X86_EDX) {
2929 x86_push_reg (code, X86_EAX);
2931 } else if (ins->dreg != X86_EAX) {
2933 x86_push_reg (code, X86_EDX);
2935 x86_mul_reg (code, non_eax_reg, FALSE);
2936 /* save before the check since pop and mov don't change the flags */
2937 if (ins->dreg != X86_EAX)
2938 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2940 x86_pop_reg (code, X86_EDX);
2942 x86_pop_reg (code, X86_EAX);
2943 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2947 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
2950 g_assert_not_reached ();
2951 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2952 x86_mov_reg_imm (code, ins->dreg, 0);
2955 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2956 x86_mov_reg_imm (code, ins->dreg, 0);
2958 case OP_LOAD_GOTADDR:
2959 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
2960 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
2963 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
2964 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
2966 case OP_X86_PUSH_GOT_ENTRY:
2967 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
2968 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
2971 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2975 * Note: this 'frame destruction' logic is useful for tail calls, too.
2976 * Keep in sync with the code in emit_epilog.
2980 /* FIXME: no tracing support... */
2981 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2982 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
2983 /* reset offset to make max_len work */
2984 offset = code - cfg->native_code;
2986 g_assert (!cfg->method->save_lmf);
2988 code = emit_load_volatile_arguments (cfg, code);
2990 if (cfg->used_int_regs & (1 << X86_EBX))
2992 if (cfg->used_int_regs & (1 << X86_EDI))
2994 if (cfg->used_int_regs & (1 << X86_ESI))
2997 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
2999 if (cfg->used_int_regs & (1 << X86_ESI))
3000 x86_pop_reg (code, X86_ESI);
3001 if (cfg->used_int_regs & (1 << X86_EDI))
3002 x86_pop_reg (code, X86_EDI);
3003 if (cfg->used_int_regs & (1 << X86_EBX))
3004 x86_pop_reg (code, X86_EBX);
3006 /* restore ESP/EBP */
3008 offset = code - cfg->native_code;
3009 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3010 x86_jump32 (code, 0);
3012 cfg->disable_aot = TRUE;
3016 MonoCallInst *call = (MonoCallInst*)ins;
3019 /* FIXME: no tracing support... */
3020 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3021 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3022 /* reset offset to make max_len work */
3023 offset = code - cfg->native_code;
3025 g_assert (!cfg->method->save_lmf);
3027 //code = emit_load_volatile_arguments (cfg, code);
3029 /* restore callee saved registers */
3030 for (i = 0; i < X86_NREG; ++i)
3031 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3033 if (cfg->used_int_regs & (1 << X86_ESI)) {
3034 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3037 if (cfg->used_int_regs & (1 << X86_EDI)) {
3038 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3041 if (cfg->used_int_regs & (1 << X86_EBX)) {
3042 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3046 /* Copy arguments on the stack to our argument area */
3047 for (i = 0; i < call->stack_usage; i += 4) {
3048 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3049 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3052 /* restore ESP/EBP */
3054 offset = code - cfg->native_code;
3055 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3056 x86_jump32 (code, 0);
3058 cfg->disable_aot = TRUE;
3062 /* ensure ins->sreg1 is not NULL
3063 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3064 * cmp DWORD PTR [eax], 0
3066 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3069 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3070 x86_push_reg (code, hreg);
3071 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3072 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3073 x86_pop_reg (code, hreg);
3082 call = (MonoCallInst*)ins;
3083 if (ins->flags & MONO_INST_HAS_METHOD)
3084 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3086 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3087 ins->flags |= MONO_INST_GC_CALLSITE;
3088 ins->backend.pc_offset = code - cfg->native_code;
3089 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3090 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
3091 * bytes to pop, we want to use pops. GCC does this (note it won't happen
3092 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
3093 * smart enough to do that optimization yet
3095 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
3096 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
3097 * (most likely from locality benefits). People with other processors should
3098 * check on theirs to see what happens.
3100 if (call->stack_usage == 4) {
3101 /* we want to use registers that won't get used soon, so use
3102 * ecx, as eax will get allocated first. edx is used by long calls,
3103 * so we can't use that.
3106 x86_pop_reg (code, X86_ECX);
3108 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3111 code = emit_move_return_value (cfg, ins, code);
3117 case OP_VOIDCALL_REG:
3119 call = (MonoCallInst*)ins;
3120 x86_call_reg (code, ins->sreg1);
3121 ins->flags |= MONO_INST_GC_CALLSITE;
3122 ins->backend.pc_offset = code - cfg->native_code;
3123 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3124 if (call->stack_usage == 4)
3125 x86_pop_reg (code, X86_ECX);
3127 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3129 code = emit_move_return_value (cfg, ins, code);
3131 case OP_FCALL_MEMBASE:
3132 case OP_LCALL_MEMBASE:
3133 case OP_VCALL_MEMBASE:
3134 case OP_VCALL2_MEMBASE:
3135 case OP_VOIDCALL_MEMBASE:
3136 case OP_CALL_MEMBASE:
3137 call = (MonoCallInst*)ins;
3139 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3140 ins->flags |= MONO_INST_GC_CALLSITE;
3141 ins->backend.pc_offset = code - cfg->native_code;
3142 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3143 if (call->stack_usage == 4)
3144 x86_pop_reg (code, X86_ECX);
3146 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3148 code = emit_move_return_value (cfg, ins, code);
3151 x86_push_reg (code, ins->sreg1);
3153 case OP_X86_PUSH_IMM:
3154 x86_push_imm (code, ins->inst_imm);
3156 case OP_X86_PUSH_MEMBASE:
3157 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
3159 case OP_X86_PUSH_OBJ:
3160 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
3161 x86_push_reg (code, X86_EDI);
3162 x86_push_reg (code, X86_ESI);
3163 x86_push_reg (code, X86_ECX);
3164 if (ins->inst_offset)
3165 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
3167 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
3168 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
3169 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
3171 x86_prefix (code, X86_REP_PREFIX);
3173 x86_pop_reg (code, X86_ECX);
3174 x86_pop_reg (code, X86_ESI);
3175 x86_pop_reg (code, X86_EDI);
3178 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3180 case OP_X86_LEA_MEMBASE:
3181 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3184 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3187 /* keep alignment */
3188 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3189 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3190 code = mono_emit_stack_alloc (code, ins);
3191 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3193 case OP_LOCALLOC_IMM: {
3194 guint32 size = ins->inst_imm;
3195 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3197 if (ins->flags & MONO_INST_INIT) {
3198 /* FIXME: Optimize this */
3199 x86_mov_reg_imm (code, ins->dreg, size);
3200 ins->sreg1 = ins->dreg;
3202 code = mono_emit_stack_alloc (code, ins);
3203 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3205 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3206 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3211 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3212 x86_push_reg (code, ins->sreg1);
3213 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3214 (gpointer)"mono_arch_throw_exception");
3215 ins->flags |= MONO_INST_GC_CALLSITE;
3216 ins->backend.pc_offset = code - cfg->native_code;
3220 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3221 x86_push_reg (code, ins->sreg1);
3222 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3223 (gpointer)"mono_arch_rethrow_exception");
3224 ins->flags |= MONO_INST_GC_CALLSITE;
3225 ins->backend.pc_offset = code - cfg->native_code;
3228 case OP_CALL_HANDLER:
3229 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3230 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3231 x86_call_imm (code, 0);
3232 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3233 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3235 case OP_START_HANDLER: {
3236 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3237 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3240 case OP_ENDFINALLY: {
3241 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3242 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3246 case OP_ENDFILTER: {
3247 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3248 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3249 /* The local allocator will put the result into EAX */
3255 ins->inst_c0 = code - cfg->native_code;
3258 if (ins->inst_target_bb->native_offset) {
3259 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3261 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3262 if ((cfg->opt & MONO_OPT_BRANCH) &&
3263 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3264 x86_jump8 (code, 0);
3266 x86_jump32 (code, 0);
3270 x86_jump_reg (code, ins->sreg1);
3283 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3284 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3286 case OP_COND_EXC_EQ:
3287 case OP_COND_EXC_NE_UN:
3288 case OP_COND_EXC_LT:
3289 case OP_COND_EXC_LT_UN:
3290 case OP_COND_EXC_GT:
3291 case OP_COND_EXC_GT_UN:
3292 case OP_COND_EXC_GE:
3293 case OP_COND_EXC_GE_UN:
3294 case OP_COND_EXC_LE:
3295 case OP_COND_EXC_LE_UN:
3296 case OP_COND_EXC_IEQ:
3297 case OP_COND_EXC_INE_UN:
3298 case OP_COND_EXC_ILT:
3299 case OP_COND_EXC_ILT_UN:
3300 case OP_COND_EXC_IGT:
3301 case OP_COND_EXC_IGT_UN:
3302 case OP_COND_EXC_IGE:
3303 case OP_COND_EXC_IGE_UN:
3304 case OP_COND_EXC_ILE:
3305 case OP_COND_EXC_ILE_UN:
3306 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3308 case OP_COND_EXC_OV:
3309 case OP_COND_EXC_NO:
3311 case OP_COND_EXC_NC:
3312 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3314 case OP_COND_EXC_IOV:
3315 case OP_COND_EXC_INO:
3316 case OP_COND_EXC_IC:
3317 case OP_COND_EXC_INC:
3318 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3330 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3338 case OP_CMOV_INE_UN:
3339 case OP_CMOV_IGE_UN:
3340 case OP_CMOV_IGT_UN:
3341 case OP_CMOV_ILE_UN:
3342 case OP_CMOV_ILT_UN:
3343 g_assert (ins->dreg == ins->sreg1);
3344 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3347 /* floating point opcodes */
3349 double d = *(double *)ins->inst_p0;
3351 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3353 } else if (d == 1.0) {
3356 if (cfg->compile_aot) {
3357 guint32 *val = (guint32*)&d;
3358 x86_push_imm (code, val [1]);
3359 x86_push_imm (code, val [0]);
3360 x86_fld_membase (code, X86_ESP, 0, TRUE);
3361 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3364 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3365 x86_fld (code, NULL, TRUE);
3371 float f = *(float *)ins->inst_p0;
3373 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3375 } else if (f == 1.0) {
3378 if (cfg->compile_aot) {
3379 guint32 val = *(guint32*)&f;
3380 x86_push_imm (code, val);
3381 x86_fld_membase (code, X86_ESP, 0, FALSE);
3382 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3385 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3386 x86_fld (code, NULL, FALSE);
3391 case OP_STORER8_MEMBASE_REG:
3392 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3394 case OP_LOADR8_MEMBASE:
3395 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3397 case OP_STORER4_MEMBASE_REG:
3398 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3400 case OP_LOADR4_MEMBASE:
3401 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3403 case OP_ICONV_TO_R4:
3404 x86_push_reg (code, ins->sreg1);
3405 x86_fild_membase (code, X86_ESP, 0, FALSE);
3406 /* Change precision */
3407 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3408 x86_fld_membase (code, X86_ESP, 0, FALSE);
3409 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3411 case OP_ICONV_TO_R8:
3412 x86_push_reg (code, ins->sreg1);
3413 x86_fild_membase (code, X86_ESP, 0, FALSE);
3414 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3416 case OP_ICONV_TO_R_UN:
3417 x86_push_imm (code, 0);
3418 x86_push_reg (code, ins->sreg1);
3419 x86_fild_membase (code, X86_ESP, 0, TRUE);
3420 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3422 case OP_X86_FP_LOAD_I8:
3423 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3425 case OP_X86_FP_LOAD_I4:
3426 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3428 case OP_FCONV_TO_R4:
3429 /* Change precision */
3430 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3431 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3432 x86_fld_membase (code, X86_ESP, 0, FALSE);
3433 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3435 case OP_FCONV_TO_I1:
3436 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3438 case OP_FCONV_TO_U1:
3439 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3441 case OP_FCONV_TO_I2:
3442 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3444 case OP_FCONV_TO_U2:
3445 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3447 case OP_FCONV_TO_I4:
3449 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3451 case OP_FCONV_TO_I8:
3452 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3453 x86_fnstcw_membase(code, X86_ESP, 0);
3454 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3455 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3456 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3457 x86_fldcw_membase (code, X86_ESP, 2);
3458 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3459 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3460 x86_pop_reg (code, ins->dreg);
3461 x86_pop_reg (code, ins->backend.reg3);
3462 x86_fldcw_membase (code, X86_ESP, 0);
3463 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3465 case OP_LCONV_TO_R8_2:
3466 x86_push_reg (code, ins->sreg2);
3467 x86_push_reg (code, ins->sreg1);
3468 x86_fild_membase (code, X86_ESP, 0, TRUE);
3469 /* Change precision */
3470 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3471 x86_fld_membase (code, X86_ESP, 0, TRUE);
3472 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3474 case OP_LCONV_TO_R4_2:
3475 x86_push_reg (code, ins->sreg2);
3476 x86_push_reg (code, ins->sreg1);
3477 x86_fild_membase (code, X86_ESP, 0, TRUE);
3478 /* Change precision */
3479 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3480 x86_fld_membase (code, X86_ESP, 0, FALSE);
3481 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3483 case OP_LCONV_TO_R_UN_2: {
3484 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3487 /* load 64bit integer to FP stack */
3488 x86_push_reg (code, ins->sreg2);
3489 x86_push_reg (code, ins->sreg1);
3490 x86_fild_membase (code, X86_ESP, 0, TRUE);
3492 /* test if lreg is negative */
3493 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3494 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3496 /* add correction constant mn */
3497 x86_fld80_mem (code, mn);
3498 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3500 x86_patch (br, code);
3502 /* Change precision */
3503 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3504 x86_fld_membase (code, X86_ESP, 0, TRUE);
3506 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3510 case OP_LCONV_TO_OVF_I:
3511 case OP_LCONV_TO_OVF_I4_2: {
3512 guint8 *br [3], *label [1];
3516 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3518 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3520 /* If the low word top bit is set, see if we are negative */
3521 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3522 /* We are not negative (no top bit set, check for our top word to be zero */
3523 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3524 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3527 /* throw exception */
3528 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3530 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3531 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3532 x86_jump8 (code, 0);
3534 x86_jump32 (code, 0);
3536 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3537 x86_jump32 (code, 0);
3541 x86_patch (br [0], code);
3542 /* our top bit is set, check that top word is 0xfffffff */
3543 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3545 x86_patch (br [1], code);
3546 /* nope, emit exception */
3547 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3548 x86_patch (br [2], label [0]);
3550 if (ins->dreg != ins->sreg1)
3551 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3555 /* Not needed on the fp stack */
3558 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3561 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3564 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3567 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3575 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3580 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3587 * it really doesn't make sense to inline all this code,
3588 * it's here just to show that things may not be as simple
3591 guchar *check_pos, *end_tan, *pop_jump;
3592 x86_push_reg (code, X86_EAX);
3595 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3597 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3598 x86_fstp (code, 0); /* pop the 1.0 */
3600 x86_jump8 (code, 0);
3602 x86_fp_op (code, X86_FADD, 0);
3606 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3608 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3611 x86_patch (pop_jump, code);
3612 x86_fstp (code, 0); /* pop the 1.0 */
3613 x86_patch (check_pos, code);
3614 x86_patch (end_tan, code);
3616 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3617 x86_pop_reg (code, X86_EAX);
3624 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3633 g_assert (cfg->opt & MONO_OPT_CMOV);
3634 g_assert (ins->dreg == ins->sreg1);
3635 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3636 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3639 g_assert (cfg->opt & MONO_OPT_CMOV);
3640 g_assert (ins->dreg == ins->sreg1);
3641 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3642 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3645 g_assert (cfg->opt & MONO_OPT_CMOV);
3646 g_assert (ins->dreg == ins->sreg1);
3647 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3648 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3651 g_assert (cfg->opt & MONO_OPT_CMOV);
3652 g_assert (ins->dreg == ins->sreg1);
3653 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3654 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3660 x86_fxch (code, ins->inst_imm);
3665 x86_push_reg (code, X86_EAX);
3666 /* we need to exchange ST(0) with ST(1) */
3669 /* this requires a loop, because fprem somtimes
3670 * returns a partial remainder */
3672 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3673 /* x86_fprem1 (code); */
3676 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3678 x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3683 x86_pop_reg (code, X86_EAX);
3687 if (cfg->opt & MONO_OPT_FCMOV) {
3688 x86_fcomip (code, 1);
3692 /* this overwrites EAX */
3693 EMIT_FPCOMPARE(code);
3694 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3697 if (cfg->opt & MONO_OPT_FCMOV) {
3698 /* zeroing the register at the start results in
3699 * shorter and faster code (we can also remove the widening op)
3701 guchar *unordered_check;
3702 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3703 x86_fcomip (code, 1);
3705 unordered_check = code;
3706 x86_branch8 (code, X86_CC_P, 0, FALSE);
3707 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3708 x86_patch (unordered_check, code);
3711 if (ins->dreg != X86_EAX)
3712 x86_push_reg (code, X86_EAX);
3714 EMIT_FPCOMPARE(code);
3715 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3716 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3717 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3718 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3720 if (ins->dreg != X86_EAX)
3721 x86_pop_reg (code, X86_EAX);
3725 if (cfg->opt & MONO_OPT_FCMOV) {
3726 /* zeroing the register at the start results in
3727 * shorter and faster code (we can also remove the widening op)
3729 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3730 x86_fcomip (code, 1);
3732 if (ins->opcode == OP_FCLT_UN) {
3733 guchar *unordered_check = code;
3734 guchar *jump_to_end;
3735 x86_branch8 (code, X86_CC_P, 0, FALSE);
3736 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3738 x86_jump8 (code, 0);
3739 x86_patch (unordered_check, code);
3740 x86_inc_reg (code, ins->dreg);
3741 x86_patch (jump_to_end, code);
3743 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3747 if (ins->dreg != X86_EAX)
3748 x86_push_reg (code, X86_EAX);
3750 EMIT_FPCOMPARE(code);
3751 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3752 if (ins->opcode == OP_FCLT_UN) {
3753 guchar *is_not_zero_check, *end_jump;
3754 is_not_zero_check = code;
3755 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3757 x86_jump8 (code, 0);
3758 x86_patch (is_not_zero_check, code);
3759 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3761 x86_patch (end_jump, code);
3763 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3764 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3766 if (ins->dreg != X86_EAX)
3767 x86_pop_reg (code, X86_EAX);
3771 if (cfg->opt & MONO_OPT_FCMOV) {
3772 /* zeroing the register at the start results in
3773 * shorter and faster code (we can also remove the widening op)
3775 guchar *unordered_check;
3776 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3777 x86_fcomip (code, 1);
3779 if (ins->opcode == OP_FCGT) {
3780 unordered_check = code;
3781 x86_branch8 (code, X86_CC_P, 0, FALSE);
3782 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3783 x86_patch (unordered_check, code);
3785 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3789 if (ins->dreg != X86_EAX)
3790 x86_push_reg (code, X86_EAX);
3792 EMIT_FPCOMPARE(code);
3793 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3794 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3795 if (ins->opcode == OP_FCGT_UN) {
3796 guchar *is_not_zero_check, *end_jump;
3797 is_not_zero_check = code;
3798 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3800 x86_jump8 (code, 0);
3801 x86_patch (is_not_zero_check, code);
3802 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3804 x86_patch (end_jump, code);
3806 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3807 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3809 if (ins->dreg != X86_EAX)
3810 x86_pop_reg (code, X86_EAX);
3813 if (cfg->opt & MONO_OPT_FCMOV) {
3814 guchar *jump = code;
3815 x86_branch8 (code, X86_CC_P, 0, TRUE);
3816 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3817 x86_patch (jump, code);
3820 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3821 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3824 /* Branch if C013 != 100 */
3825 if (cfg->opt & MONO_OPT_FCMOV) {
3826 /* branch if !ZF or (PF|CF) */
3827 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3828 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3829 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3832 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3833 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3836 if (cfg->opt & MONO_OPT_FCMOV) {
3837 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3840 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3843 if (cfg->opt & MONO_OPT_FCMOV) {
3844 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3845 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3848 if (ins->opcode == OP_FBLT_UN) {
3849 guchar *is_not_zero_check, *end_jump;
3850 is_not_zero_check = code;
3851 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3853 x86_jump8 (code, 0);
3854 x86_patch (is_not_zero_check, code);
3855 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3857 x86_patch (end_jump, code);
3859 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3863 if (cfg->opt & MONO_OPT_FCMOV) {
3864 if (ins->opcode == OP_FBGT) {
3867 /* skip branch if C1=1 */
3869 x86_branch8 (code, X86_CC_P, 0, FALSE);
3870 /* branch if (C0 | C3) = 1 */
3871 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3872 x86_patch (br1, code);
3874 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3878 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3879 if (ins->opcode == OP_FBGT_UN) {
3880 guchar *is_not_zero_check, *end_jump;
3881 is_not_zero_check = code;
3882 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3884 x86_jump8 (code, 0);
3885 x86_patch (is_not_zero_check, code);
3886 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3888 x86_patch (end_jump, code);
3890 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3893 /* Branch if C013 == 100 or 001 */
3894 if (cfg->opt & MONO_OPT_FCMOV) {
3897 /* skip branch if C1=1 */
3899 x86_branch8 (code, X86_CC_P, 0, FALSE);
3900 /* branch if (C0 | C3) = 1 */
3901 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3902 x86_patch (br1, code);
3905 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3906 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3907 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3908 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3911 /* Branch if C013 == 000 */
3912 if (cfg->opt & MONO_OPT_FCMOV) {
3913 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3916 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3919 /* Branch if C013=000 or 100 */
3920 if (cfg->opt & MONO_OPT_FCMOV) {
3923 /* skip branch if C1=1 */
3925 x86_branch8 (code, X86_CC_P, 0, FALSE);
3926 /* branch if C0=0 */
3927 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3928 x86_patch (br1, code);
3931 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
3932 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
3933 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3936 /* Branch if C013 != 001 */
3937 if (cfg->opt & MONO_OPT_FCMOV) {
3938 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3939 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
3942 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3943 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3947 x86_push_reg (code, X86_EAX);
3950 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
3951 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3952 x86_pop_reg (code, X86_EAX);
3954 /* Have to clean up the fp stack before throwing the exception */
3956 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3959 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
3961 x86_patch (br1, code);
3965 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
3968 case OP_MEMORY_BARRIER: {
3969 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
3970 x86_prefix (code, X86_LOCK_PREFIX);
3971 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
3974 case OP_ATOMIC_ADD_I4: {
3975 int dreg = ins->dreg;
3977 if (dreg == ins->inst_basereg) {
3978 x86_push_reg (code, ins->sreg2);
3982 if (dreg != ins->sreg2)
3983 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
3985 x86_prefix (code, X86_LOCK_PREFIX);
3986 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
3988 if (dreg != ins->dreg) {
3989 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
3990 x86_pop_reg (code, dreg);
3995 case OP_ATOMIC_ADD_NEW_I4: {
3996 int dreg = ins->dreg;
3998 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
3999 if (ins->sreg2 == dreg) {
4000 if (dreg == X86_EBX) {
4002 if (ins->inst_basereg == X86_EDI)
4006 if (ins->inst_basereg == X86_EBX)
4009 } else if (ins->inst_basereg == dreg) {
4010 if (dreg == X86_EBX) {
4012 if (ins->sreg2 == X86_EDI)
4016 if (ins->sreg2 == X86_EBX)
4021 if (dreg != ins->dreg) {
4022 x86_push_reg (code, dreg);
4025 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4026 x86_prefix (code, X86_LOCK_PREFIX);
4027 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4028 /* dreg contains the old value, add with sreg2 value */
4029 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4031 if (ins->dreg != dreg) {
4032 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4033 x86_pop_reg (code, dreg);
4038 case OP_ATOMIC_EXCHANGE_I4: {
4040 int sreg2 = ins->sreg2;
4041 int breg = ins->inst_basereg;
4043 /* cmpxchg uses eax as comperand, need to make sure we can use it
4044 * hack to overcome limits in x86 reg allocator
4045 * (req: dreg == eax and sreg2 != eax and breg != eax)
4047 g_assert (ins->dreg == X86_EAX);
4049 /* We need the EAX reg for the cmpxchg */
4050 if (ins->sreg2 == X86_EAX) {
4051 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4052 x86_push_reg (code, sreg2);
4053 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4056 if (breg == X86_EAX) {
4057 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4058 x86_push_reg (code, breg);
4059 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4062 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4064 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4065 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4066 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4067 x86_patch (br [1], br [0]);
4069 if (breg != ins->inst_basereg)
4070 x86_pop_reg (code, breg);
4072 if (ins->sreg2 != sreg2)
4073 x86_pop_reg (code, sreg2);
4077 case OP_ATOMIC_CAS_I4: {
4078 g_assert (ins->dreg == X86_EAX);
4079 g_assert (ins->sreg3 == X86_EAX);
4080 g_assert (ins->sreg1 != X86_EAX);
4081 g_assert (ins->sreg1 != ins->sreg2);
4083 x86_prefix (code, X86_LOCK_PREFIX);
4084 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4087 case OP_CARD_TABLE_WBARRIER: {
4088 int ptr = ins->sreg1;
4089 int value = ins->sreg2;
4091 int nursery_shift, card_table_shift;
4092 gpointer card_table_mask;
4093 size_t nursery_size;
4094 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4095 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4098 * We need one register we can clobber, we choose EDX and make sreg1
4099 * fixed EAX to work around limitations in the local register allocator.
4100 * sreg2 might get allocated to EDX, but that is not a problem since
4101 * we use it before clobbering EDX.
4103 g_assert (ins->sreg1 == X86_EAX);
4106 * This is the code we produce:
4109 * edx >>= nursery_shift
4110 * cmp edx, (nursery_start >> nursery_shift)
4113 * edx >>= card_table_shift
4114 * card_table[edx] = 1
4118 if (value != X86_EDX)
4119 x86_mov_reg_reg (code, X86_EDX, value, 4);
4120 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4121 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4122 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4123 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4124 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4125 if (card_table_mask)
4126 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4127 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4128 x86_patch (br, code);
4131 #ifdef MONO_ARCH_SIMD_INTRINSICS
4133 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4136 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4139 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4142 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4145 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4148 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4151 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4152 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4155 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4158 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4161 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4164 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4167 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4170 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4173 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4176 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4179 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4182 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4185 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4188 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4191 case OP_PSHUFLEW_HIGH:
4192 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4193 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4195 case OP_PSHUFLEW_LOW:
4196 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4197 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4200 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4201 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4205 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4208 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4211 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4214 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4217 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4220 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4223 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4224 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4227 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4230 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4233 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4236 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4239 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4242 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4245 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4248 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4251 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4254 case OP_EXTRACT_MASK:
4255 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4259 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4262 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4265 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4269 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4272 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4275 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4278 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4282 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4285 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4288 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4291 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4295 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4298 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4301 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4305 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4308 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4311 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4315 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4318 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4322 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4325 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4328 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4332 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4335 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4338 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4342 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4345 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4348 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4351 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4355 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4358 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4361 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4364 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4367 case OP_PSUM_ABS_DIFF:
4368 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4371 case OP_UNPACK_LOWB:
4372 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4374 case OP_UNPACK_LOWW:
4375 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4377 case OP_UNPACK_LOWD:
4378 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4380 case OP_UNPACK_LOWQ:
4381 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4383 case OP_UNPACK_LOWPS:
4384 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4386 case OP_UNPACK_LOWPD:
4387 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4390 case OP_UNPACK_HIGHB:
4391 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4393 case OP_UNPACK_HIGHW:
4394 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4396 case OP_UNPACK_HIGHD:
4397 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4399 case OP_UNPACK_HIGHQ:
4400 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4402 case OP_UNPACK_HIGHPS:
4403 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4405 case OP_UNPACK_HIGHPD:
4406 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4410 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4413 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4416 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4419 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4422 case OP_PADDB_SAT_UN:
4423 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4425 case OP_PSUBB_SAT_UN:
4426 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4428 case OP_PADDW_SAT_UN:
4429 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4431 case OP_PSUBW_SAT_UN:
4432 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4436 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4439 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4442 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4445 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4449 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4452 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4455 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4457 case OP_PMULW_HIGH_UN:
4458 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4461 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4465 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4468 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4472 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4475 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4479 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4482 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4486 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4489 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4493 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4496 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4500 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4503 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4507 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4510 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4514 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4517 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4521 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4524 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4528 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4530 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4531 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4535 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4537 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4538 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4542 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4544 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4545 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4549 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4551 case OP_EXTRACTX_U2:
4552 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4554 case OP_INSERTX_U1_SLOW:
4555 /*sreg1 is the extracted ireg (scratch)
4556 /sreg2 is the to be inserted ireg (scratch)
4557 /dreg is the xreg to receive the value*/
4559 /*clear the bits from the extracted word*/
4560 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4561 /*shift the value to insert if needed*/
4562 if (ins->inst_c0 & 1)
4563 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4564 /*join them together*/
4565 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4566 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4568 case OP_INSERTX_I4_SLOW:
4569 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4570 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4571 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4574 case OP_INSERTX_R4_SLOW:
4575 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4576 /*TODO if inst_c0 == 0 use movss*/
4577 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4578 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4580 case OP_INSERTX_R8_SLOW:
4581 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4583 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4585 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVSD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4588 case OP_STOREX_MEMBASE_REG:
4589 case OP_STOREX_MEMBASE:
4590 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4592 case OP_LOADX_MEMBASE:
4593 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4595 case OP_LOADX_ALIGNED_MEMBASE:
4596 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4598 case OP_STOREX_ALIGNED_MEMBASE_REG:
4599 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4601 case OP_STOREX_NTA_MEMBASE_REG:
4602 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4604 case OP_PREFETCH_MEMBASE:
4605 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4609 /*FIXME the peephole pass should have killed this*/
4610 if (ins->dreg != ins->sreg1)
4611 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4614 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4616 case OP_ICONV_TO_R8_RAW:
4617 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
4618 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
4621 case OP_FCONV_TO_R8_X:
4622 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4623 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4626 case OP_XCONV_R8_TO_I4:
4627 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4628 switch (ins->backend.source_opcode) {
4629 case OP_FCONV_TO_I1:
4630 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4632 case OP_FCONV_TO_U1:
4633 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4635 case OP_FCONV_TO_I2:
4636 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4638 case OP_FCONV_TO_U2:
4639 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4645 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4646 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4647 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4648 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4649 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4650 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4653 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4654 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4655 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4658 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4659 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4662 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4663 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4664 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4667 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4668 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4669 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4672 case OP_LIVERANGE_START: {
4673 if (cfg->verbose_level > 1)
4674 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4675 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4678 case OP_LIVERANGE_END: {
4679 if (cfg->verbose_level > 1)
4680 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4681 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4684 case OP_NACL_GC_SAFE_POINT: {
4685 #if defined(__native_client_codegen__)
4686 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
4690 case OP_GC_LIVENESS_DEF:
4691 case OP_GC_LIVENESS_USE:
4692 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4693 ins->backend.pc_offset = code - cfg->native_code;
4695 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4696 ins->backend.pc_offset = code - cfg->native_code;
4697 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4700 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4701 g_assert_not_reached ();
4704 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4705 #ifndef __native_client_codegen__
4706 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4707 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4708 g_assert_not_reached ();
4709 #endif /* __native_client_codegen__ */
4715 cfg->code_len = code - cfg->native_code;
4718 #endif /* DISABLE_JIT */
4721 mono_arch_register_lowlevel_calls (void)
4726 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4728 MonoJumpInfo *patch_info;
4729 gboolean compile_aot = !run_cctors;
4731 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4732 unsigned char *ip = patch_info->ip.i + code;
4733 const unsigned char *target;
4735 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4738 switch (patch_info->type) {
4739 case MONO_PATCH_INFO_BB:
4740 case MONO_PATCH_INFO_LABEL:
4743 /* No need to patch these */
4748 switch (patch_info->type) {
4749 case MONO_PATCH_INFO_IP:
4750 *((gconstpointer *)(ip)) = target;
4752 case MONO_PATCH_INFO_CLASS_INIT: {
4754 /* Might already been changed to a nop */
4755 x86_call_code (code, 0);
4756 x86_patch (ip, target);
4759 case MONO_PATCH_INFO_ABS:
4760 case MONO_PATCH_INFO_METHOD:
4761 case MONO_PATCH_INFO_METHOD_JUMP:
4762 case MONO_PATCH_INFO_INTERNAL_METHOD:
4763 case MONO_PATCH_INFO_BB:
4764 case MONO_PATCH_INFO_LABEL:
4765 case MONO_PATCH_INFO_RGCTX_FETCH:
4766 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
4767 case MONO_PATCH_INFO_MONITOR_ENTER:
4768 case MONO_PATCH_INFO_MONITOR_EXIT:
4769 #if defined(__native_client_codegen__) && defined(__native_client__)
4770 if (nacl_is_code_address (code)) {
4771 /* For tail calls, code is patched after being installed */
4772 /* but not through the normal "patch callsite" method. */
4773 unsigned char buf[kNaClAlignment];
4774 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
4775 unsigned char *_target = target;
4777 /* All patch targets modified in x86_patch */
4778 /* are IP relative. */
4779 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
4780 memcpy (buf, aligned_code, kNaClAlignment);
4781 /* Patch a temp buffer of bundle size, */
4782 /* then install to actual location. */
4783 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
4784 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
4785 g_assert (ret == 0);
4788 x86_patch (ip, target);
4791 x86_patch (ip, target);
4794 case MONO_PATCH_INFO_NONE:
4796 case MONO_PATCH_INFO_R4:
4797 case MONO_PATCH_INFO_R8: {
4798 guint32 offset = mono_arch_get_patch_offset (ip);
4799 *((gconstpointer *)(ip + offset)) = target;
4803 guint32 offset = mono_arch_get_patch_offset (ip);
4804 #if !defined(__native_client__)
4805 *((gconstpointer *)(ip + offset)) = target;
4807 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
4816 mono_arch_emit_prolog (MonoCompile *cfg)
4818 MonoMethod *method = cfg->method;
4820 MonoMethodSignature *sig;
4822 int alloc_size, pos, max_offset, i, cfa_offset;
4824 gboolean need_stack_frame;
4825 #ifdef __native_client_codegen__
4826 guint alignment_check;
4829 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
4831 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4832 cfg->code_size += 512;
4834 #if defined(__default_codegen__)
4835 code = cfg->native_code = g_malloc (cfg->code_size);
4836 #elif defined(__native_client_codegen__)
4837 /* native_code_alloc is not 32-byte aligned, native_code is. */
4838 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
4840 /* Align native_code to next nearest kNaclAlignment byte. */
4841 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
4842 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
4844 code = cfg->native_code;
4846 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
4847 g_assert(alignment_check == 0);
4850 /* Offset between RSP and the CFA */
4854 cfa_offset = sizeof (gpointer);
4855 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
4856 // IP saved at CFA - 4
4857 /* There is no IP reg on x86 */
4858 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
4860 need_stack_frame = needs_stack_frame (cfg);
4862 if (need_stack_frame) {
4863 x86_push_reg (code, X86_EBP);
4864 cfa_offset += sizeof (gpointer);
4865 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4866 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
4867 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
4868 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
4870 cfg->frame_reg = X86_ESP;
4873 alloc_size = cfg->stack_offset;
4876 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4877 /* Might need to attach the thread to the JIT or change the domain for the callback */
4878 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
4879 guint8 *buf, *no_domain_branch;
4881 code = mono_x86_emit_tls_get (code, X86_EAX, appdomain_tls_offset);
4882 x86_alu_reg_imm (code, X86_CMP, X86_EAX, GPOINTER_TO_UINT (cfg->domain));
4883 no_domain_branch = code;
4884 x86_branch8 (code, X86_CC_NE, 0, 0);
4885 code = mono_x86_emit_tls_get ( code, X86_EAX, lmf_tls_offset);
4886 x86_test_reg_reg (code, X86_EAX, X86_EAX);
4888 x86_branch8 (code, X86_CC_NE, 0, 0);
4889 x86_patch (no_domain_branch, code);
4890 x86_push_imm (code, cfg->domain);
4891 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4892 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
4893 x86_patch (buf, code);
4895 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4896 /* FIXME: Add a separate key for LMF to avoid this */
4897 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4901 if (cfg->compile_aot) {
4903 * This goes before the saving of callee saved regs, so save the got reg
4906 x86_push_reg (code, MONO_ARCH_GOT_REG);
4907 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
4908 x86_push_imm (code, 0);
4910 x86_push_imm (code, cfg->domain);
4912 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4913 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
4914 if (cfg->compile_aot)
4915 x86_pop_reg (code, MONO_ARCH_GOT_REG);
4919 if (method->save_lmf) {
4920 pos += sizeof (MonoLMF);
4922 /* save the current IP */
4923 if (cfg->compile_aot) {
4924 /* This pushes the current ip */
4925 x86_call_imm (code, 0);
4927 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
4928 x86_push_imm_template (code);
4930 cfa_offset += sizeof (gpointer);
4932 /* save all caller saved regs */
4933 x86_push_reg (code, X86_EBP);
4934 cfa_offset += sizeof (gpointer);
4935 x86_push_reg (code, X86_ESI);
4936 cfa_offset += sizeof (gpointer);
4937 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
4938 x86_push_reg (code, X86_EDI);
4939 cfa_offset += sizeof (gpointer);
4940 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
4941 x86_push_reg (code, X86_EBX);
4942 cfa_offset += sizeof (gpointer);
4943 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
4945 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
4947 * Optimized version which uses the mono_lmf TLS variable instead of indirection
4948 * through the mono_lmf_addr TLS variable.
4950 /* %eax = previous_lmf */
4951 x86_prefix (code, X86_GS_PREFIX);
4952 x86_mov_reg_mem (code, X86_EAX, lmf_tls_offset, 4);
4953 /* skip esp + method_info + lmf */
4954 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 12);
4955 /* push previous_lmf */
4956 x86_push_reg (code, X86_EAX);
4958 x86_prefix (code, X86_GS_PREFIX);
4959 x86_mov_mem_reg (code, lmf_tls_offset, X86_ESP, 4);
4961 /* get the address of lmf for the current thread */
4963 * This is performance critical so we try to use some tricks to make
4967 if (lmf_addr_tls_offset != -1) {
4968 /* Load lmf quicky using the GS register */
4969 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_addr_tls_offset);
4971 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4972 /* FIXME: Add a separate key for LMF to avoid this */
4973 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4976 if (cfg->compile_aot)
4977 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
4978 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_get_lmf_addr");
4981 /* Skip esp + method info */
4982 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
4985 x86_push_reg (code, X86_EAX);
4986 /* push *lfm (previous_lmf) */
4987 x86_push_membase (code, X86_EAX, 0);
4989 x86_mov_membase_reg (code, X86_EAX, 0, X86_ESP, 4);
4993 if (cfg->used_int_regs & (1 << X86_EBX)) {
4994 x86_push_reg (code, X86_EBX);
4996 cfa_offset += sizeof (gpointer);
4997 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5000 if (cfg->used_int_regs & (1 << X86_EDI)) {
5001 x86_push_reg (code, X86_EDI);
5003 cfa_offset += sizeof (gpointer);
5004 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5007 if (cfg->used_int_regs & (1 << X86_ESI)) {
5008 x86_push_reg (code, X86_ESI);
5010 cfa_offset += sizeof (gpointer);
5011 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5017 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5018 if (mono_do_x86_stack_align && need_stack_frame) {
5019 int tot = alloc_size + pos + 4; /* ret ip */
5020 if (need_stack_frame)
5022 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5024 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5028 /* See mono_emit_stack_alloc */
5029 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5030 guint32 remaining_size = alloc_size;
5031 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5032 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5033 guint32 offset = code - cfg->native_code;
5034 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5035 while (required_code_size >= (cfg->code_size - offset))
5036 cfg->code_size *= 2;
5037 cfg->native_code = mono_realloc_native_code(cfg);
5038 code = cfg->native_code + offset;
5039 mono_jit_stats.code_reallocs++;
5041 while (remaining_size >= 0x1000) {
5042 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5043 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5044 remaining_size -= 0x1000;
5047 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5049 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5052 g_assert (need_stack_frame);
5055 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5056 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5057 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5060 #if DEBUG_STACK_ALIGNMENT
5061 /* check the stack is aligned */
5062 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5063 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5064 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5065 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5066 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5067 x86_breakpoint (code);
5071 /* compute max_offset in order to use short forward jumps */
5073 if (cfg->opt & MONO_OPT_BRANCH) {
5074 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5076 bb->max_offset = max_offset;
5078 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5080 /* max alignment for loops */
5081 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5082 max_offset += LOOP_ALIGNMENT;
5083 #ifdef __native_client_codegen__
5084 /* max alignment for native client */
5085 max_offset += kNaClAlignment;
5087 MONO_BB_FOR_EACH_INS (bb, ins) {
5088 if (ins->opcode == OP_LABEL)
5089 ins->inst_c1 = max_offset;
5090 #ifdef __native_client_codegen__
5092 int space_in_block = kNaClAlignment -
5093 ((max_offset + cfg->code_len) & kNaClAlignmentMask);
5094 int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5095 if (space_in_block < max_len && max_len < kNaClAlignment) {
5096 max_offset += space_in_block;
5099 #endif /* __native_client_codegen__ */
5100 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5105 /* store runtime generic context */
5106 if (cfg->rgctx_var) {
5107 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5109 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5112 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5113 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5115 /* load arguments allocated to register from the stack */
5116 sig = mono_method_signature (method);
5119 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5120 inst = cfg->args [pos];
5121 if (inst->opcode == OP_REGVAR) {
5122 g_assert (need_stack_frame);
5123 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5124 if (cfg->verbose_level > 2)
5125 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5130 cfg->code_len = code - cfg->native_code;
5132 g_assert (cfg->code_len < cfg->code_size);
5138 mono_arch_emit_epilog (MonoCompile *cfg)
5140 MonoMethod *method = cfg->method;
5141 MonoMethodSignature *sig = mono_method_signature (method);
5143 guint32 stack_to_pop;
5145 int max_epilog_size = 16;
5147 gboolean need_stack_frame = needs_stack_frame (cfg);
5149 if (cfg->method->save_lmf)
5150 max_epilog_size += 128;
5152 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5153 cfg->code_size *= 2;
5154 cfg->native_code = mono_realloc_native_code(cfg);
5155 mono_jit_stats.code_reallocs++;
5158 code = cfg->native_code + cfg->code_len;
5160 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5161 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5163 /* the code restoring the registers must be kept in sync with OP_JMP */
5166 if (method->save_lmf) {
5167 gint32 prev_lmf_reg;
5168 gint32 lmf_offset = -sizeof (MonoLMF);
5170 /* check if we need to restore protection of the stack after a stack overflow */
5171 if (mono_get_jit_tls_offset () != -1) {
5173 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5174 /* we load the value in a separate instruction: this mechanism may be
5175 * used later as a safer way to do thread interruption
5177 x86_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5178 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5180 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5181 /* note that the call trampoline will preserve eax/edx */
5182 x86_call_reg (code, X86_ECX);
5183 x86_patch (patch, code);
5185 /* FIXME: maybe save the jit tls in the prolog */
5187 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
5189 * Optimized version which uses the mono_lmf TLS variable instead of indirection
5190 * through the mono_lmf_addr TLS variable.
5192 /* reg = previous_lmf */
5193 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
5195 /* lmf = previous_lmf */
5196 x86_prefix (code, X86_GS_PREFIX);
5197 x86_mov_mem_reg (code, lmf_tls_offset, X86_ECX, 4);
5199 /* Find a spare register */
5200 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, sig->ret)->type) {
5203 prev_lmf_reg = X86_EDI;
5204 cfg->used_int_regs |= (1 << X86_EDI);
5207 prev_lmf_reg = X86_EDX;
5211 /* reg = previous_lmf */
5212 x86_mov_reg_membase (code, prev_lmf_reg, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
5215 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 4);
5217 /* *(lmf) = previous_lmf */
5218 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
5221 /* restore caller saved regs */
5222 if (cfg->used_int_regs & (1 << X86_EBX)) {
5223 x86_mov_reg_membase (code, X86_EBX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), 4);
5226 if (cfg->used_int_regs & (1 << X86_EDI)) {
5227 x86_mov_reg_membase (code, X86_EDI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), 4);
5229 if (cfg->used_int_regs & (1 << X86_ESI)) {
5230 x86_mov_reg_membase (code, X86_ESI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), 4);
5233 /* EBP is restored by LEAVE */
5235 if (cfg->used_int_regs & (1 << X86_EBX)) {
5238 if (cfg->used_int_regs & (1 << X86_EDI)) {
5241 if (cfg->used_int_regs & (1 << X86_ESI)) {
5246 g_assert (need_stack_frame);
5247 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5250 if (cfg->used_int_regs & (1 << X86_ESI)) {
5251 x86_pop_reg (code, X86_ESI);
5253 if (cfg->used_int_regs & (1 << X86_EDI)) {
5254 x86_pop_reg (code, X86_EDI);
5256 if (cfg->used_int_regs & (1 << X86_EBX)) {
5257 x86_pop_reg (code, X86_EBX);
5261 /* Load returned vtypes into registers if needed */
5262 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5263 if (cinfo->ret.storage == ArgValuetypeInReg) {
5264 for (quad = 0; quad < 2; quad ++) {
5265 switch (cinfo->ret.pair_storage [quad]) {
5267 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5269 case ArgOnFloatFpStack:
5270 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5272 case ArgOnDoubleFpStack:
5273 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5278 g_assert_not_reached ();
5283 if (need_stack_frame)
5286 if (CALLCONV_IS_STDCALL (sig)) {
5287 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5289 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
5290 } else if (MONO_TYPE_ISSTRUCT (mono_method_signature (cfg->method)->ret) && (cinfo->ret.storage == ArgOnStack))
5296 g_assert (need_stack_frame);
5297 x86_ret_imm (code, stack_to_pop);
5302 cfg->code_len = code - cfg->native_code;
5304 g_assert (cfg->code_len < cfg->code_size);
5308 mono_arch_emit_exceptions (MonoCompile *cfg)
5310 MonoJumpInfo *patch_info;
5313 MonoClass *exc_classes [16];
5314 guint8 *exc_throw_start [16], *exc_throw_end [16];
5318 /* Compute needed space */
5319 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5320 if (patch_info->type == MONO_PATCH_INFO_EXC)
5325 * make sure we have enough space for exceptions
5326 * 16 is the size of two push_imm instructions and a call
5328 if (cfg->compile_aot)
5329 code_size = exc_count * 32;
5331 code_size = exc_count * 16;
5333 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5334 cfg->code_size *= 2;
5335 cfg->native_code = mono_realloc_native_code(cfg);
5336 mono_jit_stats.code_reallocs++;
5339 code = cfg->native_code + cfg->code_len;
5342 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5343 switch (patch_info->type) {
5344 case MONO_PATCH_INFO_EXC: {
5345 MonoClass *exc_class;
5349 x86_patch (patch_info->ip.i + cfg->native_code, code);
5351 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5352 g_assert (exc_class);
5353 throw_ip = patch_info->ip.i;
5355 /* Find a throw sequence for the same exception class */
5356 for (i = 0; i < nthrows; ++i)
5357 if (exc_classes [i] == exc_class)
5360 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5361 x86_jump_code (code, exc_throw_start [i]);
5362 patch_info->type = MONO_PATCH_INFO_NONE;
5367 /* Compute size of code following the push <OFFSET> */
5368 #if defined(__default_codegen__)
5370 #elif defined(__native_client_codegen__)
5371 code = mono_nacl_align (code);
5372 size = kNaClAlignment;
5374 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5376 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5377 /* Use the shorter form */
5379 x86_push_imm (code, 0);
5383 x86_push_imm (code, 0xf0f0f0f0);
5388 exc_classes [nthrows] = exc_class;
5389 exc_throw_start [nthrows] = code;
5392 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5393 patch_info->data.name = "mono_arch_throw_corlib_exception";
5394 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5395 patch_info->ip.i = code - cfg->native_code;
5396 x86_call_code (code, 0);
5397 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5402 exc_throw_end [nthrows] = code;
5414 cfg->code_len = code - cfg->native_code;
5416 g_assert (cfg->code_len < cfg->code_size);
5420 mono_arch_flush_icache (guint8 *code, gint size)
5426 mono_arch_flush_register_windows (void)
5431 mono_arch_is_inst_imm (gint64 imm)
5437 * Support for fast access to the thread-local lmf structure using the GS
5438 * segment register on NPTL + kernel 2.6.x.
5441 static gboolean tls_offset_inited = FALSE;
5444 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5446 if (!tls_offset_inited) {
5447 if (!getenv ("MONO_NO_TLS")) {
5450 * We need to init this multiple times, since when we are first called, the key might not
5451 * be initialized yet.
5453 appdomain_tls_offset = mono_domain_get_tls_key ();
5454 lmf_tls_offset = mono_get_jit_tls_key ();
5456 /* Only 64 tls entries can be accessed using inline code */
5457 if (appdomain_tls_offset >= 64)
5458 appdomain_tls_offset = -1;
5459 if (lmf_tls_offset >= 64)
5460 lmf_tls_offset = -1;
5463 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5465 tls_offset_inited = TRUE;
5466 appdomain_tls_offset = mono_domain_get_tls_offset ();
5467 lmf_tls_offset = mono_get_lmf_tls_offset ();
5468 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5475 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5479 #ifdef MONO_ARCH_HAVE_IMT
5481 // Linear handler, the bsearch head compare is shorter
5482 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5483 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5484 // x86_patch(ins,target)
5485 //[1 + 5] x86_jump_mem(inst,mem)
5488 #if defined(__default_codegen__)
5489 #define BR_SMALL_SIZE 2
5490 #define BR_LARGE_SIZE 5
5491 #elif defined(__native_client_codegen__)
5492 /* I suspect the size calculation below is actually incorrect. */
5493 /* TODO: fix the calculation that uses these sizes. */
5494 #define BR_SMALL_SIZE 16
5495 #define BR_LARGE_SIZE 12
5496 #endif /*__native_client_codegen__*/
5497 #define JUMP_IMM_SIZE 6
5498 #define ENABLE_WRONG_METHOD_CHECK 0
5502 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5504 int i, distance = 0;
5505 for (i = start; i < target; ++i)
5506 distance += imt_entries [i]->chunk_size;
5511 * LOCKING: called with the domain lock held
5514 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5515 gpointer fail_tramp)
5519 guint8 *code, *start;
5521 for (i = 0; i < count; ++i) {
5522 MonoIMTCheckItem *item = imt_entries [i];
5523 if (item->is_equals) {
5524 if (item->check_target_idx) {
5525 if (!item->compare_done)
5526 item->chunk_size += CMP_SIZE;
5527 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5530 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5532 item->chunk_size += JUMP_IMM_SIZE;
5533 #if ENABLE_WRONG_METHOD_CHECK
5534 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5539 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5540 imt_entries [item->check_target_idx]->compare_done = TRUE;
5542 size += item->chunk_size;
5544 #if defined(__native_client__) && defined(__native_client_codegen__)
5545 /* In Native Client, we don't re-use thunks, allocate from the */
5546 /* normal code manager paths. */
5547 code = mono_domain_code_reserve (domain, size);
5550 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5552 code = mono_domain_code_reserve (domain, size);
5555 for (i = 0; i < count; ++i) {
5556 MonoIMTCheckItem *item = imt_entries [i];
5557 item->code_target = code;
5558 if (item->is_equals) {
5559 if (item->check_target_idx) {
5560 if (!item->compare_done)
5561 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5562 item->jmp_code = code;
5563 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5564 if (item->has_target_code)
5565 x86_jump_code (code, item->value.target_code);
5567 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5570 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5571 item->jmp_code = code;
5572 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5573 if (item->has_target_code)
5574 x86_jump_code (code, item->value.target_code);
5576 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5577 x86_patch (item->jmp_code, code);
5578 x86_jump_code (code, fail_tramp);
5579 item->jmp_code = NULL;
5581 /* enable the commented code to assert on wrong method */
5582 #if ENABLE_WRONG_METHOD_CHECK
5583 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5584 item->jmp_code = code;
5585 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5587 if (item->has_target_code)
5588 x86_jump_code (code, item->value.target_code);
5590 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5591 #if ENABLE_WRONG_METHOD_CHECK
5592 x86_patch (item->jmp_code, code);
5593 x86_breakpoint (code);
5594 item->jmp_code = NULL;
5599 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5600 item->jmp_code = code;
5601 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5602 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5604 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5607 /* patch the branches to get to the target items */
5608 for (i = 0; i < count; ++i) {
5609 MonoIMTCheckItem *item = imt_entries [i];
5610 if (item->jmp_code) {
5611 if (item->check_target_idx) {
5612 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5618 mono_stats.imt_thunks_size += code - start;
5619 g_assert (code - start <= size);
5623 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5624 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5628 if (mono_jit_map_is_enabled ()) {
5631 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5633 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5634 mono_emit_jit_tramp (start, code - start, buff);
5638 nacl_domain_code_validate (domain, &start, size, &code);
5644 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5646 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5651 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5653 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5657 mono_arch_get_cie_program (void)
5661 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5662 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5668 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5670 MonoInst *ins = NULL;
5673 if (cmethod->klass == mono_defaults.math_class) {
5674 if (strcmp (cmethod->name, "Sin") == 0) {
5676 } else if (strcmp (cmethod->name, "Cos") == 0) {
5678 } else if (strcmp (cmethod->name, "Tan") == 0) {
5680 } else if (strcmp (cmethod->name, "Atan") == 0) {
5682 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5684 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5686 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5691 MONO_INST_NEW (cfg, ins, opcode);
5692 ins->type = STACK_R8;
5693 ins->dreg = mono_alloc_freg (cfg);
5694 ins->sreg1 = args [0]->dreg;
5695 MONO_ADD_INS (cfg->cbb, ins);
5698 if (cfg->opt & MONO_OPT_CMOV) {
5701 if (strcmp (cmethod->name, "Min") == 0) {
5702 if (fsig->params [0]->type == MONO_TYPE_I4)
5704 } else if (strcmp (cmethod->name, "Max") == 0) {
5705 if (fsig->params [0]->type == MONO_TYPE_I4)
5710 MONO_INST_NEW (cfg, ins, opcode);
5711 ins->type = STACK_I4;
5712 ins->dreg = mono_alloc_ireg (cfg);
5713 ins->sreg1 = args [0]->dreg;
5714 ins->sreg2 = args [1]->dreg;
5715 MONO_ADD_INS (cfg->cbb, ins);
5720 /* OP_FREM is not IEEE compatible */
5721 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5722 MONO_INST_NEW (cfg, ins, OP_FREM);
5723 ins->inst_i0 = args [0];
5724 ins->inst_i1 = args [1];
5733 mono_arch_print_tree (MonoInst *tree, int arity)
5738 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5744 if (appdomain_tls_offset == -1)
5747 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5748 ins->inst_offset = appdomain_tls_offset;
5753 mono_arch_get_patch_offset (guint8 *code)
5755 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5757 else if ((code [0] == 0xba))
5759 else if ((code [0] == 0x68))
5762 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5763 /* push <OFFSET>(<REG>) */
5765 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5766 /* call *<OFFSET>(<REG>) */
5768 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5771 else if ((code [0] == 0x58) && (code [1] == 0x05))
5772 /* pop %eax; add <OFFSET>, %eax */
5774 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5775 /* pop <REG>; add <OFFSET>, <REG> */
5777 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5778 /* mov <REG>, imm */
5781 g_assert_not_reached ();
5787 * mono_breakpoint_clean_code:
5789 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5790 * breakpoints in the original code, they are removed in the copy.
5792 * Returns TRUE if no sw breakpoint was present.
5795 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5798 gboolean can_write = TRUE;
5800 * If method_start is non-NULL we need to perform bound checks, since we access memory
5801 * at code - offset we could go before the start of the method and end up in a different
5802 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5805 if (!method_start || code - offset >= method_start) {
5806 memcpy (buf, code - offset, size);
5808 int diff = code - method_start;
5809 memset (buf, 0, size);
5810 memcpy (buf + offset - diff, method_start, diff + size - offset);
5813 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5814 int idx = mono_breakpoint_info_index [i];
5818 ptr = mono_breakpoint_info [idx].address;
5819 if (ptr >= code && ptr < code + size) {
5820 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5822 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5823 buf [ptr - code] = saved_byte;
5830 * mono_x86_get_this_arg_offset:
5832 * Return the offset of the stack location where this is passed during a virtual
5836 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
5842 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
5844 guint32 esp = regs [X86_ESP];
5845 CallInfo *cinfo = NULL;
5852 * The stack looks like:
5856 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
5858 res = (((MonoObject**)esp) [5 + (offset / 4)]);
5864 #define MAX_ARCH_DELEGATE_PARAMS 10
5867 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
5869 guint8 *code, *start;
5870 int code_reserve = 64;
5873 * The stack contains:
5879 start = code = mono_global_codeman_reserve (code_reserve);
5881 /* Replace the this argument with the target */
5882 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5883 x86_mov_reg_membase (code, X86_ECX, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, target), 4);
5884 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5885 x86_jump_membase (code, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5887 g_assert ((code - start) < code_reserve);
5890 /* 8 for mov_reg and jump, plus 8 for each parameter */
5891 #ifdef __native_client_codegen__
5892 /* TODO: calculate this size correctly */
5893 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
5895 code_reserve = 8 + (param_count * 8);
5896 #endif /* __native_client_codegen__ */
5898 * The stack contains:
5899 * <args in reverse order>
5904 * <args in reverse order>
5907 * without unbalancing the stack.
5908 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
5909 * and leaving original spot of first arg as placeholder in stack so
5910 * when callee pops stack everything works.
5913 start = code = mono_global_codeman_reserve (code_reserve);
5915 /* store delegate for access to method_ptr */
5916 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
5919 for (i = 0; i < param_count; ++i) {
5920 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
5921 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
5924 x86_jump_membase (code, X86_ECX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5926 g_assert ((code - start) < code_reserve);
5929 nacl_global_codeman_validate(&start, code_reserve, &code);
5930 mono_debug_add_delegate_trampoline (start, code - start);
5933 *code_len = code - start;
5935 if (mono_jit_map_is_enabled ()) {
5938 buff = (char*)"delegate_invoke_has_target";
5940 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
5941 mono_emit_jit_tramp (start, code - start, buff);
5950 mono_arch_get_delegate_invoke_impls (void)
5957 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
5958 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
5960 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
5961 code = get_delegate_invoke_impl (FALSE, i, &code_len);
5962 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
5969 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5971 guint8 *code, *start;
5973 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
5976 /* FIXME: Support more cases */
5977 if (MONO_TYPE_ISSTRUCT (sig->ret))
5981 * The stack contains:
5987 static guint8* cached = NULL;
5992 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
5994 start = get_delegate_invoke_impl (TRUE, 0, NULL);
5996 mono_memory_barrier ();
6000 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6003 for (i = 0; i < sig->param_count; ++i)
6004 if (!mono_is_regsize_var (sig->params [i]))
6007 code = cache [sig->param_count];
6011 if (mono_aot_only) {
6012 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6013 start = mono_aot_get_trampoline (name);
6016 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6019 mono_memory_barrier ();
6021 cache [sig->param_count] = start;
6028 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6031 case X86_EAX: return (gpointer)ctx->eax;
6032 case X86_EBX: return (gpointer)ctx->ebx;
6033 case X86_ECX: return (gpointer)ctx->ecx;
6034 case X86_EDX: return (gpointer)ctx->edx;
6035 case X86_ESP: return (gpointer)ctx->esp;
6036 case X86_EBP: return (gpointer)ctx->ebp;
6037 case X86_ESI: return (gpointer)ctx->esi;
6038 case X86_EDI: return (gpointer)ctx->edi;
6039 default: g_assert_not_reached ();
6043 #ifdef MONO_ARCH_SIMD_INTRINSICS
6046 get_float_to_x_spill_area (MonoCompile *cfg)
6048 if (!cfg->fconv_to_r8_x_var) {
6049 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6050 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6052 return cfg->fconv_to_r8_x_var;
6056 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6059 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6062 int dreg, src_opcode;
6064 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6067 switch (src_opcode = ins->opcode) {
6068 case OP_FCONV_TO_I1:
6069 case OP_FCONV_TO_U1:
6070 case OP_FCONV_TO_I2:
6071 case OP_FCONV_TO_U2:
6072 case OP_FCONV_TO_I4:
6079 /* dreg is the IREG and sreg1 is the FREG */
6080 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6081 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6082 fconv->sreg1 = ins->sreg1;
6083 fconv->dreg = mono_alloc_ireg (cfg);
6084 fconv->type = STACK_VTYPE;
6085 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6087 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6091 ins->opcode = OP_XCONV_R8_TO_I4;
6093 ins->klass = mono_defaults.int32_class;
6094 ins->sreg1 = fconv->dreg;
6096 ins->type = STACK_I4;
6097 ins->backend.source_opcode = src_opcode;
6100 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6103 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6108 if (long_ins->opcode == OP_LNEG) {
6110 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6111 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6112 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6117 #ifdef MONO_ARCH_SIMD_INTRINSICS
6119 if (!(cfg->opt & MONO_OPT_SIMD))
6122 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6123 switch (long_ins->opcode) {
6125 vreg = long_ins->sreg1;
6127 if (long_ins->inst_c0) {
6128 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6129 ins->klass = long_ins->klass;
6130 ins->sreg1 = long_ins->sreg1;
6132 ins->type = STACK_VTYPE;
6133 ins->dreg = vreg = alloc_ireg (cfg);
6134 MONO_ADD_INS (cfg->cbb, ins);
6137 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6138 ins->klass = mono_defaults.int32_class;
6140 ins->type = STACK_I4;
6141 ins->dreg = long_ins->dreg + 1;
6142 MONO_ADD_INS (cfg->cbb, ins);
6144 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6145 ins->klass = long_ins->klass;
6146 ins->sreg1 = long_ins->sreg1;
6147 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6148 ins->type = STACK_VTYPE;
6149 ins->dreg = vreg = alloc_ireg (cfg);
6150 MONO_ADD_INS (cfg->cbb, ins);
6152 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6153 ins->klass = mono_defaults.int32_class;
6155 ins->type = STACK_I4;
6156 ins->dreg = long_ins->dreg + 2;
6157 MONO_ADD_INS (cfg->cbb, ins);
6159 long_ins->opcode = OP_NOP;
6161 case OP_INSERTX_I8_SLOW:
6162 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6163 ins->dreg = long_ins->dreg;
6164 ins->sreg1 = long_ins->dreg;
6165 ins->sreg2 = long_ins->sreg2 + 1;
6166 ins->inst_c0 = long_ins->inst_c0 * 2;
6167 MONO_ADD_INS (cfg->cbb, ins);
6169 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6170 ins->dreg = long_ins->dreg;
6171 ins->sreg1 = long_ins->dreg;
6172 ins->sreg2 = long_ins->sreg2 + 2;
6173 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6174 MONO_ADD_INS (cfg->cbb, ins);
6176 long_ins->opcode = OP_NOP;
6179 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6180 ins->dreg = long_ins->dreg;
6181 ins->sreg1 = long_ins->sreg1 + 1;
6182 ins->klass = long_ins->klass;
6183 ins->type = STACK_VTYPE;
6184 MONO_ADD_INS (cfg->cbb, ins);
6186 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6187 ins->dreg = long_ins->dreg;
6188 ins->sreg1 = long_ins->dreg;
6189 ins->sreg2 = long_ins->sreg1 + 2;
6191 ins->klass = long_ins->klass;
6192 ins->type = STACK_VTYPE;
6193 MONO_ADD_INS (cfg->cbb, ins);
6195 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6196 ins->dreg = long_ins->dreg;
6197 ins->sreg1 = long_ins->dreg;;
6198 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6199 ins->klass = long_ins->klass;
6200 ins->type = STACK_VTYPE;
6201 MONO_ADD_INS (cfg->cbb, ins);
6203 long_ins->opcode = OP_NOP;
6206 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6209 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6211 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6214 gpointer *sp, old_value;
6216 const unsigned char *handler;
6218 /*Decode the first instruction to figure out where did we store the spvar*/
6219 /*Our jit MUST generate the following:
6221 Which is encoded as: 0x89 mod_rm.
6222 mod_rm (esp, ebp, imm) which can be: (imm will never be zero)
6223 mod (reg + imm8): 01 reg(esp): 100 rm(ebp): 101 -> 01100101 (0x65)
6224 mod (reg + imm32): 10 reg(esp): 100 rm(ebp): 101 -> 10100101 (0xA5)
6226 handler = clause->handler_start;
6228 if (*handler != 0x89)
6233 if (*handler == 0x65)
6234 offset = *(signed char*)(handler + 1);
6235 else if (*handler == 0xA5)
6236 offset = *(int*)(handler + 1);
6241 bp = MONO_CONTEXT_GET_BP (ctx);
6242 sp = *(gpointer*)(bp + offset);
6245 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6254 * mono_aot_emit_load_got_addr:
6256 * Emit code to load the got address.
6257 * On x86, the result is placed into EBX.
6260 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6262 x86_call_imm (code, 0);
6264 * The patch needs to point to the pop, since the GOT offset needs
6265 * to be added to that address.
6268 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6270 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6271 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6272 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6278 * mono_ppc_emit_load_aotconst:
6280 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6281 * TARGET from the mscorlib GOT in full-aot code.
6282 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6286 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6288 /* Load the mscorlib got address */
6289 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6290 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6291 /* arch_emit_got_access () patches this */
6292 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6297 /* Can't put this into mini-x86.h */
6299 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6302 mono_arch_get_trampolines (gboolean aot)
6304 MonoTrampInfo *info;
6305 GSList *tramps = NULL;
6307 mono_x86_get_signal_exception_trampoline (&info, aot);
6309 tramps = g_slist_append (tramps, info);
6316 #define DBG_SIGNAL SIGBUS
6318 #define DBG_SIGNAL SIGSEGV
6321 /* Soft Debug support */
6322 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6325 * mono_arch_set_breakpoint:
6327 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6328 * The location should contain code emitted by OP_SEQ_POINT.
6331 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6336 * In production, we will use int3 (has to fix the size in the md
6337 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6340 g_assert (code [0] == 0x90);
6341 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6345 * mono_arch_clear_breakpoint:
6347 * Clear the breakpoint at IP.
6350 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6355 for (i = 0; i < 6; ++i)
6360 * mono_arch_start_single_stepping:
6362 * Start single stepping.
6365 mono_arch_start_single_stepping (void)
6367 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6371 * mono_arch_stop_single_stepping:
6373 * Stop single stepping.
6376 mono_arch_stop_single_stepping (void)
6378 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6382 * mono_arch_is_single_step_event:
6384 * Return whenever the machine state in SIGCTX corresponds to a single
6388 mono_arch_is_single_step_event (void *info, void *sigctx)
6391 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info; /* Sometimes the address is off by 4 */
6392 if ((einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6397 siginfo_t* sinfo = (siginfo_t*) info;
6398 /* Sometimes the address is off by 4 */
6399 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6407 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6410 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info; /* Sometimes the address is off by 4 */
6411 if ((einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6416 siginfo_t* sinfo = (siginfo_t*)info;
6417 /* Sometimes the address is off by 4 */
6418 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6426 * mono_arch_get_ip_for_breakpoint:
6428 * See mini-amd64.c for docs.
6431 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
6433 guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
6438 #define BREAKPOINT_SIZE 6
6441 * mono_arch_get_ip_for_single_step:
6443 * See mini-amd64.c for docs.
6446 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
6448 guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
6450 /* Size of x86_alu_reg_imm */
6457 * mono_arch_skip_breakpoint:
6459 * See mini-amd64.c for docs.
6462 mono_arch_skip_breakpoint (MonoContext *ctx)
6464 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6468 * mono_arch_skip_single_step:
6470 * See mini-amd64.c for docs.
6473 mono_arch_skip_single_step (MonoContext *ctx)
6475 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6479 * mono_arch_get_seq_point_info:
6481 * See mini-amd64.c for docs.
6484 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)