2 * mini-arm64.c: ARM64 backend for the Mono code generator
4 * Copyright 2013 Xamarin, Inc (http://www.xamarin.com)
9 * Paolo Molaro (lupus@ximian.com)
10 * Dietmar Maurer (dietmar@ximian.com)
12 * (C) 2003 Ximian, Inc.
13 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
14 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
18 #include "cpu-arm64.h"
21 #include <mono/arch/arm64/arm64-codegen.h>
22 #include <mono/utils/mono-mmap.h>
23 #include <mono/utils/mono-memory-model.h>
24 #include <mono/metadata/abi-details.h>
29 * - ARM(R) Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile (DDI0487A_a_armv8_arm.pdf)
30 * - Procedure Call Standard for the ARM 64-bit Architecture (AArch64) (IHI0055B_aapcs64.pdf)
31 * - ELF for the ARM 64-bit Architecture (IHI0056B_aaelf64.pdf)
34 * - ip0/ip1/lr are used as temporary registers
35 * - r27 is used as the rgctx/imt register
36 * - r28 is used to access arguments passed on the stack
37 * - d15/d16 are used as fp temporary registers
40 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
42 #define FP_TEMP_REG ARMREG_D16
43 #define FP_TEMP_REG2 ARMREG_D17
45 #define THUNK_SIZE (4 * 4)
47 /* The single step trampoline */
48 static gpointer ss_trampoline;
50 /* The breakpoint trampoline */
51 static gpointer bp_trampoline;
53 static gboolean ios_abi;
55 static __attribute__((warn_unused_result)) guint8* emit_load_regset (guint8 *code, guint64 regs, int basereg, int offset);
58 mono_arch_regname (int reg)
60 static const char * rnames[] = {
61 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
62 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
63 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "fp",
66 if (reg >= 0 && reg < 32)
72 mono_arch_fregname (int reg)
74 static const char * rnames[] = {
75 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9",
76 "d10", "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19",
77 "d20", "d21", "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29",
80 if (reg >= 0 && reg < 32)
86 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
92 #define MAX_ARCH_DELEGATE_PARAMS 7
95 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
100 start = code = mono_global_codeman_reserve (12);
102 /* Replace the this argument with the target */
103 arm_ldrx (code, ARMREG_IP0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
104 arm_ldrx (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
105 arm_brx (code, ARMREG_IP0);
107 g_assert ((code - start) <= 12);
109 mono_arch_flush_icache (start, 12);
113 size = 8 + param_count * 4;
114 start = code = mono_global_codeman_reserve (size);
116 arm_ldrx (code, ARMREG_IP0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
117 /* slide down the arguments */
118 for (i = 0; i < param_count; ++i)
119 arm_movx (code, i, i + 1);
120 arm_brx (code, ARMREG_IP0);
122 g_assert ((code - start) <= size);
124 mono_arch_flush_icache (start, size);
128 *code_size = code - start;
134 * mono_arch_get_delegate_invoke_impls:
136 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
140 mono_arch_get_delegate_invoke_impls (void)
148 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
149 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
151 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
152 code = get_delegate_invoke_impl (FALSE, i, &code_len);
153 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
154 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
162 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
164 guint8 *code, *start;
167 * vtypes are returned in registers, or using the dedicated r8 register, so
168 * they can be supported by delegate invokes.
172 static guint8* cached = NULL;
178 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
180 start = get_delegate_invoke_impl (TRUE, 0, NULL);
181 mono_memory_barrier ();
185 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
188 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
190 for (i = 0; i < sig->param_count; ++i)
191 if (!mono_is_regsize_var (sig->params [i]))
194 code = cache [sig->param_count];
199 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
200 start = mono_aot_get_trampoline (name);
203 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
205 mono_memory_barrier ();
206 cache [sig->param_count] = start;
214 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
220 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
222 return (gpointer)regs [ARMREG_R0];
226 mono_arch_cpu_init (void)
231 mono_arch_init (void)
233 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
234 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
237 bp_trampoline = mini_get_breakpoint_trampoline ();
239 mono_arm_gsharedvt_init ();
241 #if defined(TARGET_IOS)
247 mono_arch_cleanup (void)
252 mono_arch_cpu_optimizations (guint32 *exclude_mask)
259 mono_arch_cpu_enumerate_simd_versions (void)
265 mono_arch_register_lowlevel_calls (void)
270 mono_arch_finish_init (void)
274 /* The maximum length is 2 instructions */
276 emit_imm (guint8 *code, int dreg, int imm)
278 // FIXME: Optimize this
281 arm_movnx (code, dreg, (~limm) & 0xffff, 0);
282 arm_movkx (code, dreg, (limm >> 16) & 0xffff, 16);
284 arm_movzx (code, dreg, imm & 0xffff, 0);
286 arm_movkx (code, dreg, (imm >> 16) & 0xffff, 16);
292 /* The maximum length is 4 instructions */
294 emit_imm64 (guint8 *code, int dreg, guint64 imm)
296 // FIXME: Optimize this
297 arm_movzx (code, dreg, imm & 0xffff, 0);
298 if ((imm >> 16) & 0xffff)
299 arm_movkx (code, dreg, (imm >> 16) & 0xffff, 16);
300 if ((imm >> 32) & 0xffff)
301 arm_movkx (code, dreg, (imm >> 32) & 0xffff, 32);
302 if ((imm >> 48) & 0xffff)
303 arm_movkx (code, dreg, (imm >> 48) & 0xffff, 48);
309 mono_arm_emit_imm64 (guint8 *code, int dreg, gint64 imm)
311 return emit_imm64 (code, dreg, imm);
317 * Emit a patchable code sequence for constructing a 64 bit immediate.
320 emit_imm64_template (guint8 *code, int dreg)
322 arm_movzx (code, dreg, 0, 0);
323 arm_movkx (code, dreg, 0, 16);
324 arm_movkx (code, dreg, 0, 32);
325 arm_movkx (code, dreg, 0, 48);
330 static inline __attribute__((warn_unused_result)) guint8*
331 emit_addw_imm (guint8 *code, int dreg, int sreg, int imm)
333 if (!arm_is_arith_imm (imm)) {
334 code = emit_imm (code, ARMREG_LR, imm);
335 arm_addw (code, dreg, sreg, ARMREG_LR);
337 arm_addw_imm (code, dreg, sreg, imm);
342 static inline __attribute__((warn_unused_result)) guint8*
343 emit_addx_imm (guint8 *code, int dreg, int sreg, int imm)
345 if (!arm_is_arith_imm (imm)) {
346 code = emit_imm (code, ARMREG_LR, imm);
347 arm_addx (code, dreg, sreg, ARMREG_LR);
349 arm_addx_imm (code, dreg, sreg, imm);
354 static inline __attribute__((warn_unused_result)) guint8*
355 emit_subw_imm (guint8 *code, int dreg, int sreg, int imm)
357 if (!arm_is_arith_imm (imm)) {
358 code = emit_imm (code, ARMREG_LR, imm);
359 arm_subw (code, dreg, sreg, ARMREG_LR);
361 arm_subw_imm (code, dreg, sreg, imm);
366 static inline __attribute__((warn_unused_result)) guint8*
367 emit_subx_imm (guint8 *code, int dreg, int sreg, int imm)
369 if (!arm_is_arith_imm (imm)) {
370 code = emit_imm (code, ARMREG_LR, imm);
371 arm_subx (code, dreg, sreg, ARMREG_LR);
373 arm_subx_imm (code, dreg, sreg, imm);
378 /* Emit sp+=imm. Clobbers ip0/ip1 */
379 static inline __attribute__((warn_unused_result)) guint8*
380 emit_addx_sp_imm (guint8 *code, int imm)
382 code = emit_imm (code, ARMREG_IP0, imm);
383 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
384 arm_addx (code, ARMREG_IP1, ARMREG_IP1, ARMREG_IP0);
385 arm_movspx (code, ARMREG_SP, ARMREG_IP1);
389 /* Emit sp-=imm. Clobbers ip0/ip1 */
390 static inline __attribute__((warn_unused_result)) guint8*
391 emit_subx_sp_imm (guint8 *code, int imm)
393 code = emit_imm (code, ARMREG_IP0, imm);
394 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
395 arm_subx (code, ARMREG_IP1, ARMREG_IP1, ARMREG_IP0);
396 arm_movspx (code, ARMREG_SP, ARMREG_IP1);
400 static inline __attribute__((warn_unused_result)) guint8*
401 emit_andw_imm (guint8 *code, int dreg, int sreg, int imm)
404 code = emit_imm (code, ARMREG_LR, imm);
405 arm_andw (code, dreg, sreg, ARMREG_LR);
410 static inline __attribute__((warn_unused_result)) guint8*
411 emit_andx_imm (guint8 *code, int dreg, int sreg, int imm)
414 code = emit_imm (code, ARMREG_LR, imm);
415 arm_andx (code, dreg, sreg, ARMREG_LR);
420 static inline __attribute__((warn_unused_result)) guint8*
421 emit_orrw_imm (guint8 *code, int dreg, int sreg, int imm)
424 code = emit_imm (code, ARMREG_LR, imm);
425 arm_orrw (code, dreg, sreg, ARMREG_LR);
430 static inline __attribute__((warn_unused_result)) guint8*
431 emit_orrx_imm (guint8 *code, int dreg, int sreg, int imm)
434 code = emit_imm (code, ARMREG_LR, imm);
435 arm_orrx (code, dreg, sreg, ARMREG_LR);
440 static inline __attribute__((warn_unused_result)) guint8*
441 emit_eorw_imm (guint8 *code, int dreg, int sreg, int imm)
444 code = emit_imm (code, ARMREG_LR, imm);
445 arm_eorw (code, dreg, sreg, ARMREG_LR);
450 static inline __attribute__((warn_unused_result)) guint8*
451 emit_eorx_imm (guint8 *code, int dreg, int sreg, int imm)
454 code = emit_imm (code, ARMREG_LR, imm);
455 arm_eorx (code, dreg, sreg, ARMREG_LR);
460 static inline __attribute__((warn_unused_result)) guint8*
461 emit_cmpw_imm (guint8 *code, int sreg, int imm)
464 arm_cmpw (code, sreg, ARMREG_RZR);
467 code = emit_imm (code, ARMREG_LR, imm);
468 arm_cmpw (code, sreg, ARMREG_LR);
474 static inline __attribute__((warn_unused_result)) guint8*
475 emit_cmpx_imm (guint8 *code, int sreg, int imm)
478 arm_cmpx (code, sreg, ARMREG_RZR);
481 code = emit_imm (code, ARMREG_LR, imm);
482 arm_cmpx (code, sreg, ARMREG_LR);
488 static inline __attribute__((warn_unused_result)) guint8*
489 emit_strb (guint8 *code, int rt, int rn, int imm)
491 if (arm_is_strb_imm (imm)) {
492 arm_strb (code, rt, rn, imm);
494 g_assert (rt != ARMREG_IP0);
495 g_assert (rn != ARMREG_IP0);
496 code = emit_imm (code, ARMREG_IP0, imm);
497 arm_strb_reg (code, rt, rn, ARMREG_IP0);
502 static inline __attribute__((warn_unused_result)) guint8*
503 emit_strh (guint8 *code, int rt, int rn, int imm)
505 if (arm_is_strh_imm (imm)) {
506 arm_strh (code, rt, rn, imm);
508 g_assert (rt != ARMREG_IP0);
509 g_assert (rn != ARMREG_IP0);
510 code = emit_imm (code, ARMREG_IP0, imm);
511 arm_strh_reg (code, rt, rn, ARMREG_IP0);
516 static inline __attribute__((warn_unused_result)) guint8*
517 emit_strw (guint8 *code, int rt, int rn, int imm)
519 if (arm_is_strw_imm (imm)) {
520 arm_strw (code, rt, rn, imm);
522 g_assert (rt != ARMREG_IP0);
523 g_assert (rn != ARMREG_IP0);
524 code = emit_imm (code, ARMREG_IP0, imm);
525 arm_strw_reg (code, rt, rn, ARMREG_IP0);
530 static inline __attribute__((warn_unused_result)) guint8*
531 emit_strfpw (guint8 *code, int rt, int rn, int imm)
533 if (arm_is_strw_imm (imm)) {
534 arm_strfpw (code, rt, rn, imm);
536 g_assert (rn != ARMREG_IP0);
537 code = emit_imm (code, ARMREG_IP0, imm);
538 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
539 arm_strfpw (code, rt, ARMREG_IP0, 0);
544 static inline __attribute__((warn_unused_result)) guint8*
545 emit_strfpx (guint8 *code, int rt, int rn, int imm)
547 if (arm_is_strx_imm (imm)) {
548 arm_strfpx (code, rt, rn, imm);
550 g_assert (rn != ARMREG_IP0);
551 code = emit_imm (code, ARMREG_IP0, imm);
552 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
553 arm_strfpx (code, rt, ARMREG_IP0, 0);
558 static inline __attribute__((warn_unused_result)) guint8*
559 emit_strx (guint8 *code, int rt, int rn, int imm)
561 if (arm_is_strx_imm (imm)) {
562 arm_strx (code, rt, rn, imm);
564 g_assert (rt != ARMREG_IP0);
565 g_assert (rn != ARMREG_IP0);
566 code = emit_imm (code, ARMREG_IP0, imm);
567 arm_strx_reg (code, rt, rn, ARMREG_IP0);
572 static inline __attribute__((warn_unused_result)) guint8*
573 emit_ldrb (guint8 *code, int rt, int rn, int imm)
575 if (arm_is_pimm12_scaled (imm, 1)) {
576 arm_ldrb (code, rt, rn, imm);
578 g_assert (rt != ARMREG_IP0);
579 g_assert (rn != ARMREG_IP0);
580 code = emit_imm (code, ARMREG_IP0, imm);
581 arm_ldrb_reg (code, rt, rn, ARMREG_IP0);
586 static inline __attribute__((warn_unused_result)) guint8*
587 emit_ldrsbx (guint8 *code, int rt, int rn, int imm)
589 if (arm_is_pimm12_scaled (imm, 1)) {
590 arm_ldrsbx (code, rt, rn, imm);
592 g_assert (rt != ARMREG_IP0);
593 g_assert (rn != ARMREG_IP0);
594 code = emit_imm (code, ARMREG_IP0, imm);
595 arm_ldrsbx_reg (code, rt, rn, ARMREG_IP0);
600 static inline __attribute__((warn_unused_result)) guint8*
601 emit_ldrh (guint8 *code, int rt, int rn, int imm)
603 if (arm_is_pimm12_scaled (imm, 2)) {
604 arm_ldrh (code, rt, rn, imm);
606 g_assert (rt != ARMREG_IP0);
607 g_assert (rn != ARMREG_IP0);
608 code = emit_imm (code, ARMREG_IP0, imm);
609 arm_ldrh_reg (code, rt, rn, ARMREG_IP0);
614 static inline __attribute__((warn_unused_result)) guint8*
615 emit_ldrshx (guint8 *code, int rt, int rn, int imm)
617 if (arm_is_pimm12_scaled (imm, 2)) {
618 arm_ldrshx (code, rt, rn, imm);
620 g_assert (rt != ARMREG_IP0);
621 g_assert (rn != ARMREG_IP0);
622 code = emit_imm (code, ARMREG_IP0, imm);
623 arm_ldrshx_reg (code, rt, rn, ARMREG_IP0);
628 static inline __attribute__((warn_unused_result)) guint8*
629 emit_ldrswx (guint8 *code, int rt, int rn, int imm)
631 if (arm_is_pimm12_scaled (imm, 4)) {
632 arm_ldrswx (code, rt, rn, imm);
634 g_assert (rt != ARMREG_IP0);
635 g_assert (rn != ARMREG_IP0);
636 code = emit_imm (code, ARMREG_IP0, imm);
637 arm_ldrswx_reg (code, rt, rn, ARMREG_IP0);
642 static inline __attribute__((warn_unused_result)) guint8*
643 emit_ldrw (guint8 *code, int rt, int rn, int imm)
645 if (arm_is_pimm12_scaled (imm, 4)) {
646 arm_ldrw (code, rt, rn, imm);
648 g_assert (rn != ARMREG_IP0);
649 code = emit_imm (code, ARMREG_IP0, imm);
650 arm_ldrw_reg (code, rt, rn, ARMREG_IP0);
655 static inline __attribute__((warn_unused_result)) guint8*
656 emit_ldrx (guint8 *code, int rt, int rn, int imm)
658 if (arm_is_pimm12_scaled (imm, 8)) {
659 arm_ldrx (code, rt, rn, imm);
661 g_assert (rn != ARMREG_IP0);
662 code = emit_imm (code, ARMREG_IP0, imm);
663 arm_ldrx_reg (code, rt, rn, ARMREG_IP0);
668 static inline __attribute__((warn_unused_result)) guint8*
669 emit_ldrfpw (guint8 *code, int rt, int rn, int imm)
671 if (arm_is_pimm12_scaled (imm, 4)) {
672 arm_ldrfpw (code, rt, rn, imm);
674 g_assert (rn != ARMREG_IP0);
675 code = emit_imm (code, ARMREG_IP0, imm);
676 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
677 arm_ldrfpw (code, rt, ARMREG_IP0, 0);
682 static inline __attribute__((warn_unused_result)) guint8*
683 emit_ldrfpx (guint8 *code, int rt, int rn, int imm)
685 if (arm_is_pimm12_scaled (imm, 8)) {
686 arm_ldrfpx (code, rt, rn, imm);
688 g_assert (rn != ARMREG_IP0);
689 code = emit_imm (code, ARMREG_IP0, imm);
690 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
691 arm_ldrfpx (code, rt, ARMREG_IP0, 0);
697 mono_arm_emit_ldrx (guint8 *code, int rt, int rn, int imm)
699 return emit_ldrx (code, rt, rn, imm);
703 emit_call (MonoCompile *cfg, guint8* code, guint32 patch_type, gconstpointer data)
706 mono_add_patch_info_rel (cfg, code - cfg->native_code, patch_type, data, MONO_R_ARM64_IMM);
707 code = emit_imm64_template (code, ARMREG_LR);
708 arm_blrx (code, ARMREG_LR);
710 mono_add_patch_info_rel (cfg, code - cfg->native_code, patch_type, data, MONO_R_ARM64_BL);
712 cfg->thunk_area += THUNK_SIZE;
717 emit_aotconst_full (MonoCompile *cfg, MonoJumpInfo **ji, guint8 *code, guint8 *start, int dreg, guint32 patch_type, gconstpointer data)
720 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
722 *ji = mono_patch_info_list_prepend (*ji, code - start, patch_type, data);
723 /* See arch_emit_got_access () in aot-compiler.c */
724 arm_ldrx_lit (code, dreg, 0);
731 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, guint32 patch_type, gconstpointer data)
733 return emit_aotconst_full (cfg, NULL, code, NULL, dreg, patch_type, data);
737 * mono_arm_emit_aotconst:
739 * Emit code to load an AOT constant into DREG. Usable from trampolines.
742 mono_arm_emit_aotconst (gpointer ji, guint8 *code, guint8 *code_start, int dreg, guint32 patch_type, gconstpointer data)
744 return emit_aotconst_full (NULL, (MonoJumpInfo**)ji, code, code_start, dreg, patch_type, data);
748 emit_tls_get (guint8 *code, int dreg, int tls_offset)
750 arm_mrs (code, dreg, ARM_MRS_REG_TPIDR_EL0);
751 if (tls_offset < 256) {
752 arm_ldrx (code, dreg, dreg, tls_offset);
754 code = emit_addx_imm (code, dreg, dreg, tls_offset);
755 arm_ldrx (code, dreg, dreg, 0);
761 emit_tls_get_reg (guint8 *code, int dreg, int offset_reg)
763 g_assert (offset_reg != ARMREG_IP0);
764 arm_mrs (code, ARMREG_IP0, ARM_MRS_REG_TPIDR_EL0);
765 arm_ldrx_reg (code, dreg, ARMREG_IP0, offset_reg);
770 emit_tls_set (guint8 *code, int sreg, int tls_offset)
772 int tmpreg = ARMREG_IP0;
774 g_assert (sreg != tmpreg);
775 arm_mrs (code, tmpreg, ARM_MRS_REG_TPIDR_EL0);
776 if (tls_offset < 256) {
777 arm_strx (code, sreg, tmpreg, tls_offset);
779 code = emit_addx_imm (code, tmpreg, tmpreg, tls_offset);
780 arm_strx (code, sreg, tmpreg, 0);
787 emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
789 int tmpreg = ARMREG_IP0;
791 g_assert (sreg != tmpreg);
792 arm_mrs (code, tmpreg, ARM_MRS_REG_TPIDR_EL0);
793 arm_strx_reg (code, sreg, tmpreg, offset_reg);
800 * - ldrp [fp, lr], [sp], !stack_offfset
801 * Clobbers TEMP_REGS.
803 __attribute__((warn_unused_result)) guint8*
804 mono_arm_emit_destroy_frame (guint8 *code, int stack_offset, guint64 temp_regs)
806 arm_movspx (code, ARMREG_SP, ARMREG_FP);
808 if (arm_is_ldpx_imm (stack_offset)) {
809 arm_ldpx_post (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, stack_offset);
811 arm_ldpx (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, 0);
812 /* sp += stack_offset */
813 g_assert (temp_regs & (1 << ARMREG_IP0));
814 if (temp_regs & (1 << ARMREG_IP1)) {
815 code = emit_addx_sp_imm (code, stack_offset);
817 int imm = stack_offset;
819 /* Can't use addx_sp_imm () since we can't clobber ip0/ip1 */
820 arm_addx_imm (code, ARMREG_IP0, ARMREG_SP, 0);
822 arm_addx_imm (code, ARMREG_IP0, ARMREG_IP0, 256);
825 arm_addx_imm (code, ARMREG_SP, ARMREG_IP0, imm);
831 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
834 emit_thunk (guint8 *code, gconstpointer target)
838 arm_ldrx_lit (code, ARMREG_IP0, code + 8);
839 arm_brx (code, ARMREG_IP0);
840 *(guint64*)code = (guint64)target;
842 mono_arch_flush_icache (p, code - p);
847 create_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
850 MonoThunkJitInfo *info;
854 guint8 *target_thunk;
857 domain = mono_domain_get ();
861 * This can be called multiple times during JITting,
862 * save the current position in cfg->arch to avoid
863 * doing a O(n^2) search.
865 if (!cfg->arch.thunks) {
866 cfg->arch.thunks = cfg->thunks;
867 cfg->arch.thunks_size = cfg->thunk_area;
869 thunks = cfg->arch.thunks;
870 thunks_size = cfg->arch.thunks_size;
872 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
873 g_assert_not_reached ();
876 g_assert (*(guint32*)thunks == 0);
877 emit_thunk (thunks, target);
879 cfg->arch.thunks += THUNK_SIZE;
880 cfg->arch.thunks_size -= THUNK_SIZE;
884 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
886 info = mono_jit_info_get_thunk_info (ji);
889 thunks = (guint8*)ji->code_start + info->thunks_offset;
890 thunks_size = info->thunks_size;
892 orig_target = mono_arch_get_call_target (code + 4);
894 mono_domain_lock (domain);
897 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
898 /* The call already points to a thunk, because of trampolines etc. */
899 target_thunk = orig_target;
901 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
902 if (((guint32*)p) [0] == 0) {
906 } else if (((guint64*)p) [1] == (guint64)target) {
907 /* Thunk already points to target */
914 //printf ("THUNK: %p %p %p\n", code, target, target_thunk);
917 mono_domain_unlock (domain);
918 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
919 g_assert_not_reached ();
922 emit_thunk (target_thunk, target);
924 mono_domain_unlock (domain);
931 arm_patch_full (MonoCompile *cfg, MonoDomain *domain, guint8 *code, guint8 *target, int relocation)
933 switch (relocation) {
935 arm_b (code, target);
937 case MONO_R_ARM64_BCC: {
940 cond = arm_get_bcc_cond (code);
941 arm_bcc (code, cond, target);
944 case MONO_R_ARM64_CBZ:
945 arm_set_cbz_target (code, target);
947 case MONO_R_ARM64_IMM: {
948 guint64 imm = (guint64)target;
951 /* emit_imm64_template () */
952 dreg = arm_get_movzx_rd (code);
953 arm_movzx (code, dreg, imm & 0xffff, 0);
954 arm_movkx (code, dreg, (imm >> 16) & 0xffff, 16);
955 arm_movkx (code, dreg, (imm >> 32) & 0xffff, 32);
956 arm_movkx (code, dreg, (imm >> 48) & 0xffff, 48);
959 case MONO_R_ARM64_BL:
960 if (arm_is_bl_disp (code, target)) {
961 arm_bl (code, target);
965 thunk = create_thunk (cfg, domain, code, target);
966 g_assert (arm_is_bl_disp (code, thunk));
967 arm_bl (code, thunk);
971 g_assert_not_reached ();
976 arm_patch_rel (guint8 *code, guint8 *target, int relocation)
978 arm_patch_full (NULL, NULL, code, target, relocation);
982 mono_arm_patch (guint8 *code, guint8 *target, int relocation)
984 arm_patch_rel (code, target, relocation);
988 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
992 ip = ji->ip.i + code;
995 case MONO_PATCH_INFO_METHOD_JUMP:
996 /* ji->relocation is not set by the caller */
997 arm_patch_rel (ip, (guint8*)target, MONO_R_ARM64_B);
1000 arm_patch_full (cfg, domain, ip, (guint8*)target, ji->relocation);
1006 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
1011 mono_arch_flush_register_windows (void)
1016 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
1018 return (gpointer)regs [MONO_ARCH_RGCTX_REG];
1022 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
1024 return (gpointer)regs [MONO_ARCH_RGCTX_REG];
1028 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
1030 return ctx->regs [reg];
1034 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
1036 ctx->regs [reg] = val;
1040 * mono_arch_set_target:
1042 * Set the target architecture the JIT backend should generate code for, in the form
1043 * of a GNU target triplet. Only used in AOT mode.
1046 mono_arch_set_target (char *mtriple)
1048 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
1054 add_general (CallInfo *cinfo, ArgInfo *ainfo, int size, gboolean sign)
1056 if (cinfo->gr >= PARAM_REGS) {
1057 ainfo->storage = ArgOnStack;
1059 /* Assume size == align */
1060 cinfo->stack_usage = ALIGN_TO (cinfo->stack_usage, size);
1061 ainfo->offset = cinfo->stack_usage;
1062 ainfo->slot_size = size;
1064 cinfo->stack_usage += size;
1066 ainfo->offset = cinfo->stack_usage;
1067 ainfo->slot_size = 8;
1068 ainfo->sign = FALSE;
1069 /* Put arguments into 8 byte aligned stack slots */
1070 cinfo->stack_usage += 8;
1073 ainfo->storage = ArgInIReg;
1074 ainfo->reg = cinfo->gr;
1080 add_fp (CallInfo *cinfo, ArgInfo *ainfo, gboolean single)
1082 int size = single ? 4 : 8;
1084 if (cinfo->fr >= FP_PARAM_REGS) {
1085 ainfo->storage = single ? ArgOnStackR4 : ArgOnStackR8;
1087 cinfo->stack_usage = ALIGN_TO (cinfo->stack_usage, size);
1088 ainfo->offset = cinfo->stack_usage;
1089 ainfo->slot_size = size;
1090 cinfo->stack_usage += size;
1092 ainfo->offset = cinfo->stack_usage;
1093 ainfo->slot_size = 8;
1094 /* Put arguments into 8 byte aligned stack slots */
1095 cinfo->stack_usage += 8;
1099 ainfo->storage = ArgInFRegR4;
1101 ainfo->storage = ArgInFReg;
1102 ainfo->reg = cinfo->fr;
1108 is_hfa (MonoType *t, int *out_nfields, int *out_esize, int *field_offsets)
1112 MonoClassField *field;
1113 MonoType *ftype, *prev_ftype = NULL;
1116 klass = mono_class_from_mono_type (t);
1118 while ((field = mono_class_get_fields (klass, &iter))) {
1119 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1121 ftype = mono_field_get_type (field);
1122 ftype = mini_get_underlying_type (ftype);
1124 if (MONO_TYPE_ISSTRUCT (ftype)) {
1125 int nested_nfields, nested_esize;
1126 int nested_field_offsets [16];
1128 if (!is_hfa (ftype, &nested_nfields, &nested_esize, nested_field_offsets))
1130 if (nested_esize == 4)
1131 ftype = &mono_defaults.single_class->byval_arg;
1133 ftype = &mono_defaults.double_class->byval_arg;
1134 if (prev_ftype && prev_ftype->type != ftype->type)
1137 for (i = 0; i < nested_nfields; ++i) {
1138 if (nfields + i < 4)
1139 field_offsets [nfields + i] = field->offset - sizeof (MonoObject) + nested_field_offsets [i];
1141 nfields += nested_nfields;
1143 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1145 if (prev_ftype && prev_ftype->type != ftype->type)
1149 field_offsets [nfields] = field->offset - sizeof (MonoObject);
1153 if (nfields == 0 || nfields > 4)
1155 *out_nfields = nfields;
1156 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1161 add_valuetype (CallInfo *cinfo, ArgInfo *ainfo, MonoType *t)
1163 int i, size, align_size, nregs, nfields, esize;
1164 int field_offsets [16];
1167 size = mini_type_stack_size_full (t, &align, FALSE);
1168 align_size = ALIGN_TO (size, 8);
1171 if (is_hfa (t, &nfields, &esize, field_offsets)) {
1173 * The struct might include nested float structs aligned at 8,
1174 * so need to keep track of the offsets of the individual fields.
1176 if (cinfo->fr + nfields <= FP_PARAM_REGS) {
1177 ainfo->storage = ArgHFA;
1178 ainfo->reg = cinfo->fr;
1179 ainfo->nregs = nfields;
1181 ainfo->esize = esize;
1182 for (i = 0; i < nfields; ++i)
1183 ainfo->foffsets [i] = field_offsets [i];
1184 cinfo->fr += ainfo->nregs;
1186 ainfo->nfregs_to_skip = FP_PARAM_REGS > cinfo->fr ? FP_PARAM_REGS - cinfo->fr : 0;
1187 cinfo->fr = FP_PARAM_REGS;
1188 size = ALIGN_TO (size, 8);
1189 ainfo->storage = ArgVtypeOnStack;
1190 ainfo->offset = cinfo->stack_usage;
1193 ainfo->nregs = nfields;
1194 ainfo->esize = esize;
1195 cinfo->stack_usage += size;
1200 if (align_size > 16) {
1201 ainfo->storage = ArgVtypeByRef;
1206 if (cinfo->gr + nregs > PARAM_REGS) {
1207 size = ALIGN_TO (size, 8);
1208 ainfo->storage = ArgVtypeOnStack;
1209 ainfo->offset = cinfo->stack_usage;
1211 cinfo->stack_usage += size;
1212 cinfo->gr = PARAM_REGS;
1214 ainfo->storage = ArgVtypeInIRegs;
1215 ainfo->reg = cinfo->gr;
1216 ainfo->nregs = nregs;
1223 add_param (CallInfo *cinfo, ArgInfo *ainfo, MonoType *t)
1227 ptype = mini_get_underlying_type (t);
1228 switch (ptype->type) {
1230 add_general (cinfo, ainfo, 1, TRUE);
1232 case MONO_TYPE_BOOLEAN:
1234 add_general (cinfo, ainfo, 1, FALSE);
1237 add_general (cinfo, ainfo, 2, TRUE);
1240 case MONO_TYPE_CHAR:
1241 add_general (cinfo, ainfo, 2, FALSE);
1244 add_general (cinfo, ainfo, 4, TRUE);
1247 add_general (cinfo, ainfo, 4, FALSE);
1252 case MONO_TYPE_FNPTR:
1253 case MONO_TYPE_CLASS:
1254 case MONO_TYPE_OBJECT:
1255 case MONO_TYPE_SZARRAY:
1256 case MONO_TYPE_ARRAY:
1257 case MONO_TYPE_STRING:
1260 add_general (cinfo, ainfo, 8, FALSE);
1263 add_fp (cinfo, ainfo, FALSE);
1266 add_fp (cinfo, ainfo, TRUE);
1268 case MONO_TYPE_VALUETYPE:
1269 case MONO_TYPE_TYPEDBYREF:
1270 add_valuetype (cinfo, ainfo, ptype);
1272 case MONO_TYPE_VOID:
1273 ainfo->storage = ArgNone;
1275 case MONO_TYPE_GENERICINST:
1276 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1277 add_general (cinfo, ainfo, 8, FALSE);
1278 } else if (mini_is_gsharedvt_variable_type (ptype)) {
1280 * Treat gsharedvt arguments as large vtypes
1282 ainfo->storage = ArgVtypeByRef;
1283 ainfo->gsharedvt = TRUE;
1285 add_valuetype (cinfo, ainfo, ptype);
1289 case MONO_TYPE_MVAR:
1290 g_assert (mini_is_gsharedvt_type (ptype));
1291 ainfo->storage = ArgVtypeByRef;
1292 ainfo->gsharedvt = TRUE;
1295 g_assert_not_reached ();
1303 * Obtain information about a call according to the calling convention.
1306 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1310 int n, pstart, pindex;
1312 n = sig->hasthis + sig->param_count;
1315 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1317 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1322 add_param (cinfo, &cinfo->ret, sig->ret);
1323 if (cinfo->ret.storage == ArgVtypeByRef)
1324 cinfo->ret.reg = ARMREG_R8;
1328 cinfo->stack_usage = 0;
1332 add_general (cinfo, cinfo->args + 0, 8, FALSE);
1334 for (pindex = pstart; pindex < sig->param_count; ++pindex) {
1335 ainfo = cinfo->args + sig->hasthis + pindex;
1337 if ((sig->call_convention == MONO_CALL_VARARG) && (pindex == sig->sentinelpos)) {
1338 /* Prevent implicit arguments and sig_cookie from
1339 being passed in registers */
1340 cinfo->gr = PARAM_REGS;
1341 cinfo->fr = FP_PARAM_REGS;
1342 /* Emit the signature cookie just before the implicit arguments */
1343 add_param (cinfo, &cinfo->sig_cookie, &mono_defaults.int_class->byval_arg);
1346 add_param (cinfo, ainfo, sig->params [pindex]);
1347 if (ainfo->storage == ArgVtypeByRef) {
1348 /* Pass the argument address in the next register */
1349 if (cinfo->gr >= PARAM_REGS) {
1350 ainfo->storage = ArgVtypeByRefOnStack;
1351 ainfo->offset = cinfo->stack_usage;
1352 cinfo->stack_usage += 8;
1354 ainfo->reg = cinfo->gr;
1360 /* Handle the case where there are no implicit arguments */
1361 if ((sig->call_convention == MONO_CALL_VARARG) && (pindex == sig->sentinelpos)) {
1362 /* Prevent implicit arguments and sig_cookie from
1363 being passed in registers */
1364 cinfo->gr = PARAM_REGS;
1365 cinfo->fr = FP_PARAM_REGS;
1366 /* Emit the signature cookie just before the implicit arguments */
1367 add_param (cinfo, &cinfo->sig_cookie, &mono_defaults.int_class->byval_arg);
1370 cinfo->stack_usage = ALIGN_TO (cinfo->stack_usage, MONO_ARCH_FRAME_ALIGNMENT);
1376 MonoMethodSignature *sig;
1379 MonoType **param_types;
1380 int n_fpargs, n_fpret;
1384 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
1388 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
1391 // FIXME: Add more cases
1392 switch (cinfo->ret.storage) {
1399 case ArgVtypeInIRegs:
1400 if (cinfo->ret.nregs > 2)
1409 for (i = 0; i < cinfo->nargs; ++i) {
1410 ArgInfo *ainfo = &cinfo->args [i];
1412 switch (ainfo->storage) {
1414 case ArgVtypeInIRegs:
1421 if (ainfo->offset >= DYN_CALL_STACK_ARGS * sizeof (mgreg_t))
1433 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
1435 ArchDynCallInfo *info;
1439 cinfo = get_call_info (NULL, sig);
1441 if (!dyn_call_supported (cinfo, sig)) {
1446 info = g_new0 (ArchDynCallInfo, 1);
1447 // FIXME: Preprocess the info to speed up start_dyn_call ()
1449 info->cinfo = cinfo;
1450 info->rtype = mini_get_underlying_type (sig->ret);
1451 info->param_types = g_new0 (MonoType*, sig->param_count);
1452 for (i = 0; i < sig->param_count; ++i)
1453 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
1455 switch (cinfo->ret.storage) {
1461 info->n_fpret = cinfo->ret.nregs;
1467 return (MonoDynCallInfo*)info;
1471 mono_arch_dyn_call_free (MonoDynCallInfo *info)
1473 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
1475 g_free (ainfo->cinfo);
1476 g_free (ainfo->param_types);
1481 bitcast_r4_to_r8 (float f)
1489 bitcast_r8_to_r4 (double f)
1497 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
1499 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
1500 DynCallArgs *p = (DynCallArgs*)buf;
1501 int aindex, arg_index, greg, i, pindex;
1502 MonoMethodSignature *sig = dinfo->sig;
1503 CallInfo *cinfo = dinfo->cinfo;
1504 int buffer_offset = 0;
1506 g_assert (buf_len >= sizeof (DynCallArgs));
1510 p->n_fpargs = dinfo->n_fpargs;
1511 p->n_fpret = dinfo->n_fpret;
1518 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
1520 if (cinfo->ret.storage == ArgVtypeByRef)
1521 p->regs [ARMREG_R8] = (mgreg_t)ret;
1523 for (aindex = pindex; aindex < sig->param_count; aindex++) {
1524 MonoType *t = dinfo->param_types [aindex];
1525 gpointer *arg = args [arg_index ++];
1526 ArgInfo *ainfo = &cinfo->args [aindex + sig->hasthis];
1529 if (ainfo->storage == ArgOnStack) {
1530 slot = PARAM_REGS + 1 + (ainfo->offset / sizeof (mgreg_t));
1536 p->regs [slot] = (mgreg_t)*arg;
1540 if (ios_abi && ainfo->storage == ArgOnStack) {
1541 guint8 *stack_arg = (guint8*)&(p->regs [PARAM_REGS + 1]) + ainfo->offset;
1542 gboolean handled = TRUE;
1544 /* Special case arguments smaller than 1 machine word */
1546 case MONO_TYPE_BOOLEAN:
1548 *(guint8*)stack_arg = *(guint8*)arg;
1551 *(gint8*)stack_arg = *(gint8*)arg;
1554 case MONO_TYPE_CHAR:
1555 *(guint16*)stack_arg = *(guint16*)arg;
1558 *(gint16*)stack_arg = *(gint16*)arg;
1561 *(gint32*)stack_arg = *(gint32*)arg;
1564 *(guint32*)stack_arg = *(guint32*)arg;
1575 case MONO_TYPE_STRING:
1576 case MONO_TYPE_CLASS:
1577 case MONO_TYPE_ARRAY:
1578 case MONO_TYPE_SZARRAY:
1579 case MONO_TYPE_OBJECT:
1585 p->regs [slot] = (mgreg_t)*arg;
1587 case MONO_TYPE_BOOLEAN:
1589 p->regs [slot] = *(guint8*)arg;
1592 p->regs [slot] = *(gint8*)arg;
1595 p->regs [slot] = *(gint16*)arg;
1598 case MONO_TYPE_CHAR:
1599 p->regs [slot] = *(guint16*)arg;
1602 p->regs [slot] = *(gint32*)arg;
1605 p->regs [slot] = *(guint32*)arg;
1608 p->fpregs [ainfo->reg] = bitcast_r4_to_r8 (*(float*)arg);
1612 p->fpregs [ainfo->reg] = *(double*)arg;
1615 case MONO_TYPE_GENERICINST:
1616 if (MONO_TYPE_IS_REFERENCE (t)) {
1617 p->regs [slot] = (mgreg_t)*arg;
1620 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
1621 MonoClass *klass = mono_class_from_mono_type (t);
1622 guint8 *nullable_buf;
1626 * Use p->buffer as a temporary buffer since the data needs to be available after this call
1627 * if the nullable param is passed by ref.
1629 size = mono_class_value_size (klass, NULL);
1630 nullable_buf = p->buffer + buffer_offset;
1631 buffer_offset += size;
1632 g_assert (buffer_offset <= 256);
1634 /* The argument pointed to by arg is either a boxed vtype or null */
1635 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
1637 arg = (gpointer*)nullable_buf;
1643 case MONO_TYPE_VALUETYPE:
1644 switch (ainfo->storage) {
1645 case ArgVtypeInIRegs:
1646 for (i = 0; i < ainfo->nregs; ++i)
1647 p->regs [slot ++] = ((mgreg_t*)arg) [i];
1650 if (ainfo->esize == 4) {
1651 for (i = 0; i < ainfo->nregs; ++i)
1652 p->fpregs [ainfo->reg + i] = bitcast_r4_to_r8 (((float*)arg) [ainfo->foffsets [i] / 4]);
1654 for (i = 0; i < ainfo->nregs; ++i)
1655 p->fpregs [ainfo->reg + i] = ((double*)arg) [ainfo->foffsets [i] / 8];
1657 p->n_fpargs += ainfo->nregs;
1660 p->regs [slot] = (mgreg_t)arg;
1663 g_assert_not_reached ();
1668 g_assert_not_reached ();
1674 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
1676 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
1677 CallInfo *cinfo = ainfo->cinfo;
1678 DynCallArgs *args = (DynCallArgs*)buf;
1679 MonoType *ptype = ainfo->rtype;
1680 guint8 *ret = args->ret;
1681 mgreg_t res = args->res;
1682 mgreg_t res2 = args->res2;
1685 if (cinfo->ret.storage == ArgVtypeByRef)
1688 switch (ptype->type) {
1689 case MONO_TYPE_VOID:
1690 *(gpointer*)ret = NULL;
1692 case MONO_TYPE_STRING:
1693 case MONO_TYPE_CLASS:
1694 case MONO_TYPE_ARRAY:
1695 case MONO_TYPE_SZARRAY:
1696 case MONO_TYPE_OBJECT:
1700 *(gpointer*)ret = (gpointer)res;
1706 case MONO_TYPE_BOOLEAN:
1707 *(guint8*)ret = res;
1710 *(gint16*)ret = res;
1713 case MONO_TYPE_CHAR:
1714 *(guint16*)ret = res;
1717 *(gint32*)ret = res;
1720 *(guint32*)ret = res;
1724 *(guint64*)ret = res;
1727 *(float*)ret = bitcast_r8_to_r4 (args->fpregs [0]);
1730 *(double*)ret = args->fpregs [0];
1732 case MONO_TYPE_GENERICINST:
1733 if (MONO_TYPE_IS_REFERENCE (ptype)) {
1734 *(gpointer*)ret = (gpointer)res;
1739 case MONO_TYPE_VALUETYPE:
1740 switch (ainfo->cinfo->ret.storage) {
1741 case ArgVtypeInIRegs:
1742 *(mgreg_t*)ret = res;
1743 if (ainfo->cinfo->ret.nregs > 1)
1744 ((mgreg_t*)ret) [1] = res2;
1747 /* Use the same area for returning fp values */
1748 if (cinfo->ret.esize == 4) {
1749 for (i = 0; i < cinfo->ret.nregs; ++i)
1750 ((float*)ret) [cinfo->ret.foffsets [i] / 4] = bitcast_r8_to_r4 (args->fpregs [i]);
1752 for (i = 0; i < cinfo->ret.nregs; ++i)
1753 ((double*)ret) [cinfo->ret.foffsets [i] / 8] = args->fpregs [i];
1757 g_assert_not_reached ();
1762 g_assert_not_reached ();
1767 void sys_icache_invalidate (void *start, size_t len);
1771 mono_arch_flush_icache (guint8 *code, gint size)
1773 #ifndef MONO_CROSS_COMPILE
1775 sys_icache_invalidate (code, size);
1777 __clear_cache (code, code + size);
1785 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
1792 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1797 for (i = 0; i < cfg->num_varinfo; i++) {
1798 MonoInst *ins = cfg->varinfo [i];
1799 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1802 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1805 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1806 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1809 if (mono_is_regsize_var (ins->inst_vtype)) {
1810 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1811 g_assert (i == vmv->idx);
1812 vars = g_list_prepend (vars, vmv);
1816 vars = mono_varlist_sort (cfg, vars, 0);
1822 mono_arch_get_global_int_regs (MonoCompile *cfg)
1827 /* r28 is reserved for cfg->arch.args_reg */
1828 /* r27 is reserved for the imt argument */
1829 for (i = ARMREG_R19; i <= ARMREG_R26; ++i)
1830 regs = g_list_prepend (regs, GUINT_TO_POINTER (i));
1836 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1838 MonoInst *ins = cfg->varinfo [vmv->idx];
1840 if (ins->opcode == OP_ARG)
1847 mono_arch_create_vars (MonoCompile *cfg)
1849 MonoMethodSignature *sig;
1852 sig = mono_method_signature (cfg->method);
1853 if (!cfg->arch.cinfo)
1854 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1855 cinfo = cfg->arch.cinfo;
1857 if (cinfo->ret.storage == ArgVtypeByRef) {
1858 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1859 cfg->vret_addr->flags |= MONO_INST_VOLATILE;
1862 if (cfg->gen_sdb_seq_points) {
1865 if (cfg->compile_aot) {
1866 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1867 ins->flags |= MONO_INST_VOLATILE;
1868 cfg->arch.seq_point_info_var = ins;
1871 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1872 ins->flags |= MONO_INST_VOLATILE;
1873 cfg->arch.ss_tramp_var = ins;
1875 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1876 ins->flags |= MONO_INST_VOLATILE;
1877 cfg->arch.bp_tramp_var = ins;
1880 if (cfg->method->save_lmf) {
1881 cfg->create_lmf_var = TRUE;
1884 cfg->lmf_ir_mono_lmf = TRUE;
1890 mono_arch_allocate_vars (MonoCompile *cfg)
1892 MonoMethodSignature *sig;
1896 int i, offset, size, align;
1897 guint32 locals_stack_size, locals_stack_align;
1901 * Allocate arguments and locals to either register (OP_REGVAR) or to a stack slot (OP_REGOFFSET).
1902 * Compute cfg->stack_offset and update cfg->used_int_regs.
1905 sig = mono_method_signature (cfg->method);
1907 if (!cfg->arch.cinfo)
1908 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1909 cinfo = cfg->arch.cinfo;
1912 * The ARM64 ABI always uses a frame pointer.
1913 * The instruction set prefers positive offsets, so fp points to the bottom of the
1914 * frame, and stack slots are at positive offsets.
1915 * If some arguments are received on the stack, their offsets relative to fp can
1916 * not be computed right now because the stack frame might grow due to spilling
1917 * done by the local register allocator. To solve this, we reserve a register
1918 * which points to them.
1919 * The stack frame looks like this:
1920 * args_reg -> <bottom of parent frame>
1922 * fp -> <saved fp+lr>
1923 * sp -> <localloc/params area>
1925 cfg->frame_reg = ARMREG_FP;
1926 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1932 if (cinfo->stack_usage) {
1933 g_assert (!(cfg->used_int_regs & (1 << ARMREG_R28)));
1934 cfg->arch.args_reg = ARMREG_R28;
1935 cfg->used_int_regs |= 1 << ARMREG_R28;
1938 if (cfg->method->save_lmf) {
1939 /* The LMF var is allocated normally */
1941 /* Callee saved regs */
1942 cfg->arch.saved_gregs_offset = offset;
1943 for (i = 0; i < 32; ++i)
1944 if ((MONO_ARCH_CALLEE_SAVED_REGS & (1 << i)) && (cfg->used_int_regs & (1 << i)))
1949 switch (cinfo->ret.storage) {
1955 cfg->ret->opcode = OP_REGVAR;
1956 cfg->ret->dreg = cinfo->ret.reg;
1958 case ArgVtypeInIRegs:
1960 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1961 cfg->ret->opcode = OP_REGOFFSET;
1962 cfg->ret->inst_basereg = cfg->frame_reg;
1963 cfg->ret->inst_offset = offset;
1964 if (cinfo->ret.storage == ArgHFA)
1971 /* This variable will be initalized in the prolog from R8 */
1972 cfg->vret_addr->opcode = OP_REGOFFSET;
1973 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1974 cfg->vret_addr->inst_offset = offset;
1976 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1977 printf ("vret_addr =");
1978 mono_print_ins (cfg->vret_addr);
1982 g_assert_not_reached ();
1987 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1988 ainfo = cinfo->args + i;
1990 ins = cfg->args [i];
1991 if (ins->opcode == OP_REGVAR)
1994 ins->opcode = OP_REGOFFSET;
1995 ins->inst_basereg = cfg->frame_reg;
1997 switch (ainfo->storage) {
2001 // FIXME: Use nregs/size
2002 /* These will be copied to the stack in the prolog */
2003 ins->inst_offset = offset;
2009 case ArgVtypeOnStack:
2010 /* These are in the parent frame */
2011 g_assert (cfg->arch.args_reg);
2012 ins->inst_basereg = cfg->arch.args_reg;
2013 ins->inst_offset = ainfo->offset;
2015 case ArgVtypeInIRegs:
2017 ins->opcode = OP_REGOFFSET;
2018 ins->inst_basereg = cfg->frame_reg;
2019 /* These arguments are saved to the stack in the prolog */
2020 ins->inst_offset = offset;
2021 if (cfg->verbose_level >= 2)
2022 printf ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2023 if (ainfo->storage == ArgHFA)
2029 case ArgVtypeByRefOnStack: {
2032 if (ainfo->gsharedvt) {
2033 ins->opcode = OP_REGOFFSET;
2034 ins->inst_basereg = cfg->arch.args_reg;
2035 ins->inst_offset = ainfo->offset;
2039 /* The vtype address is in the parent frame */
2040 g_assert (cfg->arch.args_reg);
2041 MONO_INST_NEW (cfg, vtaddr, 0);
2042 vtaddr->opcode = OP_REGOFFSET;
2043 vtaddr->inst_basereg = cfg->arch.args_reg;
2044 vtaddr->inst_offset = ainfo->offset;
2046 /* Need an indirection */
2047 ins->opcode = OP_VTARG_ADDR;
2048 ins->inst_left = vtaddr;
2051 case ArgVtypeByRef: {
2054 if (ainfo->gsharedvt) {
2055 ins->opcode = OP_REGOFFSET;
2056 ins->inst_basereg = cfg->frame_reg;
2057 ins->inst_offset = offset;
2062 /* The vtype address is in a register, will be copied to the stack in the prolog */
2063 MONO_INST_NEW (cfg, vtaddr, 0);
2064 vtaddr->opcode = OP_REGOFFSET;
2065 vtaddr->inst_basereg = cfg->frame_reg;
2066 vtaddr->inst_offset = offset;
2069 /* Need an indirection */
2070 ins->opcode = OP_VTARG_ADDR;
2071 ins->inst_left = vtaddr;
2075 g_assert_not_reached ();
2080 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
2081 // FIXME: Allocate these to registers
2082 ins = cfg->arch.seq_point_info_var;
2086 offset += align - 1;
2087 offset &= ~(align - 1);
2088 ins->opcode = OP_REGOFFSET;
2089 ins->inst_basereg = cfg->frame_reg;
2090 ins->inst_offset = offset;
2093 ins = cfg->arch.ss_tramp_var;
2097 offset += align - 1;
2098 offset &= ~(align - 1);
2099 ins->opcode = OP_REGOFFSET;
2100 ins->inst_basereg = cfg->frame_reg;
2101 ins->inst_offset = offset;
2104 ins = cfg->arch.bp_tramp_var;
2108 offset += align - 1;
2109 offset &= ~(align - 1);
2110 ins->opcode = OP_REGOFFSET;
2111 ins->inst_basereg = cfg->frame_reg;
2112 ins->inst_offset = offset;
2117 offsets = mono_allocate_stack_slots (cfg, FALSE, &locals_stack_size, &locals_stack_align);
2118 if (locals_stack_align)
2119 offset = ALIGN_TO (offset, locals_stack_align);
2121 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
2122 if (offsets [i] != -1) {
2123 ins = cfg->varinfo [i];
2124 ins->opcode = OP_REGOFFSET;
2125 ins->inst_basereg = cfg->frame_reg;
2126 ins->inst_offset = offset + offsets [i];
2127 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
2130 offset += locals_stack_size;
2132 offset = ALIGN_TO (offset, MONO_ARCH_FRAME_ALIGNMENT);
2134 cfg->stack_offset = offset;
2139 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2144 LLVMCallInfo *linfo;
2146 n = sig->param_count + sig->hasthis;
2148 cinfo = get_call_info (cfg->mempool, sig);
2150 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2152 switch (cinfo->ret.storage) {
2159 linfo->ret.storage = LLVMArgVtypeByRef;
2162 // FIXME: This doesn't work yet since the llvm backend represents these types as an i8
2163 // array which is returned in int regs
2166 linfo->ret.storage = LLVMArgFpStruct;
2167 linfo->ret.nslots = cinfo->ret.nregs;
2168 linfo->ret.esize = cinfo->ret.esize;
2170 case ArgVtypeInIRegs:
2171 /* LLVM models this by returning an int */
2172 linfo->ret.storage = LLVMArgVtypeAsScalar;
2173 linfo->ret.nslots = cinfo->ret.nregs;
2174 linfo->ret.esize = cinfo->ret.esize;
2177 g_assert_not_reached ();
2181 for (i = 0; i < n; ++i) {
2182 LLVMArgInfo *lainfo = &linfo->args [i];
2184 ainfo = cinfo->args + i;
2186 lainfo->storage = LLVMArgNone;
2188 switch (ainfo->storage) {
2195 lainfo->storage = LLVMArgNormal;
2198 case ArgVtypeByRefOnStack:
2199 lainfo->storage = LLVMArgVtypeByRef;
2204 lainfo->storage = LLVMArgAsFpArgs;
2205 lainfo->nslots = ainfo->nregs;
2206 lainfo->esize = ainfo->esize;
2207 for (j = 0; j < ainfo->nregs; ++j)
2208 lainfo->pair_storage [j] = LLVMArgInFPReg;
2211 case ArgVtypeInIRegs:
2212 lainfo->storage = LLVMArgAsIArgs;
2213 lainfo->nslots = ainfo->nregs;
2215 case ArgVtypeOnStack:
2219 lainfo->storage = LLVMArgAsFpArgs;
2220 lainfo->nslots = ainfo->nregs;
2221 lainfo->esize = ainfo->esize;
2222 lainfo->ndummy_fpargs = ainfo->nfregs_to_skip;
2223 for (j = 0; j < ainfo->nregs; ++j)
2224 lainfo->pair_storage [j] = LLVMArgInFPReg;
2226 lainfo->storage = LLVMArgAsIArgs;
2227 lainfo->nslots = ainfo->size / 8;
2231 g_assert_not_reached ();
2241 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2247 MONO_INST_NEW (cfg, ins, OP_MOVE);
2248 ins->dreg = mono_alloc_ireg_copy (cfg, arg->dreg);
2249 ins->sreg1 = arg->dreg;
2250 MONO_ADD_INS (cfg->cbb, ins);
2251 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2254 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2255 ins->dreg = mono_alloc_freg (cfg);
2256 ins->sreg1 = arg->dreg;
2257 MONO_ADD_INS (cfg->cbb, ins);
2258 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2261 if (COMPILE_LLVM (cfg))
2262 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2264 MONO_INST_NEW (cfg, ins, OP_RMOVE);
2266 MONO_INST_NEW (cfg, ins, OP_ARM_SETFREG_R4);
2267 ins->dreg = mono_alloc_freg (cfg);
2268 ins->sreg1 = arg->dreg;
2269 MONO_ADD_INS (cfg->cbb, ins);
2270 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2273 g_assert_not_reached ();
2279 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2281 MonoMethodSignature *tmp_sig;
2284 if (call->tail_call)
2287 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2290 * mono_ArgIterator_Setup assumes the signature cookie is
2291 * passed first and all the arguments which were before it are
2292 * passed on the stack after the signature. So compensate by
2293 * passing a different signature.
2295 tmp_sig = mono_metadata_signature_dup (call->signature);
2296 tmp_sig->param_count -= call->signature->sentinelpos;
2297 tmp_sig->sentinelpos = 0;
2298 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2300 sig_reg = mono_alloc_ireg (cfg);
2301 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2303 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2307 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2309 MonoMethodSignature *sig;
2310 MonoInst *arg, *vtarg;
2315 sig = call->signature;
2317 cinfo = get_call_info (cfg->mempool, sig);
2319 switch (cinfo->ret.storage) {
2320 case ArgVtypeInIRegs:
2323 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2324 * the location pointed to by it after call in emit_move_return_value ().
2326 if (!cfg->arch.vret_addr_loc) {
2327 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2328 /* Prevent it from being register allocated or optimized away */
2329 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2332 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2335 /* Pass the vtype return address in R8 */
2336 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2337 vtarg->sreg1 = call->vret_var->dreg;
2338 vtarg->dreg = mono_alloc_preg (cfg);
2339 MONO_ADD_INS (cfg->cbb, vtarg);
2341 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2347 for (i = 0; i < cinfo->nargs; ++i) {
2348 ainfo = cinfo->args + i;
2349 arg = call->args [i];
2351 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2352 /* Emit the signature cookie just before the implicit arguments */
2353 emit_sig_cookie (cfg, call, cinfo);
2356 switch (ainfo->storage) {
2360 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, arg);
2363 switch (ainfo->slot_size) {
2365 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2368 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2371 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI2_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2374 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI1_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2377 g_assert_not_reached ();
2382 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2385 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2387 case ArgVtypeInIRegs:
2389 case ArgVtypeByRefOnStack:
2390 case ArgVtypeOnStack:
2396 size = mono_class_value_size (arg->klass, &align);
2398 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2399 ins->sreg1 = arg->dreg;
2400 ins->klass = arg->klass;
2401 ins->backend.size = size;
2402 ins->inst_p0 = call;
2403 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2404 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2405 MONO_ADD_INS (cfg->cbb, ins);
2409 g_assert_not_reached ();
2414 /* Handle the case where there are no implicit arguments */
2415 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (cinfo->nargs == sig->sentinelpos))
2416 emit_sig_cookie (cfg, call, cinfo);
2418 call->call_info = cinfo;
2419 call->stack_usage = cinfo->stack_usage;
2423 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2425 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2426 ArgInfo *ainfo = ins->inst_p1;
2430 if (ins->backend.size == 0 && !ainfo->gsharedvt)
2433 switch (ainfo->storage) {
2434 case ArgVtypeInIRegs:
2435 for (i = 0; i < ainfo->nregs; ++i) {
2436 // FIXME: Smaller sizes
2437 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
2438 load->dreg = mono_alloc_ireg (cfg);
2439 load->inst_basereg = src->dreg;
2440 load->inst_offset = i * sizeof(mgreg_t);
2441 MONO_ADD_INS (cfg->cbb, load);
2442 add_outarg_reg (cfg, call, ArgInIReg, ainfo->reg + i, load);
2446 for (i = 0; i < ainfo->nregs; ++i) {
2447 if (ainfo->esize == 4)
2448 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2450 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2451 load->dreg = mono_alloc_freg (cfg);
2452 load->inst_basereg = src->dreg;
2453 load->inst_offset = ainfo->foffsets [i];
2454 MONO_ADD_INS (cfg->cbb, load);
2455 add_outarg_reg (cfg, call, ainfo->esize == 4 ? ArgInFRegR4 : ArgInFReg, ainfo->reg + i, load);
2459 case ArgVtypeByRefOnStack: {
2460 MonoInst *vtaddr, *load, *arg;
2462 /* Pass the vtype address in a reg/on the stack */
2463 if (ainfo->gsharedvt) {
2466 /* Make a copy of the argument */
2467 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2469 MONO_INST_NEW (cfg, load, OP_LDADDR);
2470 load->inst_p0 = vtaddr;
2471 vtaddr->flags |= MONO_INST_INDIRECT;
2472 load->type = STACK_MP;
2473 load->klass = vtaddr->klass;
2474 load->dreg = mono_alloc_ireg (cfg);
2475 MONO_ADD_INS (cfg->cbb, load);
2476 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, ainfo->size, 8);
2479 if (ainfo->storage == ArgVtypeByRef) {
2480 MONO_INST_NEW (cfg, arg, OP_MOVE);
2481 arg->dreg = mono_alloc_preg (cfg);
2482 arg->sreg1 = load->dreg;
2483 MONO_ADD_INS (cfg->cbb, arg);
2484 add_outarg_reg (cfg, call, ArgInIReg, ainfo->reg, arg);
2486 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, load->dreg);
2490 case ArgVtypeOnStack:
2491 for (i = 0; i < ainfo->size / 8; ++i) {
2492 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
2493 load->dreg = mono_alloc_ireg (cfg);
2494 load->inst_basereg = src->dreg;
2495 load->inst_offset = i * 8;
2496 MONO_ADD_INS (cfg->cbb, load);
2497 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset + (i * 8), load->dreg);
2501 g_assert_not_reached ();
2507 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2509 MonoMethodSignature *sig;
2512 sig = mono_method_signature (cfg->method);
2513 if (!cfg->arch.cinfo)
2514 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2515 cinfo = cfg->arch.cinfo;
2517 switch (cinfo->ret.storage) {
2521 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2524 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2527 if (COMPILE_LLVM (cfg))
2528 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2530 MONO_EMIT_NEW_UNALU (cfg, OP_RMOVE, cfg->ret->dreg, val->dreg);
2532 MONO_EMIT_NEW_UNALU (cfg, OP_ARM_SETFREG_R4, cfg->ret->dreg, val->dreg);
2535 g_assert_not_reached ();
2541 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
2546 if (cfg->compile_aot && !cfg->full_aot)
2547 /* OP_TAILCALL doesn't work with AOT */
2550 c1 = get_call_info (NULL, caller_sig);
2551 c2 = get_call_info (NULL, callee_sig);
2553 // FIXME: Relax these restrictions
2554 if (c1->stack_usage != 0)
2556 if (c1->stack_usage != c2->stack_usage)
2558 if ((c1->ret.storage != ArgNone && c1->ret.storage != ArgInIReg) || c1->ret.storage != c2->ret.storage)
2568 mono_arch_is_inst_imm (gint64 imm)
2570 return (imm >= -((gint64)1<<31) && imm <= (((gint64)1<<31)-1));
2574 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2581 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2588 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2594 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2599 #define ADD_NEW_INS(cfg,dest,op) do { \
2600 MONO_INST_NEW ((cfg), (dest), (op)); \
2601 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2605 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2607 MonoInst *ins, *temp, *last_ins = NULL;
2609 MONO_BB_FOR_EACH_INS (bb, ins) {
2610 switch (ins->opcode) {
2615 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
2616 /* ARM sets the C flag to 1 if there was _no_ overflow */
2617 ins->next->opcode = OP_COND_EXC_NC;
2621 case OP_IDIV_UN_IMM:
2622 case OP_IREM_UN_IMM:
2624 mono_decompose_op_imm (cfg, bb, ins);
2626 case OP_LOCALLOC_IMM:
2627 if (ins->inst_imm > 32) {
2628 ADD_NEW_INS (cfg, temp, OP_ICONST);
2629 temp->inst_c0 = ins->inst_imm;
2630 temp->dreg = mono_alloc_ireg (cfg);
2631 ins->sreg1 = temp->dreg;
2632 ins->opcode = mono_op_imm_to_op (ins->opcode);
2635 case OP_ICOMPARE_IMM:
2636 if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_IBEQ) {
2637 ins->next->opcode = OP_ARM64_CBZW;
2638 ins->next->sreg1 = ins->sreg1;
2640 } else if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_IBNE_UN) {
2641 ins->next->opcode = OP_ARM64_CBNZW;
2642 ins->next->sreg1 = ins->sreg1;
2646 case OP_LCOMPARE_IMM:
2647 case OP_COMPARE_IMM:
2648 if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_LBEQ) {
2649 ins->next->opcode = OP_ARM64_CBZX;
2650 ins->next->sreg1 = ins->sreg1;
2652 } else if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_LBNE_UN) {
2653 ins->next->opcode = OP_ARM64_CBNZX;
2654 ins->next->sreg1 = ins->sreg1;
2659 gboolean swap = FALSE;
2663 /* Optimized away */
2669 * FP compares with unordered operands set the flags
2670 * to NZCV=0011, which matches some non-unordered compares
2671 * as well, like LE, so have to swap the operands.
2673 switch (ins->next->opcode) {
2675 ins->next->opcode = OP_FBGT;
2679 ins->next->opcode = OP_FBGE;
2687 ins->sreg1 = ins->sreg2;
2698 bb->last_ins = last_ins;
2699 bb->max_vreg = cfg->next_vreg;
2703 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
2708 opcode_to_armcond (int opcode)
2719 case OP_COND_EXC_IEQ:
2720 case OP_COND_EXC_EQ:
2737 case OP_COND_EXC_IGT:
2738 case OP_COND_EXC_GT:
2753 case OP_COND_EXC_ILT:
2754 case OP_COND_EXC_LT:
2762 case OP_COND_EXC_INE_UN:
2763 case OP_COND_EXC_NE_UN:
2769 case OP_COND_EXC_IGE_UN:
2770 case OP_COND_EXC_GE_UN:
2780 case OP_COND_EXC_IGT_UN:
2781 case OP_COND_EXC_GT_UN:
2787 case OP_COND_EXC_ILE_UN:
2788 case OP_COND_EXC_LE_UN:
2796 case OP_COND_EXC_ILT_UN:
2797 case OP_COND_EXC_LT_UN:
2800 * FCMP sets the NZCV condition bits as follows:
2805 * ARMCOND_LT is N!=V, so it matches unordered too, so
2806 * fclt and fclt_un need to be special cased.
2816 case OP_COND_EXC_IC:
2818 case OP_COND_EXC_OV:
2819 case OP_COND_EXC_IOV:
2821 case OP_COND_EXC_NC:
2822 case OP_COND_EXC_INC:
2824 case OP_COND_EXC_NO:
2825 case OP_COND_EXC_INO:
2828 printf ("%s\n", mono_inst_name (opcode));
2829 g_assert_not_reached ();
2834 /* This clobbers LR */
2835 static inline __attribute__((warn_unused_result)) guint8*
2836 emit_cond_exc (MonoCompile *cfg, guint8 *code, int opcode, const char *exc_name)
2840 cond = opcode_to_armcond (opcode);
2842 arm_adrx (code, ARMREG_IP1, code);
2843 mono_add_patch_info_rel (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, exc_name, MONO_R_ARM64_BCC);
2844 arm_bcc (code, cond, 0);
2849 emit_move_return_value (MonoCompile *cfg, guint8 * code, MonoInst *ins)
2854 call = (MonoCallInst*)ins;
2855 cinfo = call->call_info;
2857 switch (cinfo->ret.storage) {
2861 /* LLVM compiled code might only set the bottom bits */
2862 if (call->signature && mini_get_underlying_type (call->signature->ret)->type == MONO_TYPE_I4)
2863 arm_sxtwx (code, call->inst.dreg, cinfo->ret.reg);
2864 else if (call->inst.dreg != cinfo->ret.reg)
2865 arm_movx (code, call->inst.dreg, cinfo->ret.reg);
2868 if (call->inst.dreg != cinfo->ret.reg)
2869 arm_fmovd (code, call->inst.dreg, cinfo->ret.reg);
2873 arm_fmovs (code, call->inst.dreg, cinfo->ret.reg);
2875 arm_fcvt_sd (code, call->inst.dreg, cinfo->ret.reg);
2877 case ArgVtypeInIRegs: {
2878 MonoInst *loc = cfg->arch.vret_addr_loc;
2881 /* Load the destination address */
2882 g_assert (loc && loc->opcode == OP_REGOFFSET);
2883 code = emit_ldrx (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
2884 for (i = 0; i < cinfo->ret.nregs; ++i)
2885 arm_strx (code, cinfo->ret.reg + i, ARMREG_LR, i * 8);
2889 MonoInst *loc = cfg->arch.vret_addr_loc;
2892 /* Load the destination address */
2893 g_assert (loc && loc->opcode == OP_REGOFFSET);
2894 code = emit_ldrx (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
2895 for (i = 0; i < cinfo->ret.nregs; ++i) {
2896 if (cinfo->ret.esize == 4)
2897 arm_strfpw (code, cinfo->ret.reg + i, ARMREG_LR, cinfo->ret.foffsets [i]);
2899 arm_strfpx (code, cinfo->ret.reg + i, ARMREG_LR, cinfo->ret.foffsets [i]);
2906 g_assert_not_reached ();
2913 * emit_branch_island:
2915 * Emit a branch island for the conditional branches from cfg->native_code + start_offset to code.
2918 emit_branch_island (MonoCompile *cfg, guint8 *code, int start_offset)
2921 int offset, island_size;
2923 /* Iterate over the patch infos added so far by this bb */
2925 for (ji = cfg->patch_info; ji; ji = ji->next) {
2926 if (ji->ip.i < start_offset)
2927 /* The patch infos are in reverse order, so this means the end */
2929 if (ji->relocation == MONO_R_ARM64_BCC || ji->relocation == MONO_R_ARM64_CBZ)
2934 offset = code - cfg->native_code;
2935 if (offset > (cfg->code_size - island_size - 16)) {
2936 cfg->code_size *= 2;
2937 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2938 code = cfg->native_code + offset;
2941 /* Branch over the island */
2942 arm_b (code, code + 4 + island_size);
2944 for (ji = cfg->patch_info; ji; ji = ji->next) {
2945 if (ji->ip.i < start_offset)
2947 if (ji->relocation == MONO_R_ARM64_BCC || ji->relocation == MONO_R_ARM64_CBZ) {
2948 /* Rewrite the cond branch so it branches to an uncoditional branch in the branch island */
2949 arm_patch_rel (cfg->native_code + ji->ip.i, code, ji->relocation);
2950 /* Rewrite the patch so it points to the unconditional branch */
2951 ji->ip.i = code - cfg->native_code;
2952 ji->relocation = MONO_R_ARM64_B;
2961 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2966 guint8 *code = cfg->native_code + cfg->code_len;
2967 int start_offset, max_len, dreg, sreg1, sreg2;
2970 if (cfg->verbose_level > 2)
2971 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2973 start_offset = code - cfg->native_code;
2975 MONO_BB_FOR_EACH_INS (bb, ins) {
2976 offset = code - cfg->native_code;
2978 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2980 if (offset > (cfg->code_size - max_len - 16)) {
2981 cfg->code_size *= 2;
2982 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2983 code = cfg->native_code + offset;
2986 if (G_UNLIKELY (cfg->arch.cond_branch_islands && offset - start_offset > 4 * 0x1ffff)) {
2987 /* Emit a branch island for large basic blocks */
2988 code = emit_branch_island (cfg, code, start_offset);
2989 offset = code - cfg->native_code;
2990 start_offset = offset;
2993 mono_debug_record_line_number (cfg, ins, offset);
2998 imm = ins->inst_imm;
3000 switch (ins->opcode) {
3002 code = emit_imm (code, dreg, ins->inst_c0);
3005 code = emit_imm64 (code, dreg, ins->inst_c0);
3009 arm_movx (code, dreg, sreg1);
3012 case OP_RELAXED_NOP:
3015 mono_add_patch_info_rel (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0, MONO_R_ARM64_IMM);
3016 code = emit_imm64_template (code, dreg);
3020 * gdb does not like encountering the hw breakpoint ins in the debugged code.
3021 * So instead of emitting a trap, we emit a call a C function and place a
3024 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_break");
3029 arm_addx_imm (code, ARMREG_IP0, sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
3030 // FIXME: andx_imm doesn't work yet
3031 code = emit_imm (code, ARMREG_IP1, -MONO_ARCH_FRAME_ALIGNMENT);
3032 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
3033 //arm_andx_imm (code, ARMREG_IP0, sreg1, - MONO_ARCH_FRAME_ALIGNMENT);
3034 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
3035 arm_subx (code, ARMREG_IP1, ARMREG_IP1, ARMREG_IP0);
3036 arm_movspx (code, ARMREG_SP, ARMREG_IP1);
3039 /* ip1 = pointer, ip0 = end */
3040 arm_addx (code, ARMREG_IP0, ARMREG_IP1, ARMREG_IP0);
3042 arm_cmpx (code, ARMREG_IP1, ARMREG_IP0);
3044 arm_bcc (code, ARMCOND_EQ, 0);
3045 arm_stpx (code, ARMREG_RZR, ARMREG_RZR, ARMREG_IP1, 0);
3046 arm_addx_imm (code, ARMREG_IP1, ARMREG_IP1, 16);
3047 arm_b (code, buf [0]);
3048 arm_patch_rel (buf [1], code, MONO_R_ARM64_BCC);
3050 arm_movspx (code, dreg, ARMREG_SP);
3051 if (cfg->param_area)
3052 code = emit_subx_sp_imm (code, cfg->param_area);
3055 case OP_LOCALLOC_IMM: {
3058 imm = ALIGN_TO (ins->inst_imm, MONO_ARCH_FRAME_ALIGNMENT);
3059 g_assert (arm_is_arith_imm (imm));
3060 arm_subx_imm (code, ARMREG_SP, ARMREG_SP, imm);
3063 g_assert (MONO_ARCH_FRAME_ALIGNMENT == 16);
3065 while (offset < imm) {
3066 arm_stpx (code, ARMREG_RZR, ARMREG_RZR, ARMREG_SP, offset);
3069 arm_movspx (code, dreg, ARMREG_SP);
3070 if (cfg->param_area)
3071 code = emit_subx_sp_imm (code, cfg->param_area);
3075 code = emit_aotconst (cfg, code, dreg, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3077 case OP_OBJC_GET_SELECTOR:
3078 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
3079 /* See arch_emit_objc_selector_ref () in aot-compiler.c */
3080 arm_ldrx_lit (code, ins->dreg, 0);
3084 case OP_SEQ_POINT: {
3085 MonoInst *info_var = cfg->arch.seq_point_info_var;
3088 * For AOT, we use one got slot per method, which will point to a
3089 * SeqPointInfo structure, containing all the information required
3090 * by the code below.
3092 if (cfg->compile_aot) {
3093 g_assert (info_var);
3094 g_assert (info_var->opcode == OP_REGOFFSET);
3097 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3098 MonoInst *var = cfg->arch.ss_tramp_var;
3101 g_assert (var->opcode == OP_REGOFFSET);
3102 /* Load ss_tramp_var */
3103 /* This is equal to &ss_trampoline */
3104 arm_ldrx (code, ARMREG_IP1, var->inst_basereg, var->inst_offset);
3105 /* Load the trampoline address */
3106 arm_ldrx (code, ARMREG_IP1, ARMREG_IP1, 0);
3107 /* Call it if it is non-null */
3108 arm_cbzx (code, ARMREG_IP1, code + 8);
3109 arm_blrx (code, ARMREG_IP1);
3112 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3114 if (cfg->compile_aot) {
3115 guint32 offset = code - cfg->native_code;
3118 arm_ldrx (code, ARMREG_IP1, info_var->inst_basereg, info_var->inst_offset);
3119 /* Add the offset */
3120 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
3121 /* Load the info->bp_addrs [offset], which is either 0 or the address of the bp trampoline */
3122 code = emit_ldrx (code, ARMREG_IP1, ARMREG_IP1, val);
3123 /* Skip the load if its 0 */
3124 arm_cbzx (code, ARMREG_IP1, code + 8);
3125 /* Call the breakpoint trampoline */
3126 arm_blrx (code, ARMREG_IP1);
3128 MonoInst *var = cfg->arch.bp_tramp_var;
3131 g_assert (var->opcode == OP_REGOFFSET);
3132 /* Load the address of the bp trampoline into IP0 */
3133 arm_ldrx (code, ARMREG_IP0, var->inst_basereg, var->inst_offset);
3135 * A placeholder for a possible breakpoint inserted by
3136 * mono_arch_set_breakpoint ().
3145 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb, MONO_R_ARM64_B);
3149 arm_brx (code, sreg1);
3181 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3182 cond = opcode_to_armcond (ins->opcode);
3183 arm_bcc (code, cond, 0);
3187 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3188 /* For fp compares, ARMCOND_LT is lt or unordered */
3189 arm_bcc (code, ARMCOND_LT, 0);
3192 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3193 arm_bcc (code, ARMCOND_EQ, 0);
3194 offset = code - cfg->native_code;
3195 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3196 /* For fp compares, ARMCOND_LT is lt or unordered */
3197 arm_bcc (code, ARMCOND_LT, 0);
3200 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3201 arm_cbzw (code, sreg1, 0);
3204 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3205 arm_cbzx (code, sreg1, 0);
3207 case OP_ARM64_CBNZW:
3208 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3209 arm_cbnzw (code, sreg1, 0);
3211 case OP_ARM64_CBNZX:
3212 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3213 arm_cbnzx (code, sreg1, 0);
3217 arm_addw (code, dreg, sreg1, sreg2);
3220 arm_addx (code, dreg, sreg1, sreg2);
3223 arm_subw (code, dreg, sreg1, sreg2);
3226 arm_subx (code, dreg, sreg1, sreg2);
3229 arm_andw (code, dreg, sreg1, sreg2);
3232 arm_andx (code, dreg, sreg1, sreg2);
3235 arm_orrw (code, dreg, sreg1, sreg2);
3238 arm_orrx (code, dreg, sreg1, sreg2);
3241 arm_eorw (code, dreg, sreg1, sreg2);
3244 arm_eorx (code, dreg, sreg1, sreg2);
3247 arm_negw (code, dreg, sreg1);
3250 arm_negx (code, dreg, sreg1);
3253 arm_mvnw (code, dreg, sreg1);
3256 arm_mvnx (code, dreg, sreg1);
3259 arm_addsw (code, dreg, sreg1, sreg2);
3263 arm_addsx (code, dreg, sreg1, sreg2);
3266 arm_subsw (code, dreg, sreg1, sreg2);
3270 arm_subsx (code, dreg, sreg1, sreg2);
3273 arm_cmpw (code, sreg1, sreg2);
3277 arm_cmpx (code, sreg1, sreg2);
3280 code = emit_addw_imm (code, dreg, sreg1, imm);
3284 code = emit_addx_imm (code, dreg, sreg1, imm);
3287 code = emit_subw_imm (code, dreg, sreg1, imm);
3290 code = emit_subx_imm (code, dreg, sreg1, imm);
3293 code = emit_andw_imm (code, dreg, sreg1, imm);
3297 code = emit_andx_imm (code, dreg, sreg1, imm);
3300 code = emit_orrw_imm (code, dreg, sreg1, imm);
3303 code = emit_orrx_imm (code, dreg, sreg1, imm);
3306 code = emit_eorw_imm (code, dreg, sreg1, imm);
3309 code = emit_eorx_imm (code, dreg, sreg1, imm);
3311 case OP_ICOMPARE_IMM:
3312 code = emit_cmpw_imm (code, sreg1, imm);
3314 case OP_LCOMPARE_IMM:
3315 case OP_COMPARE_IMM:
3317 arm_cmpx (code, sreg1, ARMREG_RZR);
3319 // FIXME: 32 vs 64 bit issues for 0xffffffff
3320 code = emit_imm64 (code, ARMREG_LR, imm);
3321 arm_cmpx (code, sreg1, ARMREG_LR);
3325 arm_lslvw (code, dreg, sreg1, sreg2);
3328 arm_lslvx (code, dreg, sreg1, sreg2);
3331 arm_asrvw (code, dreg, sreg1, sreg2);
3334 arm_asrvx (code, dreg, sreg1, sreg2);
3337 arm_lsrvw (code, dreg, sreg1, sreg2);
3340 arm_lsrvx (code, dreg, sreg1, sreg2);
3344 arm_movx (code, dreg, sreg1);
3346 arm_lslw (code, dreg, sreg1, imm);
3350 arm_movx (code, dreg, sreg1);
3352 arm_lslx (code, dreg, sreg1, imm);
3356 arm_movx (code, dreg, sreg1);
3358 arm_asrw (code, dreg, sreg1, imm);
3363 arm_movx (code, dreg, sreg1);
3365 arm_asrx (code, dreg, sreg1, imm);
3367 case OP_ISHR_UN_IMM:
3369 arm_movx (code, dreg, sreg1);
3371 arm_lsrw (code, dreg, sreg1, imm);
3374 case OP_LSHR_UN_IMM:
3376 arm_movx (code, dreg, sreg1);
3378 arm_lsrx (code, dreg, sreg1, imm);
3383 arm_sxtwx (code, dreg, sreg1);
3386 /* Clean out the upper word */
3387 arm_movw (code, dreg, sreg1);
3390 arm_lslx (code, dreg, sreg1, imm);
3393 /* MULTIPLY/DIVISION */
3396 // FIXME: Optimize this
3397 /* Check for zero */
3398 arm_cmpx_imm (code, sreg2, 0);
3399 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3400 /* Check for INT_MIN/-1 */
3401 code = emit_imm (code, ARMREG_IP0, 0x80000000);
3402 arm_cmpx (code, sreg1, ARMREG_IP0);
3403 arm_cset (code, ARMCOND_EQ, ARMREG_IP1);
3404 code = emit_imm (code, ARMREG_IP0, 0xffffffff);
3405 arm_cmpx (code, sreg2, ARMREG_IP0);
3406 arm_cset (code, ARMCOND_EQ, ARMREG_IP0);
3407 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
3408 arm_cmpx_imm (code, ARMREG_IP0, 1);
3409 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "OverflowException");
3410 if (ins->opcode == OP_IREM) {
3411 arm_sdivw (code, ARMREG_LR, sreg1, sreg2);
3412 arm_msubw (code, dreg, ARMREG_LR, sreg2, sreg1);
3414 arm_sdivw (code, dreg, sreg1, sreg2);
3418 arm_cmpx_imm (code, sreg2, 0);
3419 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3420 arm_udivw (code, dreg, sreg1, sreg2);
3423 arm_cmpx_imm (code, sreg2, 0);
3424 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3425 arm_udivw (code, ARMREG_LR, sreg1, sreg2);
3426 arm_msubw (code, dreg, ARMREG_LR, sreg2, sreg1);
3430 // FIXME: Optimize this
3431 /* Check for zero */
3432 arm_cmpx_imm (code, sreg2, 0);
3433 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3434 /* Check for INT64_MIN/-1 */
3435 code = emit_imm64 (code, ARMREG_IP0, 0x8000000000000000);
3436 arm_cmpx (code, sreg1, ARMREG_IP0);
3437 arm_cset (code, ARMCOND_EQ, ARMREG_IP1);
3438 code = emit_imm64 (code, ARMREG_IP0, 0xffffffffffffffff);
3439 arm_cmpx (code, sreg2, ARMREG_IP0);
3440 arm_cset (code, ARMCOND_EQ, ARMREG_IP0);
3441 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
3442 arm_cmpx_imm (code, ARMREG_IP0, 1);
3443 /* 64 bit uses ArithmeticException */
3444 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "ArithmeticException");
3445 if (ins->opcode == OP_LREM) {
3446 arm_sdivx (code, ARMREG_LR, sreg1, sreg2);
3447 arm_msubx (code, dreg, ARMREG_LR, sreg2, sreg1);
3449 arm_sdivx (code, dreg, sreg1, sreg2);
3453 arm_cmpx_imm (code, sreg2, 0);
3454 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3455 arm_udivx (code, dreg, sreg1, sreg2);
3458 arm_cmpx_imm (code, sreg2, 0);
3459 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3460 arm_udivx (code, ARMREG_LR, sreg1, sreg2);
3461 arm_msubx (code, dreg, ARMREG_LR, sreg2, sreg1);
3464 arm_mulw (code, dreg, sreg1, sreg2);
3467 arm_mulx (code, dreg, sreg1, sreg2);
3470 code = emit_imm (code, ARMREG_LR, imm);
3471 arm_mulw (code, dreg, sreg1, ARMREG_LR);
3475 code = emit_imm (code, ARMREG_LR, imm);
3476 arm_mulx (code, dreg, sreg1, ARMREG_LR);
3480 case OP_ICONV_TO_I1:
3481 case OP_LCONV_TO_I1:
3482 arm_sxtbx (code, dreg, sreg1);
3484 case OP_ICONV_TO_I2:
3485 case OP_LCONV_TO_I2:
3486 arm_sxthx (code, dreg, sreg1);
3488 case OP_ICONV_TO_U1:
3489 case OP_LCONV_TO_U1:
3490 arm_uxtbw (code, dreg, sreg1);
3492 case OP_ICONV_TO_U2:
3493 case OP_LCONV_TO_U2:
3494 arm_uxthw (code, dreg, sreg1);
3520 cond = opcode_to_armcond (ins->opcode);
3521 arm_cset (code, cond, dreg);
3534 cond = opcode_to_armcond (ins->opcode);
3535 arm_fcmpd (code, sreg1, sreg2);
3536 arm_cset (code, cond, dreg);
3541 case OP_LOADI1_MEMBASE:
3542 code = emit_ldrsbx (code, dreg, ins->inst_basereg, ins->inst_offset);
3544 case OP_LOADU1_MEMBASE:
3545 code = emit_ldrb (code, dreg, ins->inst_basereg, ins->inst_offset);
3547 case OP_LOADI2_MEMBASE:
3548 code = emit_ldrshx (code, dreg, ins->inst_basereg, ins->inst_offset);
3550 case OP_LOADU2_MEMBASE:
3551 code = emit_ldrh (code, dreg, ins->inst_basereg, ins->inst_offset);
3553 case OP_LOADI4_MEMBASE:
3554 code = emit_ldrswx (code, dreg, ins->inst_basereg, ins->inst_offset);
3556 case OP_LOADU4_MEMBASE:
3557 code = emit_ldrw (code, dreg, ins->inst_basereg, ins->inst_offset);
3559 case OP_LOAD_MEMBASE:
3560 case OP_LOADI8_MEMBASE:
3561 code = emit_ldrx (code, dreg, ins->inst_basereg, ins->inst_offset);
3563 case OP_STOREI1_MEMBASE_IMM:
3564 case OP_STOREI2_MEMBASE_IMM:
3565 case OP_STOREI4_MEMBASE_IMM:
3566 case OP_STORE_MEMBASE_IMM:
3567 case OP_STOREI8_MEMBASE_IMM: {
3571 code = emit_imm (code, ARMREG_LR, imm);
3574 immreg = ARMREG_RZR;
3577 switch (ins->opcode) {
3578 case OP_STOREI1_MEMBASE_IMM:
3579 code = emit_strb (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3581 case OP_STOREI2_MEMBASE_IMM:
3582 code = emit_strh (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3584 case OP_STOREI4_MEMBASE_IMM:
3585 code = emit_strw (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3587 case OP_STORE_MEMBASE_IMM:
3588 case OP_STOREI8_MEMBASE_IMM:
3589 code = emit_strx (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3592 g_assert_not_reached ();
3597 case OP_STOREI1_MEMBASE_REG:
3598 code = emit_strb (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3600 case OP_STOREI2_MEMBASE_REG:
3601 code = emit_strh (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3603 case OP_STOREI4_MEMBASE_REG:
3604 code = emit_strw (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3606 case OP_STORE_MEMBASE_REG:
3607 case OP_STOREI8_MEMBASE_REG:
3608 code = emit_strx (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3612 code = emit_tls_get (code, dreg, ins->inst_offset);
3614 case OP_TLS_GET_REG:
3615 code = emit_tls_get_reg (code, dreg, sreg1);
3618 code = emit_tls_set (code, sreg1, ins->inst_offset);
3620 case OP_TLS_SET_REG:
3621 code = emit_tls_set_reg (code, sreg1, sreg2);
3625 case OP_MEMORY_BARRIER:
3628 case OP_ATOMIC_ADD_I4: {
3632 arm_ldaxrw (code, ARMREG_IP0, sreg1);
3633 arm_addx (code, ARMREG_IP0, ARMREG_IP0, sreg2);
3634 arm_stlxrw (code, ARMREG_IP1, ARMREG_IP0, sreg1);
3635 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3637 arm_movx (code, dreg, ARMREG_IP0);
3640 case OP_ATOMIC_ADD_I8: {
3644 arm_ldaxrx (code, ARMREG_IP0, sreg1);
3645 arm_addx (code, ARMREG_IP0, ARMREG_IP0, sreg2);
3646 arm_stlxrx (code, ARMREG_IP1, ARMREG_IP0, sreg1);
3647 arm_cbnzx (code, ARMREG_IP1, buf [0]);
3649 arm_movx (code, dreg, ARMREG_IP0);
3652 case OP_ATOMIC_EXCHANGE_I4: {
3656 arm_ldaxrw (code, ARMREG_IP0, sreg1);
3657 arm_stlxrw (code, ARMREG_IP1, sreg2, sreg1);
3658 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3660 arm_movx (code, dreg, ARMREG_IP0);
3663 case OP_ATOMIC_EXCHANGE_I8: {
3667 arm_ldaxrx (code, ARMREG_IP0, sreg1);
3668 arm_stlxrx (code, ARMREG_IP1, sreg2, sreg1);
3669 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3671 arm_movx (code, dreg, ARMREG_IP0);
3674 case OP_ATOMIC_CAS_I4: {
3677 /* sreg2 is the value, sreg3 is the comparand */
3679 arm_ldaxrw (code, ARMREG_IP0, sreg1);
3680 arm_cmpw (code, ARMREG_IP0, ins->sreg3);
3682 arm_bcc (code, ARMCOND_NE, 0);
3683 arm_stlxrw (code, ARMREG_IP1, sreg2, sreg1);
3684 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3685 arm_patch_rel (buf [1], code, MONO_R_ARM64_BCC);
3687 arm_movx (code, dreg, ARMREG_IP0);
3690 case OP_ATOMIC_CAS_I8: {
3694 arm_ldaxrx (code, ARMREG_IP0, sreg1);
3695 arm_cmpx (code, ARMREG_IP0, ins->sreg3);
3697 arm_bcc (code, ARMCOND_NE, 0);
3698 arm_stlxrx (code, ARMREG_IP1, sreg2, sreg1);
3699 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3700 arm_patch_rel (buf [1], code, MONO_R_ARM64_BCC);
3702 arm_movx (code, dreg, ARMREG_IP0);
3705 case OP_ATOMIC_LOAD_I1: {
3706 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3707 arm_ldarb (code, ins->dreg, ARMREG_LR);
3708 arm_sxtbx (code, ins->dreg, ins->dreg);
3711 case OP_ATOMIC_LOAD_U1: {
3712 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3713 arm_ldarb (code, ins->dreg, ARMREG_LR);
3714 arm_uxtbx (code, ins->dreg, ins->dreg);
3717 case OP_ATOMIC_LOAD_I2: {
3718 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3719 arm_ldarh (code, ins->dreg, ARMREG_LR);
3720 arm_sxthx (code, ins->dreg, ins->dreg);
3723 case OP_ATOMIC_LOAD_U2: {
3724 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3725 arm_ldarh (code, ins->dreg, ARMREG_LR);
3726 arm_uxthx (code, ins->dreg, ins->dreg);
3729 case OP_ATOMIC_LOAD_I4: {
3730 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3731 arm_ldarw (code, ins->dreg, ARMREG_LR);
3732 arm_sxtwx (code, ins->dreg, ins->dreg);
3735 case OP_ATOMIC_LOAD_U4: {
3736 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3737 arm_ldarw (code, ins->dreg, ARMREG_LR);
3738 arm_movw (code, ins->dreg, ins->dreg); /* Clear upper half of the register. */
3741 case OP_ATOMIC_LOAD_I8:
3742 case OP_ATOMIC_LOAD_U8: {
3743 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3744 arm_ldarx (code, ins->dreg, ARMREG_LR);
3747 case OP_ATOMIC_LOAD_R4: {
3748 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3750 arm_ldarw (code, ARMREG_LR, ARMREG_LR);
3751 arm_fmov_rx_to_double (code, ins->dreg, ARMREG_LR);
3753 arm_ldarw (code, ARMREG_LR, ARMREG_LR);
3754 arm_fmov_rx_to_double (code, FP_TEMP_REG, ARMREG_LR);
3755 arm_fcvt_sd (code, ins->dreg, FP_TEMP_REG);
3759 case OP_ATOMIC_LOAD_R8: {
3760 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3761 arm_ldarx (code, ARMREG_LR, ARMREG_LR);
3762 arm_fmov_rx_to_double (code, ins->dreg, ARMREG_LR);
3765 case OP_ATOMIC_STORE_I1:
3766 case OP_ATOMIC_STORE_U1: {
3767 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3768 arm_stlrb (code, ARMREG_LR, ins->sreg1);
3771 case OP_ATOMIC_STORE_I2:
3772 case OP_ATOMIC_STORE_U2: {
3773 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3774 arm_stlrh (code, ARMREG_LR, ins->sreg1);
3777 case OP_ATOMIC_STORE_I4:
3778 case OP_ATOMIC_STORE_U4: {
3779 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3780 arm_stlrw (code, ARMREG_LR, ins->sreg1);
3783 case OP_ATOMIC_STORE_I8:
3784 case OP_ATOMIC_STORE_U8: {
3785 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3786 arm_stlrx (code, ARMREG_LR, ins->sreg1);
3789 case OP_ATOMIC_STORE_R4: {
3790 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3792 arm_fmov_double_to_rx (code, ARMREG_IP0, ins->sreg1);
3793 arm_stlrw (code, ARMREG_LR, ARMREG_IP0);
3795 arm_fcvt_ds (code, FP_TEMP_REG, ins->sreg1);
3796 arm_fmov_double_to_rx (code, ARMREG_IP0, FP_TEMP_REG);
3797 arm_stlrw (code, ARMREG_LR, ARMREG_IP0);
3801 case OP_ATOMIC_STORE_R8: {
3802 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3803 arm_fmov_double_to_rx (code, ARMREG_IP0, ins->sreg1);
3804 arm_stlrx (code, ARMREG_LR, ARMREG_IP0);
3810 guint64 imm = *(guint64*)ins->inst_p0;
3813 arm_fmov_rx_to_double (code, dreg, ARMREG_RZR);
3815 code = emit_imm64 (code, ARMREG_LR, imm);
3816 arm_fmov_rx_to_double (code, ins->dreg, ARMREG_LR);
3821 guint64 imm = *(guint32*)ins->inst_p0;
3823 code = emit_imm64 (code, ARMREG_LR, imm);
3825 arm_fmov_rx_to_double (code, dreg, ARMREG_LR);
3827 arm_fmov_rx_to_double (code, FP_TEMP_REG, ARMREG_LR);
3828 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3832 case OP_LOADR8_MEMBASE:
3833 code = emit_ldrfpx (code, dreg, ins->inst_basereg, ins->inst_offset);
3835 case OP_LOADR4_MEMBASE:
3837 code = emit_ldrfpw (code, dreg, ins->inst_basereg, ins->inst_offset);
3839 code = emit_ldrfpw (code, FP_TEMP_REG, ins->inst_basereg, ins->inst_offset);
3840 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3843 case OP_STORER8_MEMBASE_REG:
3844 code = emit_strfpx (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3846 case OP_STORER4_MEMBASE_REG:
3848 code = emit_strfpw (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3850 arm_fcvt_ds (code, FP_TEMP_REG, sreg1);
3851 code = emit_strfpw (code, FP_TEMP_REG, ins->inst_destbasereg, ins->inst_offset);
3856 arm_fmovd (code, dreg, sreg1);
3860 arm_fmovs (code, dreg, sreg1);
3862 case OP_MOVE_F_TO_I4:
3864 arm_fmov_double_to_rx (code, ins->dreg, ins->sreg1);
3866 arm_fcvt_ds (code, ins->dreg, ins->sreg1);
3867 arm_fmov_double_to_rx (code, ins->dreg, ins->dreg);
3870 case OP_MOVE_I4_TO_F:
3872 arm_fmov_rx_to_double (code, ins->dreg, ins->sreg1);
3874 arm_fmov_rx_to_double (code, ins->dreg, ins->sreg1);
3875 arm_fcvt_sd (code, ins->dreg, ins->dreg);
3878 case OP_MOVE_F_TO_I8:
3879 arm_fmov_double_to_rx (code, ins->dreg, ins->sreg1);
3881 case OP_MOVE_I8_TO_F:
3882 arm_fmov_rx_to_double (code, ins->dreg, ins->sreg1);
3885 arm_fcmpd (code, sreg1, sreg2);
3888 arm_fcmps (code, sreg1, sreg2);
3890 case OP_FCONV_TO_I1:
3891 arm_fcvtzs_dx (code, dreg, sreg1);
3892 arm_sxtbx (code, dreg, dreg);
3894 case OP_FCONV_TO_U1:
3895 arm_fcvtzu_dx (code, dreg, sreg1);
3896 arm_uxtbw (code, dreg, dreg);
3898 case OP_FCONV_TO_I2:
3899 arm_fcvtzs_dx (code, dreg, sreg1);
3900 arm_sxthx (code, dreg, dreg);
3902 case OP_FCONV_TO_U2:
3903 arm_fcvtzu_dx (code, dreg, sreg1);
3904 arm_uxthw (code, dreg, dreg);
3906 case OP_FCONV_TO_I4:
3907 arm_fcvtzs_dx (code, dreg, sreg1);
3908 arm_sxtwx (code, dreg, dreg);
3910 case OP_FCONV_TO_U4:
3911 arm_fcvtzu_dx (code, dreg, sreg1);
3913 case OP_FCONV_TO_I8:
3914 arm_fcvtzs_dx (code, dreg, sreg1);
3916 case OP_FCONV_TO_U8:
3917 arm_fcvtzu_dx (code, dreg, sreg1);
3919 case OP_FCONV_TO_R4:
3921 arm_fcvt_ds (code, dreg, sreg1);
3923 arm_fcvt_ds (code, FP_TEMP_REG, sreg1);
3924 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3927 case OP_ICONV_TO_R4:
3929 arm_scvtf_rw_to_s (code, dreg, sreg1);
3931 arm_scvtf_rw_to_s (code, FP_TEMP_REG, sreg1);
3932 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3935 case OP_LCONV_TO_R4:
3937 arm_scvtf_rx_to_s (code, dreg, sreg1);
3939 arm_scvtf_rx_to_s (code, FP_TEMP_REG, sreg1);
3940 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3943 case OP_ICONV_TO_R8:
3944 arm_scvtf_rw_to_d (code, dreg, sreg1);
3946 case OP_LCONV_TO_R8:
3947 arm_scvtf_rx_to_d (code, dreg, sreg1);
3949 case OP_ICONV_TO_R_UN:
3950 arm_ucvtf_rw_to_d (code, dreg, sreg1);
3952 case OP_LCONV_TO_R_UN:
3953 arm_ucvtf_rx_to_d (code, dreg, sreg1);
3956 arm_fadd_d (code, dreg, sreg1, sreg2);
3959 arm_fsub_d (code, dreg, sreg1, sreg2);
3962 arm_fmul_d (code, dreg, sreg1, sreg2);
3965 arm_fdiv_d (code, dreg, sreg1, sreg2);
3969 g_assert_not_reached ();
3972 arm_fneg_d (code, dreg, sreg1);
3974 case OP_ARM_SETFREG_R4:
3975 arm_fcvt_ds (code, dreg, sreg1);
3978 /* Check for infinity */
3979 code = emit_imm64 (code, ARMREG_LR, 0x7fefffffffffffffLL);
3980 arm_fmov_rx_to_double (code, FP_TEMP_REG, ARMREG_LR);
3981 arm_fabs_d (code, FP_TEMP_REG2, sreg1);
3982 arm_fcmpd (code, FP_TEMP_REG2, FP_TEMP_REG);
3983 code = emit_cond_exc (cfg, code, OP_COND_EXC_GT, "ArithmeticException");
3984 /* Check for nans */
3985 arm_fcmpd (code, FP_TEMP_REG2, FP_TEMP_REG2);
3986 code = emit_cond_exc (cfg, code, OP_COND_EXC_OV, "ArithmeticException");
3987 arm_fmovd (code, dreg, sreg1);
3992 arm_fadd_s (code, dreg, sreg1, sreg2);
3995 arm_fsub_s (code, dreg, sreg1, sreg2);
3998 arm_fmul_s (code, dreg, sreg1, sreg2);
4001 arm_fdiv_s (code, dreg, sreg1, sreg2);
4004 arm_fneg_s (code, dreg, sreg1);
4006 case OP_RCONV_TO_I1:
4007 arm_fcvtzs_sx (code, dreg, sreg1);
4008 arm_sxtbx (code, dreg, dreg);
4010 case OP_RCONV_TO_U1:
4011 arm_fcvtzu_sx (code, dreg, sreg1);
4012 arm_uxtbw (code, dreg, dreg);
4014 case OP_RCONV_TO_I2:
4015 arm_fcvtzs_sx (code, dreg, sreg1);
4016 arm_sxthx (code, dreg, dreg);
4018 case OP_RCONV_TO_U2:
4019 arm_fcvtzu_sx (code, dreg, sreg1);
4020 arm_uxthw (code, dreg, dreg);
4022 case OP_RCONV_TO_I4:
4023 arm_fcvtzs_sx (code, dreg, sreg1);
4024 arm_sxtwx (code, dreg, dreg);
4026 case OP_RCONV_TO_U4:
4027 arm_fcvtzu_sx (code, dreg, sreg1);
4029 case OP_RCONV_TO_I8:
4030 arm_fcvtzs_sx (code, dreg, sreg1);
4032 case OP_RCONV_TO_U8:
4033 arm_fcvtzu_sx (code, dreg, sreg1);
4035 case OP_RCONV_TO_R8:
4036 arm_fcvt_sd (code, dreg, sreg1);
4038 case OP_RCONV_TO_R4:
4040 arm_fmovs (code, dreg, sreg1);
4052 cond = opcode_to_armcond (ins->opcode);
4053 arm_fcmps (code, sreg1, sreg2);
4054 arm_cset (code, cond, dreg);
4065 call = (MonoCallInst*)ins;
4066 if (ins->flags & MONO_INST_HAS_METHOD)
4067 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
4069 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
4070 code = emit_move_return_value (cfg, code, ins);
4072 case OP_VOIDCALL_REG:
4078 arm_blrx (code, sreg1);
4079 code = emit_move_return_value (cfg, code, ins);
4081 case OP_VOIDCALL_MEMBASE:
4082 case OP_CALL_MEMBASE:
4083 case OP_LCALL_MEMBASE:
4084 case OP_FCALL_MEMBASE:
4085 case OP_RCALL_MEMBASE:
4086 case OP_VCALL2_MEMBASE:
4087 code = emit_ldrx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4088 arm_blrx (code, ARMREG_IP0);
4089 code = emit_move_return_value (cfg, code, ins);
4092 MonoCallInst *call = (MonoCallInst*)ins;
4094 g_assert (!cfg->method->save_lmf);
4096 // FIXME: Copy stack arguments
4098 /* Restore registers */
4099 code = emit_load_regset (code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->arch.saved_gregs_offset);
4102 code = mono_arm_emit_destroy_frame (code, cfg->stack_offset, ((1 << ARMREG_IP0) | (1 << ARMREG_IP1)));
4104 if (cfg->compile_aot) {
4105 /* This is not a PLT patch */
4106 code = emit_aotconst (cfg, code, ARMREG_IP0, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4107 arm_brx (code, ARMREG_IP0);
4109 mono_add_patch_info_rel (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method, MONO_R_ARM64_B);
4112 ins->flags |= MONO_INST_GC_CALLSITE;
4113 ins->backend.pc_offset = code - cfg->native_code;
4117 g_assert (cfg->arch.cinfo);
4118 code = emit_addx_imm (code, ARMREG_IP0, cfg->arch.args_reg, ((CallInfo*)cfg->arch.cinfo)->sig_cookie.offset);
4119 arm_strx (code, ARMREG_IP0, sreg1, 0);
4122 MonoInst *var = cfg->dyn_call_var;
4123 guint8 *labels [16];
4127 * sreg1 points to a DynCallArgs structure initialized by mono_arch_start_dyn_call ().
4128 * sreg2 is the function to call.
4131 g_assert (var->opcode == OP_REGOFFSET);
4133 arm_movx (code, ARMREG_LR, sreg1);
4134 arm_movx (code, ARMREG_IP1, sreg2);
4136 /* Save args buffer */
4137 code = emit_strx (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
4139 /* Set fp argument regs */
4140 code = emit_ldrw (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, n_fpargs));
4141 arm_cmpw (code, ARMREG_R0, ARMREG_RZR);
4143 arm_bcc (code, ARMCOND_EQ, 0);
4144 for (i = 0; i < 8; ++i)
4145 code = emit_ldrfpx (code, ARMREG_D0 + i, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * 8));
4146 arm_patch_rel (labels [0], code, MONO_R_ARM64_BCC);
4148 /* Set stack args */
4149 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4150 code = emit_ldrx (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + 1 + i) * sizeof (mgreg_t)));
4151 code = emit_strx (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
4154 /* Set argument registers + r8 */
4155 code = mono_arm_emit_load_regarray (code, 0x1ff, ARMREG_LR, 0);
4158 arm_blrx (code, ARMREG_IP1);
4161 code = emit_ldrx (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
4162 arm_strx (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, res));
4163 arm_strx (code, ARMREG_R1, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, res2));
4164 /* Save fp result */
4165 code = emit_ldrw (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, n_fpret));
4166 arm_cmpw (code, ARMREG_R0, ARMREG_RZR);
4168 arm_bcc (code, ARMCOND_EQ, 0);
4169 for (i = 0; i < 8; ++i)
4170 code = emit_strfpx (code, ARMREG_D0 + i, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * 8));
4171 arm_patch_rel (labels [1], code, MONO_R_ARM64_BCC);
4175 case OP_GENERIC_CLASS_INIT: {
4176 static int byte_offset = -1;
4177 static guint8 bitmask;
4180 if (byte_offset < 0)
4181 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4183 /* Load vtable->initialized */
4184 arm_ldrsbx (code, ARMREG_IP0, sreg1, byte_offset);
4185 // FIXME: No andx_imm yet */
4186 code = mono_arm_emit_imm64 (code, ARMREG_IP1, bitmask);
4187 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
4189 arm_cbnzx (code, ARMREG_IP0, 0);
4192 g_assert (sreg1 == ARMREG_R0);
4193 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4194 (gpointer)"mono_generic_class_init");
4196 mono_arm_patch (jump, code, MONO_R_ARM64_CBZ);
4201 arm_ldrx (code, ARMREG_LR, sreg1, 0);
4204 case OP_NOT_REACHED:
4207 case OP_IL_SEQ_POINT:
4208 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4213 case OP_COND_EXC_IC:
4214 case OP_COND_EXC_OV:
4215 case OP_COND_EXC_IOV:
4216 case OP_COND_EXC_NC:
4217 case OP_COND_EXC_INC:
4218 case OP_COND_EXC_NO:
4219 case OP_COND_EXC_INO:
4220 case OP_COND_EXC_EQ:
4221 case OP_COND_EXC_IEQ:
4222 case OP_COND_EXC_NE_UN:
4223 case OP_COND_EXC_INE_UN:
4224 case OP_COND_EXC_ILT:
4225 case OP_COND_EXC_LT:
4226 case OP_COND_EXC_ILT_UN:
4227 case OP_COND_EXC_LT_UN:
4228 case OP_COND_EXC_IGT:
4229 case OP_COND_EXC_GT:
4230 case OP_COND_EXC_IGT_UN:
4231 case OP_COND_EXC_GT_UN:
4232 case OP_COND_EXC_IGE:
4233 case OP_COND_EXC_GE:
4234 case OP_COND_EXC_IGE_UN:
4235 case OP_COND_EXC_GE_UN:
4236 case OP_COND_EXC_ILE:
4237 case OP_COND_EXC_LE:
4238 case OP_COND_EXC_ILE_UN:
4239 case OP_COND_EXC_LE_UN:
4240 code = emit_cond_exc (cfg, code, ins->opcode, ins->inst_p1);
4243 if (sreg1 != ARMREG_R0)
4244 arm_movx (code, ARMREG_R0, sreg1);
4245 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4246 (gpointer)"mono_arch_throw_exception");
4249 if (sreg1 != ARMREG_R0)
4250 arm_movx (code, ARMREG_R0, sreg1);
4251 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4252 (gpointer)"mono_arch_rethrow_exception");
4254 case OP_CALL_HANDLER:
4255 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb, MONO_R_ARM64_BL);
4257 cfg->thunk_area += THUNK_SIZE;
4259 case OP_START_HANDLER: {
4260 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4262 /* Save caller address */
4263 code = emit_strx (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4266 * Reserve a param area, see test_0_finally_param_area ().
4267 * This is needed because the param area is not set up when
4268 * we are called from EH code.
4270 if (cfg->param_area)
4271 code = emit_subx_sp_imm (code, cfg->param_area);
4275 case OP_ENDFILTER: {
4276 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4278 if (cfg->param_area)
4279 code = emit_addx_sp_imm (code, cfg->param_area);
4281 if (ins->opcode == OP_ENDFILTER && sreg1 != ARMREG_R0)
4282 arm_movx (code, ARMREG_R0, sreg1);
4284 /* Return to either after the branch in OP_CALL_HANDLER, or to the EH code */
4285 code = emit_ldrx (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4286 arm_brx (code, ARMREG_LR);
4290 if (ins->dreg != ARMREG_R0)
4291 arm_movx (code, ins->dreg, ARMREG_R0);
4293 case OP_GC_SAFE_POINT: {
4294 #if defined (USE_COOP_GC)
4297 arm_ldrx (code, ARMREG_IP1, ins->sreg1, 0);
4298 /* Call it if it is non-null */
4300 arm_cbzx (code, ARMREG_IP1, 0);
4301 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
4302 mono_arm_patch (buf [0], code, MONO_R_ARM64_CBZ);
4308 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4309 g_assert_not_reached ();
4312 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
4313 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4314 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4315 g_assert_not_reached ();
4320 * If the compiled code size is larger than the bcc displacement (19 bits signed),
4321 * insert branch islands between/inside basic blocks.
4323 if (cfg->arch.cond_branch_islands)
4324 code = emit_branch_island (cfg, code, start_offset);
4326 cfg->code_len = code - cfg->native_code;
4330 emit_move_args (MonoCompile *cfg, guint8 *code)
4337 cinfo = cfg->arch.cinfo;
4339 for (i = 0; i < cinfo->nargs; ++i) {
4340 ainfo = cinfo->args + i;
4341 ins = cfg->args [i];
4343 if (ins->opcode == OP_REGVAR) {
4344 switch (ainfo->storage) {
4346 arm_movx (code, ins->dreg, ainfo->reg);
4349 switch (ainfo->slot_size) {
4352 code = emit_ldrsbx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4354 code = emit_ldrb (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4358 code = emit_ldrshx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4360 code = emit_ldrh (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4364 code = emit_ldrswx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4366 code = emit_ldrw (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4369 code = emit_ldrx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4374 g_assert_not_reached ();
4378 if (ainfo->storage != ArgVtypeByRef && ainfo->storage != ArgVtypeByRefOnStack)
4379 g_assert (ins->opcode == OP_REGOFFSET);
4381 switch (ainfo->storage) {
4383 /* Stack slots for arguments have size 8 */
4384 code = emit_strx (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4387 code = emit_strfpx (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4390 code = emit_strfpw (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4395 case ArgVtypeByRefOnStack:
4396 case ArgVtypeOnStack:
4398 case ArgVtypeByRef: {
4399 MonoInst *addr_arg = ins->inst_left;
4401 if (ainfo->gsharedvt) {
4402 g_assert (ins->opcode == OP_GSHAREDVT_ARG_REGOFFSET);
4403 arm_strx (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4405 g_assert (ins->opcode == OP_VTARG_ADDR);
4406 g_assert (addr_arg->opcode == OP_REGOFFSET);
4407 arm_strx (code, ainfo->reg, addr_arg->inst_basereg, addr_arg->inst_offset);
4411 case ArgVtypeInIRegs:
4412 for (part = 0; part < ainfo->nregs; part ++) {
4413 code = emit_strx (code, ainfo->reg + part, ins->inst_basereg, ins->inst_offset + (part * 8));
4417 for (part = 0; part < ainfo->nregs; part ++) {
4418 if (ainfo->esize == 4)
4419 code = emit_strfpw (code, ainfo->reg + part, ins->inst_basereg, ins->inst_offset + ainfo->foffsets [part]);
4421 code = emit_strfpx (code, ainfo->reg + part, ins->inst_basereg, ins->inst_offset + ainfo->foffsets [part]);
4425 g_assert_not_reached ();
4435 * emit_store_regarray:
4437 * Emit code to store the registers in REGS into the appropriate elements of
4438 * the register array at BASEREG+OFFSET.
4440 static __attribute__((warn_unused_result)) guint8*
4441 emit_store_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4445 for (i = 0; i < 32; ++i) {
4446 if (regs & (1 << i)) {
4447 if (i + 1 < 32 && (regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4448 arm_stpx (code, i, i + 1, basereg, offset + (i * 8));
4450 } else if (i == ARMREG_SP) {
4451 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
4452 arm_strx (code, ARMREG_IP1, basereg, offset + (i * 8));
4454 arm_strx (code, i, basereg, offset + (i * 8));
4462 * emit_load_regarray:
4464 * Emit code to load the registers in REGS from the appropriate elements of
4465 * the register array at BASEREG+OFFSET.
4467 static __attribute__((warn_unused_result)) guint8*
4468 emit_load_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4472 for (i = 0; i < 32; ++i) {
4473 if (regs & (1 << i)) {
4474 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4475 if (offset + (i * 8) < 500)
4476 arm_ldpx (code, i, i + 1, basereg, offset + (i * 8));
4478 code = emit_ldrx (code, i, basereg, offset + (i * 8));
4479 code = emit_ldrx (code, i + 1, basereg, offset + ((i + 1) * 8));
4482 } else if (i == ARMREG_SP) {
4483 g_assert_not_reached ();
4485 code = emit_ldrx (code, i, basereg, offset + (i * 8));
4493 * emit_store_regset:
4495 * Emit code to store the registers in REGS into consecutive memory locations starting
4496 * at BASEREG+OFFSET.
4498 static __attribute__((warn_unused_result)) guint8*
4499 emit_store_regset (guint8 *code, guint64 regs, int basereg, int offset)
4504 for (i = 0; i < 32; ++i) {
4505 if (regs & (1 << i)) {
4506 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4507 arm_stpx (code, i, i + 1, basereg, offset + (pos * 8));
4510 } else if (i == ARMREG_SP) {
4511 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
4512 arm_strx (code, ARMREG_IP1, basereg, offset + (pos * 8));
4514 arm_strx (code, i, basereg, offset + (pos * 8));
4525 * Emit code to load the registers in REGS from consecutive memory locations starting
4526 * at BASEREG+OFFSET.
4528 static __attribute__((warn_unused_result)) guint8*
4529 emit_load_regset (guint8 *code, guint64 regs, int basereg, int offset)
4534 for (i = 0; i < 32; ++i) {
4535 if (regs & (1 << i)) {
4536 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4537 arm_ldpx (code, i, i + 1, basereg, offset + (pos * 8));
4540 } else if (i == ARMREG_SP) {
4541 g_assert_not_reached ();
4543 arm_ldrx (code, i, basereg, offset + (pos * 8));
4551 __attribute__((warn_unused_result)) guint8*
4552 mono_arm_emit_load_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4554 return emit_load_regarray (code, regs, basereg, offset);
4557 __attribute__((warn_unused_result)) guint8*
4558 mono_arm_emit_store_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4560 return emit_store_regarray (code, regs, basereg, offset);
4563 __attribute__((warn_unused_result)) guint8*
4564 mono_arm_emit_store_regset (guint8 *code, guint64 regs, int basereg, int offset)
4566 return emit_store_regset (code, regs, basereg, offset);
4569 /* Same as emit_store_regset, but emit unwind info too */
4570 /* CFA_OFFSET is the offset between the CFA and basereg */
4571 static __attribute__((warn_unused_result)) guint8*
4572 emit_store_regset_cfa (MonoCompile *cfg, guint8 *code, guint64 regs, int basereg, int offset, int cfa_offset, guint64 no_cfa_regset)
4574 int i, j, pos, nregs;
4575 guint32 cfa_regset = regs & ~no_cfa_regset;
4578 for (i = 0; i < 32; ++i) {
4580 if (regs & (1 << i)) {
4581 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4583 arm_stpx (code, i, i + 1, basereg, offset + (pos * 8));
4585 code = emit_strx (code, i, basereg, offset + (pos * 8));
4586 code = emit_strx (code, i + 1, basereg, offset + (pos * 8) + 8);
4589 } else if (i == ARMREG_SP) {
4590 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
4591 code = emit_strx (code, ARMREG_IP1, basereg, offset + (pos * 8));
4593 code = emit_strx (code, i, basereg, offset + (pos * 8));
4596 for (j = 0; j < nregs; ++j) {
4597 if (cfa_regset & (1 << (i + j)))
4598 mono_emit_unwind_op_offset (cfg, code, i + j, (- cfa_offset) + offset + ((pos + j) * 8));
4611 * Emit code to initialize an LMF structure at LMF_OFFSET.
4615 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
4618 * The LMF should contain all the state required to be able to reconstruct the machine state
4619 * at the current point of execution. Since the LMF is only read during EH, only callee
4620 * saved etc. registers need to be saved.
4621 * FIXME: Save callee saved fp regs, JITted code doesn't use them, but native code does, and they
4622 * need to be restored during EH.
4626 arm_adrx (code, ARMREG_LR, code);
4627 code = emit_strx (code, ARMREG_LR, ARMREG_FP, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, pc));
4628 /* gregs + fp + sp */
4629 /* Don't emit unwind info for sp/fp, they are already handled in the prolog */
4630 code = emit_store_regset_cfa (cfg, code, MONO_ARCH_LMF_REGS, ARMREG_FP, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, gregs), cfa_offset, (1 << ARMREG_FP) | (1 << ARMREG_SP));
4636 mono_arch_emit_prolog (MonoCompile *cfg)
4638 MonoMethod *method = cfg->method;
4639 MonoMethodSignature *sig;
4642 int cfa_offset, max_offset;
4644 sig = mono_method_signature (method);
4645 cfg->code_size = 256 + sig->param_count * 64;
4646 code = cfg->native_code = g_malloc (cfg->code_size);
4648 /* This can be unaligned */
4649 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4655 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
4658 if (arm_is_ldpx_imm (-cfg->stack_offset)) {
4659 arm_stpx_pre (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, -cfg->stack_offset);
4661 /* sp -= cfg->stack_offset */
4662 /* This clobbers ip0/ip1 */
4663 code = emit_subx_sp_imm (code, cfg->stack_offset);
4664 arm_stpx (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, 0);
4666 cfa_offset += cfg->stack_offset;
4667 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4668 mono_emit_unwind_op_offset (cfg, code, ARMREG_FP, (- cfa_offset) + 0);
4669 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, (- cfa_offset) + 8);
4670 arm_movspx (code, ARMREG_FP, ARMREG_SP);
4671 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_FP);
4672 if (cfg->param_area) {
4673 /* The param area is below the frame pointer */
4674 code = emit_subx_sp_imm (code, cfg->param_area);
4677 if (cfg->method->save_lmf) {
4678 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
4681 code = emit_store_regset_cfa (cfg, code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->arch.saved_gregs_offset, cfa_offset, 0);
4684 /* Setup args reg */
4685 if (cfg->arch.args_reg) {
4686 /* The register was already saved above */
4687 code = emit_addx_imm (code, cfg->arch.args_reg, ARMREG_FP, cfg->stack_offset);
4690 /* Save return area addr received in R8 */
4691 if (cfg->vret_addr) {
4692 MonoInst *ins = cfg->vret_addr;
4694 g_assert (ins->opcode == OP_REGOFFSET);
4695 code = emit_strx (code, ARMREG_R8, ins->inst_basereg, ins->inst_offset);
4698 /* Save mrgctx received in MONO_ARCH_RGCTX_REG */
4699 if (cfg->rgctx_var) {
4700 MonoInst *ins = cfg->rgctx_var;
4702 g_assert (ins->opcode == OP_REGOFFSET);
4704 code = emit_strx (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
4708 * Move arguments to their registers/stack locations.
4710 code = emit_move_args (cfg, code);
4712 /* Initialize seq_point_info_var */
4713 if (cfg->arch.seq_point_info_var) {
4714 MonoInst *ins = cfg->arch.seq_point_info_var;
4716 /* Initialize the variable from a GOT slot */
4717 code = emit_aotconst (cfg, code, ARMREG_IP0, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
4718 g_assert (ins->opcode == OP_REGOFFSET);
4719 code = emit_strx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4721 /* Initialize ss_tramp_var */
4722 ins = cfg->arch.ss_tramp_var;
4723 g_assert (ins->opcode == OP_REGOFFSET);
4725 code = emit_ldrx (code, ARMREG_IP1, ARMREG_IP0, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr));
4726 code = emit_strx (code, ARMREG_IP1, ins->inst_basereg, ins->inst_offset);
4730 if (cfg->arch.ss_tramp_var) {
4731 /* Initialize ss_tramp_var */
4732 ins = cfg->arch.ss_tramp_var;
4733 g_assert (ins->opcode == OP_REGOFFSET);
4735 code = emit_imm64 (code, ARMREG_IP0, (guint64)&ss_trampoline);
4736 code = emit_strx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4739 if (cfg->arch.bp_tramp_var) {
4740 /* Initialize bp_tramp_var */
4741 ins = cfg->arch.bp_tramp_var;
4742 g_assert (ins->opcode == OP_REGOFFSET);
4744 code = emit_imm64 (code, ARMREG_IP0, (guint64)bp_trampoline);
4745 code = emit_strx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4750 if (cfg->opt & MONO_OPT_BRANCH) {
4751 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4753 bb->max_offset = max_offset;
4755 MONO_BB_FOR_EACH_INS (bb, ins) {
4756 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4760 if (max_offset > 0x3ffff * 4)
4761 cfg->arch.cond_branch_islands = TRUE;
4767 realloc_code (MonoCompile *cfg, int size)
4769 while (cfg->code_len + size > (cfg->code_size - 16)) {
4770 cfg->code_size *= 2;
4771 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4772 cfg->stat_code_reallocs++;
4774 return cfg->native_code + cfg->code_len;
4778 mono_arch_emit_epilog (MonoCompile *cfg)
4781 int max_epilog_size;
4785 max_epilog_size = 16 + 20*4;
4786 code = realloc_code (cfg, max_epilog_size);
4788 if (cfg->method->save_lmf) {
4789 code = mono_arm_emit_load_regarray (code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, gregs) - (MONO_ARCH_FIRST_LMF_REG * 8));
4792 code = emit_load_regset (code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->arch.saved_gregs_offset);
4795 /* Load returned vtypes into registers if needed */
4796 cinfo = cfg->arch.cinfo;
4797 switch (cinfo->ret.storage) {
4798 case ArgVtypeInIRegs: {
4799 MonoInst *ins = cfg->ret;
4801 for (i = 0; i < cinfo->ret.nregs; ++i)
4802 code = emit_ldrx (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * 8));
4806 MonoInst *ins = cfg->ret;
4808 for (i = 0; i < cinfo->ret.nregs; ++i) {
4809 if (cinfo->ret.esize == 4)
4810 code = emit_ldrfpw (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + cinfo->ret.foffsets [i]);
4812 code = emit_ldrfpx (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + cinfo->ret.foffsets [i]);
4821 code = mono_arm_emit_destroy_frame (code, cfg->stack_offset, ((1 << ARMREG_IP0) | (1 << ARMREG_IP1)));
4823 arm_retx (code, ARMREG_LR);
4825 g_assert (code - (cfg->native_code + cfg->code_len) < max_epilog_size);
4827 cfg->code_len = code - cfg->native_code;
4831 mono_arch_emit_exceptions (MonoCompile *cfg)
4834 MonoClass *exc_class;
4836 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
4837 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
4838 int i, id, size = 0;
4840 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
4841 exc_throw_pos [i] = NULL;
4842 exc_throw_found [i] = 0;
4845 for (ji = cfg->patch_info; ji; ji = ji->next) {
4846 if (ji->type == MONO_PATCH_INFO_EXC) {
4847 i = mini_exception_id_by_name (ji->data.target);
4848 if (!exc_throw_found [i]) {
4850 exc_throw_found [i] = TRUE;
4855 code = realloc_code (cfg, size);
4857 /* Emit code to raise corlib exceptions */
4858 for (ji = cfg->patch_info; ji; ji = ji->next) {
4859 if (ji->type != MONO_PATCH_INFO_EXC)
4862 ip = cfg->native_code + ji->ip.i;
4864 id = mini_exception_id_by_name (ji->data.target);
4866 if (exc_throw_pos [id]) {
4867 /* ip points to the bcc () in OP_COND_EXC_... */
4868 arm_patch_rel (ip, exc_throw_pos [id], ji->relocation);
4869 ji->type = MONO_PATCH_INFO_NONE;
4873 exc_throw_pos [id] = code;
4874 arm_patch_rel (ip, code, ji->relocation);
4876 /* We are being branched to from the code generated by emit_cond_exc (), the pc is in ip1 */
4878 /* r0 = type token */
4879 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", ji->data.name);
4880 code = emit_imm (code, ARMREG_R0, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
4882 arm_movx (code, ARMREG_R1, ARMREG_IP1);
4883 /* Branch to the corlib exception throwing trampoline */
4884 ji->ip.i = code - cfg->native_code;
4885 ji->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4886 ji->data.name = "mono_arch_throw_corlib_exception";
4887 ji->relocation = MONO_R_ARM64_BL;
4889 cfg->thunk_area += THUNK_SIZE;
4892 cfg->code_len = code - cfg->native_code;
4894 g_assert (cfg->code_len < cfg->code_size);
4898 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4904 mono_arch_print_tree (MonoInst *tree, int arity)
4910 mono_arch_get_patch_offset (guint8 *code)
4916 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
4917 gpointer fail_tramp)
4919 int i, buf_len, imt_reg;
4923 printf ("building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable);
4924 for (i = 0; i < count; ++i) {
4925 MonoIMTCheckItem *item = imt_entries [i];
4926 printf ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, item->key->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
4931 for (i = 0; i < count; ++i) {
4932 MonoIMTCheckItem *item = imt_entries [i];
4933 if (item->is_equals) {
4934 gboolean fail_case = !item->check_target_idx && fail_tramp;
4936 if (item->check_target_idx || fail_case) {
4937 if (!item->compare_done || fail_case) {
4938 buf_len += 4 * 4 + 4;
4941 if (item->has_target_code) {
4958 buf = mono_method_alloc_generic_virtual_thunk (domain, buf_len);
4960 buf = mono_domain_code_reserve (domain, buf_len);
4964 * We are called by JITted code, which passes in the IMT argument in
4965 * MONO_ARCH_RGCTX_REG (r27). We need to preserve all caller saved regs
4968 imt_reg = MONO_ARCH_RGCTX_REG;
4969 for (i = 0; i < count; ++i) {
4970 MonoIMTCheckItem *item = imt_entries [i];
4972 item->code_target = code;
4974 if (item->is_equals) {
4976 * Check the imt argument against item->key, if equals, jump to either
4977 * item->value.target_code or to vtable [item->value.vtable_slot].
4978 * If fail_tramp is set, jump to it if not-equals.
4980 gboolean fail_case = !item->check_target_idx && fail_tramp;
4982 if (item->check_target_idx || fail_case) {
4983 /* Compare imt_reg with item->key */
4984 if (!item->compare_done || fail_case) {
4985 // FIXME: Optimize this
4986 code = emit_imm64 (code, ARMREG_IP0, (guint64)item->key);
4987 arm_cmpx (code, imt_reg, ARMREG_IP0);
4989 item->jmp_code = code;
4990 arm_bcc (code, ARMCOND_NE, 0);
4991 /* Jump to target if equals */
4992 if (item->has_target_code) {
4993 code = emit_imm64 (code, ARMREG_IP0, (guint64)item->value.target_code);
4994 arm_brx (code, ARMREG_IP0);
4996 guint64 imm = (guint64)&(vtable->vtable [item->value.vtable_slot]);
4998 code = emit_imm64 (code, ARMREG_IP0, imm);
4999 arm_ldrx (code, ARMREG_IP0, ARMREG_IP0, 0);
5000 arm_brx (code, ARMREG_IP0);
5004 arm_patch_rel (item->jmp_code, code, MONO_R_ARM64_BCC);
5005 item->jmp_code = NULL;
5006 code = emit_imm64 (code, ARMREG_IP0, (guint64)fail_tramp);
5007 arm_brx (code, ARMREG_IP0);
5010 guint64 imm = (guint64)&(vtable->vtable [item->value.vtable_slot]);
5012 code = emit_imm64 (code, ARMREG_IP0, imm);
5013 arm_ldrx (code, ARMREG_IP0, ARMREG_IP0, 0);
5014 arm_brx (code, ARMREG_IP0);
5017 code = emit_imm64 (code, ARMREG_IP0, (guint64)item->key);
5018 arm_cmpx (code, imt_reg, ARMREG_IP0);
5019 item->jmp_code = code;
5020 arm_bcc (code, ARMCOND_HS, 0);
5023 /* Patch the branches */
5024 for (i = 0; i < count; ++i) {
5025 MonoIMTCheckItem *item = imt_entries [i];
5026 if (item->jmp_code && item->check_target_idx)
5027 arm_patch_rel (item->jmp_code, imt_entries [item->check_target_idx]->code_target, MONO_R_ARM64_BCC);
5030 g_assert ((code - buf) < buf_len);
5032 mono_arch_flush_icache (buf, code - buf);
5038 mono_arch_get_trampolines (gboolean aot)
5040 return mono_arm_get_exception_trampolines (aot);
5043 #else /* DISABLE_JIT */
5046 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5047 gpointer fail_tramp)
5049 g_assert_not_reached ();
5053 #endif /* !DISABLE_JIT */
5055 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
5058 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
5061 guint32 native_offset = ip - (guint8*)ji->code_start;
5064 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5066 g_assert (native_offset % 4 == 0);
5067 g_assert (info->bp_addrs [native_offset / 4] == 0);
5068 info->bp_addrs [native_offset / 4] = mini_get_breakpoint_trampoline ();
5070 /* ip points to an ldrx */
5072 arm_blrx (code, ARMREG_IP0);
5073 mono_arch_flush_icache (ip, code - ip);
5078 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
5083 guint32 native_offset = ip - (guint8*)ji->code_start;
5084 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5086 g_assert (native_offset % 4 == 0);
5087 info->bp_addrs [native_offset / 4] = NULL;
5089 /* ip points to an ldrx */
5092 mono_arch_flush_icache (ip, code - ip);
5097 mono_arch_start_single_stepping (void)
5099 ss_trampoline = mini_get_single_step_trampoline ();
5103 mono_arch_stop_single_stepping (void)
5105 ss_trampoline = NULL;
5109 mono_arch_is_single_step_event (void *info, void *sigctx)
5111 /* We use soft breakpoints on arm64 */
5116 mono_arch_is_breakpoint_event (void *info, void *sigctx)
5118 /* We use soft breakpoints on arm64 */
5123 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
5125 g_assert_not_reached ();
5129 mono_arch_skip_single_step (MonoContext *ctx)
5131 g_assert_not_reached ();
5135 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
5140 // FIXME: Add a free function
5142 mono_domain_lock (domain);
5143 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
5145 mono_domain_unlock (domain);
5148 ji = mono_jit_info_table_find (domain, (char*)code);
5151 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size / 4) * sizeof(guint8*));
5153 info->ss_tramp_addr = &ss_trampoline;
5155 mono_domain_lock (domain);
5156 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
5158 mono_domain_unlock (domain);
5165 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
5167 ext->lmf.previous_lmf = prev_lmf;
5168 /* Mark that this is a MonoLMFExt */
5169 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
5170 ext->lmf.gregs [MONO_ARCH_LMF_REG_SP] = (gssize)ext;
5173 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
5176 mono_arch_opcode_supported (int opcode)
5179 case OP_ATOMIC_ADD_I4:
5180 case OP_ATOMIC_ADD_I8:
5181 case OP_ATOMIC_EXCHANGE_I4:
5182 case OP_ATOMIC_EXCHANGE_I8:
5183 case OP_ATOMIC_CAS_I4:
5184 case OP_ATOMIC_CAS_I8:
5185 case OP_ATOMIC_LOAD_I1:
5186 case OP_ATOMIC_LOAD_I2:
5187 case OP_ATOMIC_LOAD_I4:
5188 case OP_ATOMIC_LOAD_I8:
5189 case OP_ATOMIC_LOAD_U1:
5190 case OP_ATOMIC_LOAD_U2:
5191 case OP_ATOMIC_LOAD_U4:
5192 case OP_ATOMIC_LOAD_U8:
5193 case OP_ATOMIC_LOAD_R4:
5194 case OP_ATOMIC_LOAD_R8:
5195 case OP_ATOMIC_STORE_I1:
5196 case OP_ATOMIC_STORE_I2:
5197 case OP_ATOMIC_STORE_I4:
5198 case OP_ATOMIC_STORE_I8:
5199 case OP_ATOMIC_STORE_U1:
5200 case OP_ATOMIC_STORE_U2:
5201 case OP_ATOMIC_STORE_U4:
5202 case OP_ATOMIC_STORE_U8:
5203 case OP_ATOMIC_STORE_R4:
5204 case OP_ATOMIC_STORE_R8:
5212 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
5214 return get_call_info (mp, sig);