3 * ARM backend for the Mono code generator
6 * Paolo Molaro (lupus@ximian.com)
7 * Dietmar Maurer (dietmar@ximian.com)
9 * (C) 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
11 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
12 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
17 #include <mono/metadata/abi-details.h>
18 #include <mono/metadata/appdomain.h>
19 #include <mono/metadata/profiler-private.h>
20 #include <mono/metadata/debug-helpers.h>
21 #include <mono/utils/mono-mmap.h>
22 #include <mono/utils/mono-hwcap.h>
23 #include <mono/utils/mono-memory-model.h>
24 #include <mono/utils/mono-threads-coop.h>
30 #include "debugger-agent.h"
32 #include "mono/arch/arm/arm-vfp-codegen.h"
34 /* Sanity check: This makes no sense */
35 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
36 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
40 * IS_SOFT_FLOAT: Is full software floating point used?
41 * IS_HARD_FLOAT: Is full hardware floating point used?
42 * IS_VFP: Is hardware floating point with software ABI used?
44 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
45 * IS_VFP may delegate to mono_arch_is_soft_float ().
48 #if defined(ARM_FPU_VFP_HARD)
49 #define IS_SOFT_FLOAT (FALSE)
50 #define IS_HARD_FLOAT (TRUE)
52 #elif defined(ARM_FPU_NONE)
53 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
54 #define IS_HARD_FLOAT (FALSE)
55 #define IS_VFP (!mono_arch_is_soft_float ())
57 #define IS_SOFT_FLOAT (FALSE)
58 #define IS_HARD_FLOAT (FALSE)
62 #define THUNK_SIZE (3 * 4)
64 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
67 void sys_icache_invalidate (void *start, size_t len);
70 /* This mutex protects architecture specific caches */
71 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
72 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
73 static mono_mutex_t mini_arch_mutex;
75 static gboolean v5_supported = FALSE;
76 static gboolean v6_supported = FALSE;
77 static gboolean v7_supported = FALSE;
78 static gboolean v7s_supported = FALSE;
79 static gboolean v7k_supported = FALSE;
80 static gboolean thumb_supported = FALSE;
81 static gboolean thumb2_supported = FALSE;
83 * Whenever to use the ARM EABI
85 static gboolean eabi_supported = FALSE;
88 * Whenever to use the iphone ABI extensions:
89 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
90 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
91 * This is required for debugging/profiling tools to work, but it has some overhead so it should
92 * only be turned on in debug builds.
94 static gboolean iphone_abi = FALSE;
97 * The FPU we are generating code for. This is NOT runtime configurable right now,
98 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
100 static MonoArmFPU arm_fpu;
102 #if defined(ARM_FPU_VFP_HARD)
104 * On armhf, d0-d7 are used for argument passing and d8-d15
105 * must be preserved across calls, which leaves us no room
106 * for scratch registers. So we use d14-d15 but back up their
107 * previous contents to a stack slot before using them - see
108 * mono_arm_emit_vfp_scratch_save/_restore ().
110 static int vfp_scratch1 = ARM_VFP_D14;
111 static int vfp_scratch2 = ARM_VFP_D15;
114 * On armel, d0-d7 do not need to be preserved, so we can
115 * freely make use of them as scratch registers.
117 static int vfp_scratch1 = ARM_VFP_D0;
118 static int vfp_scratch2 = ARM_VFP_D1;
123 static gpointer single_step_tramp, breakpoint_tramp;
124 static gpointer get_tls_tramp;
127 * The code generated for sequence points reads from this location, which is
128 * made read-only when single stepping is enabled.
130 static gpointer ss_trigger_page;
132 /* Enabled breakpoints read from this trigger page */
133 static gpointer bp_trigger_page;
137 * floating point support: on ARM it is a mess, there are at least 3
138 * different setups, each of which binary incompat with the other.
139 * 1) FPA: old and ugly, but unfortunately what current distros use
140 * the double binary format has the two words swapped. 8 double registers.
141 * Implemented usually by kernel emulation.
142 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
143 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
144 * 3) VFP: the new and actually sensible and useful FP support. Implemented
145 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
147 * We do not care about FPA. We will support soft float and VFP.
149 int mono_exc_esp_offset = 0;
151 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
152 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
153 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
155 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
156 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
157 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
159 //#define DEBUG_IMT 0
162 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
166 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data);
169 mono_arch_regname (int reg)
171 static const char * rnames[] = {
172 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
173 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
174 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
177 if (reg >= 0 && reg < 16)
183 mono_arch_fregname (int reg)
185 static const char * rnames[] = {
186 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
187 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
188 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
189 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
190 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
191 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
194 if (reg >= 0 && reg < 32)
202 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
204 int imm8, rot_amount;
205 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
206 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
210 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
211 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
213 code = mono_arm_emit_load_imm (code, dreg, imm);
214 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
219 /* If dreg == sreg, this clobbers IP */
221 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
223 int imm8, rot_amount;
224 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
225 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
229 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
230 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
232 code = mono_arm_emit_load_imm (code, dreg, imm);
233 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
239 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
241 /* we can use r0-r3, since this is called only for incoming args on the stack */
242 if (size > sizeof (gpointer) * 4) {
244 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
245 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
246 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
247 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
248 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
249 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
250 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
251 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
252 ARM_B_COND (code, ARMCOND_NE, 0);
253 arm_patch (code - 4, start_loop);
256 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
257 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
259 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
260 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
266 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
267 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
268 doffset = soffset = 0;
270 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
271 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
277 g_assert (size == 0);
282 emit_call_reg (guint8 *code, int reg)
285 ARM_BLX_REG (code, reg);
287 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
291 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
297 emit_call_seq (MonoCompile *cfg, guint8 *code)
299 if (cfg->method->dynamic) {
300 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
302 *(gpointer*)code = NULL;
304 code = emit_call_reg (code, ARMREG_IP);
308 cfg->thunk_area += THUNK_SIZE;
313 mono_arm_patchable_b (guint8 *code, int cond)
315 ARM_B_COND (code, cond, 0);
320 mono_arm_patchable_bl (guint8 *code, int cond)
322 ARM_BL_COND (code, cond, 0);
326 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID) && !defined(__native_client__)
327 #define HAVE_AEABI_READ_TP 1
330 #ifdef HAVE_AEABI_READ_TP
331 gpointer __aeabi_read_tp (void);
335 mono_arch_have_fast_tls (void)
337 #ifdef HAVE_AEABI_READ_TP
338 static gboolean have_fast_tls = FALSE;
339 static gboolean inited = FALSE;
342 if (mini_get_debug_options ()->use_fallback_tls)
346 return have_fast_tls;
348 tp1 = __aeabi_read_tp ();
349 asm volatile("mrc p15, 0, %0, c13, c0, 3" : "=r" (tp2));
351 have_fast_tls = tp1 && tp1 == tp2;
353 return have_fast_tls;
360 emit_tls_get (guint8 *code, int dreg, int tls_offset)
362 ARM_MRC (code, 15, 0, dreg, 13, 0, 3);
363 ARM_LDR_IMM (code, dreg, dreg, tls_offset);
368 emit_tls_set (guint8 *code, int sreg, int tls_offset)
370 int tp_reg = (sreg != ARMREG_R0) ? ARMREG_R0 : ARMREG_R1;
371 ARM_MRC (code, 15, 0, tp_reg, 13, 0, 3);
372 ARM_STR_IMM (code, sreg, tp_reg, tls_offset);
379 * Emit code to push an LMF structure on the LMF stack.
380 * On arm, this is intermixed with the initialization of other fields of the structure.
383 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
387 if (mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_LMF_ADDR) != -1) {
388 code = emit_tls_get (code, ARMREG_R0, mono_tls_get_tls_offset (TLS_KEY_LMF_ADDR));
390 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
391 (gpointer)"mono_tls_get_lmf_addr");
392 code = emit_call_seq (cfg, code);
394 /* we build the MonoLMF structure on the stack - see mini-arm.h */
395 /* lmf_offset is the offset from the previous stack pointer,
396 * alloc_size is the total stack space allocated, so the offset
397 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
398 * The pointer to the struct is put in r1 (new_lmf).
399 * ip is used as scratch
400 * The callee-saved registers are already in the MonoLMF structure
402 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
403 /* r0 is the result from mono_get_lmf_addr () */
404 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
405 /* new_lmf->previous_lmf = *lmf_addr */
406 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
407 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
408 /* *(lmf_addr) = r1 */
409 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
410 /* Skip method (only needed for trampoline LMF frames) */
411 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
412 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
413 /* save the current IP */
414 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
415 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
417 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
418 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
429 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
433 for (list = inst->float_args; list; list = list->next) {
434 FloatArgData *fad = list->data;
435 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
436 gboolean imm = arm_is_fpimm8 (var->inst_offset);
438 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
444 if (*offset + *max_len > cfg->code_size) {
445 cfg->code_size += *max_len;
446 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
448 code = cfg->native_code + *offset;
452 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
453 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
455 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
457 *offset = code - cfg->native_code;
464 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
468 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
470 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
473 if (!arm_is_fpimm8 (inst->inst_offset)) {
474 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
475 ARM_FSTD (code, reg, ARMREG_LR, 0);
477 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
484 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
488 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
490 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
493 if (!arm_is_fpimm8 (inst->inst_offset)) {
494 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
495 ARM_FLDD (code, reg, ARMREG_LR, 0);
497 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
506 * Emit code to pop an LMF structure from the LMF stack.
509 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
513 if (lmf_offset < 32) {
514 basereg = cfg->frame_reg;
519 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
522 /* ip = previous_lmf */
523 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
525 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
526 /* *(lmf_addr) = previous_lmf */
527 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
532 #endif /* #ifndef DISABLE_JIT */
535 * mono_arch_get_argument_info:
536 * @csig: a method signature
537 * @param_count: the number of parameters to consider
538 * @arg_info: an array to store the result infos
540 * Gathers information on parameters such as size, alignment and
541 * padding. arg_info should be large enought to hold param_count + 1 entries.
543 * Returns the size of the activation frame.
546 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
548 int k, frame_size = 0;
549 guint32 size, align, pad;
553 t = mini_get_underlying_type (csig->ret);
554 if (MONO_TYPE_ISSTRUCT (t)) {
555 frame_size += sizeof (gpointer);
559 arg_info [0].offset = offset;
562 frame_size += sizeof (gpointer);
566 arg_info [0].size = frame_size;
568 for (k = 0; k < param_count; k++) {
569 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
571 /* ignore alignment for now */
574 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
575 arg_info [k].pad = pad;
577 arg_info [k + 1].pad = 0;
578 arg_info [k + 1].size = size;
580 arg_info [k + 1].offset = offset;
584 align = MONO_ARCH_FRAME_ALIGNMENT;
585 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
586 arg_info [k].pad = pad;
591 #define MAX_ARCH_DELEGATE_PARAMS 3
594 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
596 guint8 *code, *start;
597 GSList *unwind_ops = mono_arch_get_cie_program ();
600 start = code = mono_global_codeman_reserve (12);
602 /* Replace the this argument with the target */
603 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
604 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
605 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
607 g_assert ((code - start) <= 12);
609 mono_arch_flush_icache (start, 12);
613 size = 8 + param_count * 4;
614 start = code = mono_global_codeman_reserve (size);
616 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
617 /* slide down the arguments */
618 for (i = 0; i < param_count; ++i) {
619 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
621 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
623 g_assert ((code - start) <= size);
625 mono_arch_flush_icache (start, size);
629 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
631 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
632 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
636 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
642 * mono_arch_get_delegate_invoke_impls:
644 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
648 mono_arch_get_delegate_invoke_impls (void)
654 get_delegate_invoke_impl (&info, TRUE, 0);
655 res = g_slist_prepend (res, info);
657 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
658 get_delegate_invoke_impl (&info, FALSE, i);
659 res = g_slist_prepend (res, info);
666 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
668 guint8 *code, *start;
671 /* FIXME: Support more cases */
672 sig_ret = mini_get_underlying_type (sig->ret);
673 if (MONO_TYPE_ISSTRUCT (sig_ret))
677 static guint8* cached = NULL;
678 mono_mini_arch_lock ();
680 mono_mini_arch_unlock ();
685 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
688 start = get_delegate_invoke_impl (&info, TRUE, 0);
689 mono_tramp_info_register (info, NULL);
692 mono_mini_arch_unlock ();
695 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
698 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
700 for (i = 0; i < sig->param_count; ++i)
701 if (!mono_is_regsize_var (sig->params [i]))
704 mono_mini_arch_lock ();
705 code = cache [sig->param_count];
707 mono_mini_arch_unlock ();
712 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
713 start = mono_aot_get_trampoline (name);
717 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
718 mono_tramp_info_register (info, NULL);
720 cache [sig->param_count] = start;
721 mono_mini_arch_unlock ();
729 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
735 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
737 return (gpointer)regs [ARMREG_R0];
741 * Initialize the cpu to execute managed code.
744 mono_arch_cpu_init (void)
746 i8_align = MONO_ABI_ALIGNOF (gint64);
747 #ifdef MONO_CROSS_COMPILE
748 /* Need to set the alignment of i8 since it can different on the target */
749 #ifdef TARGET_ANDROID
751 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
757 * Initialize architecture specific code.
760 mono_arch_init (void)
762 const char *cpu_arch;
764 #ifdef TARGET_WATCHOS
765 mini_get_debug_options ()->soft_breakpoints = TRUE;
768 mono_os_mutex_init_recursive (&mini_arch_mutex);
769 if (mini_get_debug_options ()->soft_breakpoints) {
771 breakpoint_tramp = mini_get_breakpoint_trampoline ();
773 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT, MONO_MEM_ACCOUNT_OTHER);
774 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT, MONO_MEM_ACCOUNT_OTHER);
775 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
778 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
779 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
780 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
781 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
782 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
784 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
785 mono_aot_register_jit_icall ("mono_arm_handler_block_trampoline_helper", mono_arm_handler_block_trampoline_helper);
786 #if defined(__ARM_EABI__)
787 eabi_supported = TRUE;
790 #if defined(ARM_FPU_VFP_HARD)
791 arm_fpu = MONO_ARM_FPU_VFP_HARD;
793 arm_fpu = MONO_ARM_FPU_VFP;
795 #if defined(ARM_FPU_NONE) && !defined(TARGET_IOS)
797 * If we're compiling with a soft float fallback and it
798 * turns out that no VFP unit is available, we need to
799 * switch to soft float. We don't do this for iOS, since
800 * iOS devices always have a VFP unit.
802 if (!mono_hwcap_arm_has_vfp)
803 arm_fpu = MONO_ARM_FPU_NONE;
806 * This environment variable can be useful in testing
807 * environments to make sure the soft float fallback
808 * works. Most ARM devices have VFP units these days, so
809 * normally soft float code would not be exercised much.
811 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
813 if (soft && !strncmp (soft, "1", 1))
814 arm_fpu = MONO_ARM_FPU_NONE;
818 v5_supported = mono_hwcap_arm_is_v5;
819 v6_supported = mono_hwcap_arm_is_v6;
820 v7_supported = mono_hwcap_arm_is_v7;
823 * On weird devices, the hwcap code may fail to detect
824 * the ARM version. In that case, we can at least safely
825 * assume the version the runtime was compiled for.
837 #if defined(TARGET_IOS)
838 /* iOS is special-cased here because we don't yet
839 have a way to properly detect CPU features on it. */
840 thumb_supported = TRUE;
843 thumb_supported = mono_hwcap_arm_has_thumb;
844 thumb2_supported = mono_hwcap_arm_has_thumb2;
847 /* Format: armv(5|6|7[s])[-thumb[2]] */
848 cpu_arch = g_getenv ("MONO_CPU_ARCH");
850 /* Do this here so it overrides any detection. */
852 if (strncmp (cpu_arch, "armv", 4) == 0) {
853 v5_supported = cpu_arch [4] >= '5';
854 v6_supported = cpu_arch [4] >= '6';
855 v7_supported = cpu_arch [4] >= '7';
856 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
857 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
860 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
861 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
866 * Cleanup architecture specific code.
869 mono_arch_cleanup (void)
874 * This function returns the optimizations supported on this cpu.
877 mono_arch_cpu_optimizations (guint32 *exclude_mask)
879 /* no arm-specific optimizations yet */
885 * This function test for all SIMD functions supported.
887 * Returns a bitmask corresponding to all supported versions.
891 mono_arch_cpu_enumerate_simd_versions (void)
893 /* SIMD is currently unimplemented */
898 mono_arm_is_hard_float (void)
900 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
906 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
908 if (v7s_supported || v7k_supported) {
922 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
924 mono_arch_is_soft_float (void)
926 return arm_fpu == MONO_ARM_FPU_NONE;
931 is_regsize_var (MonoType *t)
935 t = mini_get_underlying_type (t);
942 case MONO_TYPE_FNPTR:
944 case MONO_TYPE_OBJECT:
945 case MONO_TYPE_STRING:
946 case MONO_TYPE_CLASS:
947 case MONO_TYPE_SZARRAY:
948 case MONO_TYPE_ARRAY:
950 case MONO_TYPE_GENERICINST:
951 if (!mono_type_generic_inst_is_valuetype (t))
954 case MONO_TYPE_VALUETYPE:
961 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
966 for (i = 0; i < cfg->num_varinfo; i++) {
967 MonoInst *ins = cfg->varinfo [i];
968 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
971 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
974 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
977 /* we can only allocate 32 bit values */
978 if (is_regsize_var (ins->inst_vtype)) {
979 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
980 g_assert (i == vmv->idx);
981 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
989 mono_arch_get_global_int_regs (MonoCompile *cfg)
993 mono_arch_compute_omit_fp (cfg);
996 * FIXME: Interface calls might go through a static rgctx trampoline which
997 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1000 if (cfg->flags & MONO_CFG_HAS_CALLS)
1001 cfg->uses_rgctx_reg = TRUE;
1003 if (cfg->arch.omit_fp)
1004 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1005 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1006 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1007 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1009 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1010 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1012 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1013 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1014 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1015 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1016 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1017 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1023 * mono_arch_regalloc_cost:
1025 * Return the cost, in number of memory references, of the action of
1026 * allocating the variable VMV into a register during global register
1030 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1036 #endif /* #ifndef DISABLE_JIT */
1039 mono_arch_flush_icache (guint8 *code, gint size)
1041 #if defined(MONO_CROSS_COMPILE)
1043 sys_icache_invalidate (code, size);
1045 __builtin___clear_cache (code, code + size);
1052 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1055 if (*gr > ARMREG_R3) {
1057 ainfo->offset = *stack_size;
1058 ainfo->reg = ARMREG_SP; /* in the caller */
1059 ainfo->storage = RegTypeBase;
1062 ainfo->storage = RegTypeGeneral;
1069 split = i8_align == 4;
1074 if (*gr == ARMREG_R3 && split) {
1075 /* first word in r3 and the second on the stack */
1076 ainfo->offset = *stack_size;
1077 ainfo->reg = ARMREG_SP; /* in the caller */
1078 ainfo->storage = RegTypeBaseGen;
1080 } else if (*gr >= ARMREG_R3) {
1081 if (eabi_supported) {
1082 /* darwin aligns longs to 4 byte only */
1083 if (i8_align == 8) {
1088 ainfo->offset = *stack_size;
1089 ainfo->reg = ARMREG_SP; /* in the caller */
1090 ainfo->storage = RegTypeBase;
1093 if (eabi_supported) {
1094 if (i8_align == 8 && ((*gr) & 1))
1097 ainfo->storage = RegTypeIRegPair;
1106 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1109 * If we're calling a function like this:
1111 * void foo(float a, double b, float c)
1113 * We pass a in s0 and b in d1. That leaves us
1114 * with s1 being unused. The armhf ABI recognizes
1115 * this and requires register assignment to then
1116 * use that for the next single-precision arg,
1117 * i.e. c in this example. So float_spare either
1118 * tells us which reg to use for the next single-
1119 * precision arg, or it's -1, meaning use *fpr.
1121 * Note that even though most of the JIT speaks
1122 * double-precision, fpr represents single-
1123 * precision registers.
1125 * See parts 5.5 and 6.1.2 of the AAPCS for how
1129 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1130 ainfo->storage = RegTypeFP;
1134 * If we're passing a double-precision value
1135 * and *fpr is odd (e.g. it's s1, s3, ...)
1136 * we need to use the next even register. So
1137 * we mark the current *fpr as a spare that
1138 * can be used for the next single-precision
1142 *float_spare = *fpr;
1147 * At this point, we have an even register
1148 * so we assign that and move along.
1152 } else if (*float_spare >= 0) {
1154 * We're passing a single-precision value
1155 * and it looks like a spare single-
1156 * precision register is available. Let's
1160 ainfo->reg = *float_spare;
1164 * If we hit this branch, we're passing a
1165 * single-precision value and we can simply
1166 * use the next available register.
1174 * We've exhausted available floating point
1175 * regs, so pass the rest on the stack.
1183 ainfo->offset = *stack_size;
1184 ainfo->reg = ARMREG_SP;
1185 ainfo->storage = RegTypeBase;
1192 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1196 MonoClassField *field;
1197 MonoType *ftype, *prev_ftype = NULL;
1200 klass = mono_class_from_mono_type (t);
1202 while ((field = mono_class_get_fields (klass, &iter))) {
1203 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1205 ftype = mono_field_get_type (field);
1206 ftype = mini_get_underlying_type (ftype);
1208 if (MONO_TYPE_ISSTRUCT (ftype)) {
1209 int nested_nfields, nested_esize;
1211 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1213 if (nested_esize == 4)
1214 ftype = &mono_defaults.single_class->byval_arg;
1216 ftype = &mono_defaults.double_class->byval_arg;
1217 if (prev_ftype && prev_ftype->type != ftype->type)
1220 nfields += nested_nfields;
1222 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1224 if (prev_ftype && prev_ftype->type != ftype->type)
1230 if (nfields == 0 || nfields > 4)
1232 *out_nfields = nfields;
1233 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1238 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1240 guint i, gr, fpr, pstart;
1242 int n = sig->hasthis + sig->param_count;
1246 guint32 stack_size = 0;
1248 gboolean is_pinvoke = sig->pinvoke;
1249 gboolean vtype_retaddr = FALSE;
1252 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1254 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1261 t = mini_get_underlying_type (sig->ret);
1272 case MONO_TYPE_FNPTR:
1273 case MONO_TYPE_CLASS:
1274 case MONO_TYPE_OBJECT:
1275 case MONO_TYPE_SZARRAY:
1276 case MONO_TYPE_ARRAY:
1277 case MONO_TYPE_STRING:
1278 cinfo->ret.storage = RegTypeGeneral;
1279 cinfo->ret.reg = ARMREG_R0;
1283 cinfo->ret.storage = RegTypeIRegPair;
1284 cinfo->ret.reg = ARMREG_R0;
1288 cinfo->ret.storage = RegTypeFP;
1290 if (t->type == MONO_TYPE_R4)
1291 cinfo->ret.size = 4;
1293 cinfo->ret.size = 8;
1295 if (IS_HARD_FLOAT) {
1296 cinfo->ret.reg = ARM_VFP_F0;
1298 cinfo->ret.reg = ARMREG_R0;
1301 case MONO_TYPE_GENERICINST:
1302 if (!mono_type_generic_inst_is_valuetype (t)) {
1303 cinfo->ret.storage = RegTypeGeneral;
1304 cinfo->ret.reg = ARMREG_R0;
1307 if (mini_is_gsharedvt_variable_type (t)) {
1308 cinfo->ret.storage = RegTypeStructByAddr;
1312 case MONO_TYPE_VALUETYPE:
1313 case MONO_TYPE_TYPEDBYREF:
1314 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1315 cinfo->ret.storage = RegTypeHFA;
1317 cinfo->ret.nregs = nfields;
1318 cinfo->ret.esize = esize;
1321 int native_size = mono_class_native_size (mono_class_from_mono_type (t), &align);
1324 #ifdef TARGET_WATCHOS
1329 if (native_size <= max_size) {
1330 cinfo->ret.storage = RegTypeStructByVal;
1331 cinfo->ret.struct_size = native_size;
1332 cinfo->ret.nregs = ALIGN_TO (native_size, 4) / 4;
1334 cinfo->ret.storage = RegTypeStructByAddr;
1337 cinfo->ret.storage = RegTypeStructByAddr;
1342 case MONO_TYPE_MVAR:
1343 g_assert (mini_is_gsharedvt_type (t));
1344 cinfo->ret.storage = RegTypeStructByAddr;
1346 case MONO_TYPE_VOID:
1349 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1352 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1357 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1358 * the first argument, allowing 'this' to be always passed in the first arg reg.
1359 * Also do this if the first argument is a reference type, since virtual calls
1360 * are sometimes made using calli without sig->hasthis set, like in the delegate
1363 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1365 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1367 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1371 cinfo->ret.reg = gr;
1373 cinfo->vret_arg_index = 1;
1377 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1380 if (vtype_retaddr) {
1381 cinfo->ret.reg = gr;
1386 DEBUG(g_print("params: %d\n", sig->param_count));
1387 for (i = pstart; i < sig->param_count; ++i) {
1388 ArgInfo *ainfo = &cinfo->args [n];
1390 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1391 /* Prevent implicit arguments and sig_cookie from
1392 being passed in registers */
1395 /* Emit the signature cookie just before the implicit arguments */
1396 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1398 DEBUG(g_print("param %d: ", i));
1399 if (sig->params [i]->byref) {
1400 DEBUG(g_print("byref\n"));
1401 add_general (&gr, &stack_size, ainfo, TRUE);
1405 t = mini_get_underlying_type (sig->params [i]);
1409 cinfo->args [n].size = 1;
1410 add_general (&gr, &stack_size, ainfo, TRUE);
1414 cinfo->args [n].size = 2;
1415 add_general (&gr, &stack_size, ainfo, TRUE);
1419 cinfo->args [n].size = 4;
1420 add_general (&gr, &stack_size, ainfo, TRUE);
1425 case MONO_TYPE_FNPTR:
1426 case MONO_TYPE_CLASS:
1427 case MONO_TYPE_OBJECT:
1428 case MONO_TYPE_STRING:
1429 case MONO_TYPE_SZARRAY:
1430 case MONO_TYPE_ARRAY:
1431 cinfo->args [n].size = sizeof (gpointer);
1432 add_general (&gr, &stack_size, ainfo, TRUE);
1434 case MONO_TYPE_GENERICINST:
1435 if (!mono_type_generic_inst_is_valuetype (t)) {
1436 cinfo->args [n].size = sizeof (gpointer);
1437 add_general (&gr, &stack_size, ainfo, TRUE);
1440 if (mini_is_gsharedvt_variable_type (t)) {
1441 /* gsharedvt arguments are passed by ref */
1442 g_assert (mini_is_gsharedvt_type (t));
1443 add_general (&gr, &stack_size, ainfo, TRUE);
1444 switch (ainfo->storage) {
1445 case RegTypeGeneral:
1446 ainfo->storage = RegTypeGSharedVtInReg;
1449 ainfo->storage = RegTypeGSharedVtOnStack;
1452 g_assert_not_reached ();
1457 case MONO_TYPE_TYPEDBYREF:
1458 case MONO_TYPE_VALUETYPE: {
1461 int nwords, nfields, esize;
1464 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1465 if (fpr + nfields < ARM_VFP_F16) {
1466 ainfo->storage = RegTypeHFA;
1468 ainfo->nregs = nfields;
1469 ainfo->esize = esize;
1480 if (t->type == MONO_TYPE_TYPEDBYREF) {
1481 size = sizeof (MonoTypedRef);
1482 align = sizeof (gpointer);
1484 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1486 size = mono_class_native_size (klass, &align);
1488 size = mini_type_stack_size_full (t, &align, FALSE);
1490 DEBUG(g_print ("load %d bytes struct\n", size));
1492 #ifdef TARGET_WATCHOS
1493 /* Watchos pass large structures by ref */
1494 /* We only do this for pinvoke to make gsharedvt/dyncall simpler */
1495 if (sig->pinvoke && size > 16) {
1496 add_general (&gr, &stack_size, ainfo, TRUE);
1497 switch (ainfo->storage) {
1498 case RegTypeGeneral:
1499 ainfo->storage = RegTypeStructByAddr;
1502 ainfo->storage = RegTypeStructByAddrOnStack;
1505 g_assert_not_reached ();
1514 align_size += (sizeof (gpointer) - 1);
1515 align_size &= ~(sizeof (gpointer) - 1);
1516 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1517 ainfo->storage = RegTypeStructByVal;
1518 ainfo->struct_size = size;
1519 ainfo->align = align;
1520 /* FIXME: align stack_size if needed */
1521 if (eabi_supported) {
1522 if (align >= 8 && (gr & 1))
1525 if (gr > ARMREG_R3) {
1527 ainfo->vtsize = nwords;
1529 int rest = ARMREG_R3 - gr + 1;
1530 int n_in_regs = rest >= nwords? nwords: rest;
1532 ainfo->size = n_in_regs;
1533 ainfo->vtsize = nwords - n_in_regs;
1536 nwords -= n_in_regs;
1538 if (sig->call_convention == MONO_CALL_VARARG)
1539 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1540 stack_size = ALIGN_TO (stack_size, align);
1541 ainfo->offset = stack_size;
1542 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1543 stack_size += nwords * sizeof (gpointer);
1549 add_general (&gr, &stack_size, ainfo, FALSE);
1555 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1557 add_general (&gr, &stack_size, ainfo, TRUE);
1563 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1565 add_general (&gr, &stack_size, ainfo, FALSE);
1568 case MONO_TYPE_MVAR:
1569 /* gsharedvt arguments are passed by ref */
1570 g_assert (mini_is_gsharedvt_type (t));
1571 add_general (&gr, &stack_size, ainfo, TRUE);
1572 switch (ainfo->storage) {
1573 case RegTypeGeneral:
1574 ainfo->storage = RegTypeGSharedVtInReg;
1577 ainfo->storage = RegTypeGSharedVtOnStack;
1580 g_assert_not_reached ();
1584 g_error ("Can't handle 0x%x", sig->params [i]->type);
1589 /* Handle the case where there are no implicit arguments */
1590 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1591 /* Prevent implicit arguments and sig_cookie from
1592 being passed in registers */
1595 /* Emit the signature cookie just before the implicit arguments */
1596 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1599 /* align stack size to 8 */
1600 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1601 stack_size = (stack_size + 7) & ~7;
1603 cinfo->stack_usage = stack_size;
1609 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1611 MonoType *callee_ret;
1615 c1 = get_call_info (NULL, caller_sig);
1616 c2 = get_call_info (NULL, callee_sig);
1619 * Tail calls with more callee stack usage than the caller cannot be supported, since
1620 * the extra stack space would be left on the stack after the tail call.
1622 res = c1->stack_usage >= c2->stack_usage;
1623 callee_ret = mini_get_underlying_type (callee_sig->ret);
1624 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1625 /* An address on the callee's stack is passed as the first argument */
1628 if (c2->stack_usage > 16 * 4)
1640 debug_omit_fp (void)
1643 return mono_debug_count ();
1650 * mono_arch_compute_omit_fp:
1652 * Determine whenever the frame pointer can be eliminated.
1655 mono_arch_compute_omit_fp (MonoCompile *cfg)
1657 MonoMethodSignature *sig;
1658 MonoMethodHeader *header;
1662 if (cfg->arch.omit_fp_computed)
1665 header = cfg->header;
1667 sig = mono_method_signature (cfg->method);
1669 if (!cfg->arch.cinfo)
1670 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1671 cinfo = cfg->arch.cinfo;
1674 * FIXME: Remove some of the restrictions.
1676 cfg->arch.omit_fp = TRUE;
1677 cfg->arch.omit_fp_computed = TRUE;
1679 if (cfg->disable_omit_fp)
1680 cfg->arch.omit_fp = FALSE;
1681 if (!debug_omit_fp ())
1682 cfg->arch.omit_fp = FALSE;
1684 if (cfg->method->save_lmf)
1685 cfg->arch.omit_fp = FALSE;
1687 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1688 cfg->arch.omit_fp = FALSE;
1689 if (header->num_clauses)
1690 cfg->arch.omit_fp = FALSE;
1691 if (cfg->param_area)
1692 cfg->arch.omit_fp = FALSE;
1693 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1694 cfg->arch.omit_fp = FALSE;
1695 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1696 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1697 cfg->arch.omit_fp = FALSE;
1698 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1699 ArgInfo *ainfo = &cinfo->args [i];
1701 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1703 * The stack offset can only be determined when the frame
1706 cfg->arch.omit_fp = FALSE;
1711 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1712 MonoInst *ins = cfg->varinfo [i];
1715 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1720 * Set var information according to the calling convention. arm version.
1721 * The locals var stuff should most likely be split in another method.
1724 mono_arch_allocate_vars (MonoCompile *cfg)
1726 MonoMethodSignature *sig;
1727 MonoMethodHeader *header;
1730 int i, offset, size, align, curinst;
1735 sig = mono_method_signature (cfg->method);
1737 if (!cfg->arch.cinfo)
1738 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1739 cinfo = cfg->arch.cinfo;
1740 sig_ret = mini_get_underlying_type (sig->ret);
1742 mono_arch_compute_omit_fp (cfg);
1744 if (cfg->arch.omit_fp)
1745 cfg->frame_reg = ARMREG_SP;
1747 cfg->frame_reg = ARMREG_FP;
1749 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1751 /* allow room for the vararg method args: void* and long/double */
1752 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1753 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1755 header = cfg->header;
1757 /* See mono_arch_get_global_int_regs () */
1758 if (cfg->flags & MONO_CFG_HAS_CALLS)
1759 cfg->uses_rgctx_reg = TRUE;
1761 if (cfg->frame_reg != ARMREG_SP)
1762 cfg->used_int_regs |= 1 << cfg->frame_reg;
1764 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1765 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1766 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1770 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1771 if (sig_ret->type != MONO_TYPE_VOID) {
1772 cfg->ret->opcode = OP_REGVAR;
1773 cfg->ret->inst_c0 = ARMREG_R0;
1776 /* local vars are at a positive offset from the stack pointer */
1778 * also note that if the function uses alloca, we use FP
1779 * to point at the local variables.
1781 offset = 0; /* linkage area */
1782 /* align the offset to 16 bytes: not sure this is needed here */
1784 //offset &= ~(8 - 1);
1786 /* add parameter area size for called functions */
1787 offset += cfg->param_area;
1790 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1793 /* allow room to save the return value */
1794 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1797 switch (cinfo->ret.storage) {
1798 case RegTypeStructByVal:
1800 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1801 offset = ALIGN_TO (offset, 8);
1802 cfg->ret->opcode = OP_REGOFFSET;
1803 cfg->ret->inst_basereg = cfg->frame_reg;
1804 cfg->ret->inst_offset = offset;
1805 if (cinfo->ret.storage == RegTypeStructByVal)
1806 offset += cinfo->ret.nregs * sizeof (gpointer);
1810 case RegTypeStructByAddr:
1811 ins = cfg->vret_addr;
1812 offset += sizeof(gpointer) - 1;
1813 offset &= ~(sizeof(gpointer) - 1);
1814 ins->inst_offset = offset;
1815 ins->opcode = OP_REGOFFSET;
1816 ins->inst_basereg = cfg->frame_reg;
1817 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1818 g_print ("vret_addr =");
1819 mono_print_ins (cfg->vret_addr);
1821 offset += sizeof(gpointer);
1827 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1828 if (cfg->arch.seq_point_info_var) {
1831 ins = cfg->arch.seq_point_info_var;
1835 offset += align - 1;
1836 offset &= ~(align - 1);
1837 ins->opcode = OP_REGOFFSET;
1838 ins->inst_basereg = cfg->frame_reg;
1839 ins->inst_offset = offset;
1842 if (cfg->arch.ss_trigger_page_var) {
1845 ins = cfg->arch.ss_trigger_page_var;
1848 offset += align - 1;
1849 offset &= ~(align - 1);
1850 ins->opcode = OP_REGOFFSET;
1851 ins->inst_basereg = cfg->frame_reg;
1852 ins->inst_offset = offset;
1856 if (cfg->arch.seq_point_ss_method_var) {
1859 ins = cfg->arch.seq_point_ss_method_var;
1862 offset += align - 1;
1863 offset &= ~(align - 1);
1864 ins->opcode = OP_REGOFFSET;
1865 ins->inst_basereg = cfg->frame_reg;
1866 ins->inst_offset = offset;
1869 if (cfg->arch.seq_point_bp_method_var) {
1872 ins = cfg->arch.seq_point_bp_method_var;
1875 offset += align - 1;
1876 offset &= ~(align - 1);
1877 ins->opcode = OP_REGOFFSET;
1878 ins->inst_basereg = cfg->frame_reg;
1879 ins->inst_offset = offset;
1883 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
1884 /* Allocate a temporary used by the atomic ops */
1888 /* Allocate a local slot to hold the sig cookie address */
1889 offset += align - 1;
1890 offset &= ~(align - 1);
1891 cfg->arch.atomic_tmp_offset = offset;
1894 cfg->arch.atomic_tmp_offset = -1;
1897 cfg->locals_min_stack_offset = offset;
1899 curinst = cfg->locals_start;
1900 for (i = curinst; i < cfg->num_varinfo; ++i) {
1903 ins = cfg->varinfo [i];
1904 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1907 t = ins->inst_vtype;
1908 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
1911 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1912 * pinvoke wrappers when they call functions returning structure */
1913 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
1914 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
1918 size = mono_type_size (t, &align);
1920 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1921 * since it loads/stores misaligned words, which don't do the right thing.
1923 if (align < 4 && size >= 4)
1925 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1926 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1927 offset += align - 1;
1928 offset &= ~(align - 1);
1929 ins->opcode = OP_REGOFFSET;
1930 ins->inst_offset = offset;
1931 ins->inst_basereg = cfg->frame_reg;
1933 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1936 cfg->locals_max_stack_offset = offset;
1940 ins = cfg->args [curinst];
1941 if (ins->opcode != OP_REGVAR) {
1942 ins->opcode = OP_REGOFFSET;
1943 ins->inst_basereg = cfg->frame_reg;
1944 offset += sizeof (gpointer) - 1;
1945 offset &= ~(sizeof (gpointer) - 1);
1946 ins->inst_offset = offset;
1947 offset += sizeof (gpointer);
1952 if (sig->call_convention == MONO_CALL_VARARG) {
1956 /* Allocate a local slot to hold the sig cookie address */
1957 offset += align - 1;
1958 offset &= ~(align - 1);
1959 cfg->sig_cookie = offset;
1963 for (i = 0; i < sig->param_count; ++i) {
1964 ainfo = cinfo->args + i;
1966 ins = cfg->args [curinst];
1968 switch (ainfo->storage) {
1970 offset = ALIGN_TO (offset, 8);
1971 ins->opcode = OP_REGOFFSET;
1972 ins->inst_basereg = cfg->frame_reg;
1973 /* These arguments are saved to the stack in the prolog */
1974 ins->inst_offset = offset;
1975 if (cfg->verbose_level >= 2)
1976 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
1984 if (ins->opcode != OP_REGVAR) {
1985 ins->opcode = OP_REGOFFSET;
1986 ins->inst_basereg = cfg->frame_reg;
1987 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
1989 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1990 * since it loads/stores misaligned words, which don't do the right thing.
1992 if (align < 4 && size >= 4)
1994 /* The code in the prolog () stores words when storing vtypes received in a register */
1995 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
1997 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1998 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1999 offset += align - 1;
2000 offset &= ~(align - 1);
2001 ins->inst_offset = offset;
2007 /* align the offset to 8 bytes */
2008 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2009 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2014 cfg->stack_offset = offset;
2018 mono_arch_create_vars (MonoCompile *cfg)
2020 MonoMethodSignature *sig;
2024 sig = mono_method_signature (cfg->method);
2026 if (!cfg->arch.cinfo)
2027 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2028 cinfo = cfg->arch.cinfo;
2030 if (IS_HARD_FLOAT) {
2031 for (i = 0; i < 2; i++) {
2032 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2033 inst->flags |= MONO_INST_VOLATILE;
2035 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2039 if (cinfo->ret.storage == RegTypeStructByVal)
2040 cfg->ret_var_is_local = TRUE;
2042 if (cinfo->ret.storage == RegTypeStructByAddr) {
2043 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2044 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2045 g_print ("vret_addr = ");
2046 mono_print_ins (cfg->vret_addr);
2050 if (cfg->gen_sdb_seq_points) {
2051 if (cfg->compile_aot) {
2052 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2053 ins->flags |= MONO_INST_VOLATILE;
2054 cfg->arch.seq_point_info_var = ins;
2056 if (!cfg->soft_breakpoints) {
2057 /* Allocate a separate variable for this to save 1 load per seq point */
2058 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2059 ins->flags |= MONO_INST_VOLATILE;
2060 cfg->arch.ss_trigger_page_var = ins;
2063 if (cfg->soft_breakpoints) {
2066 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2067 ins->flags |= MONO_INST_VOLATILE;
2068 cfg->arch.seq_point_ss_method_var = ins;
2070 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2071 ins->flags |= MONO_INST_VOLATILE;
2072 cfg->arch.seq_point_bp_method_var = ins;
2078 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2080 MonoMethodSignature *tmp_sig;
2083 if (call->tail_call)
2086 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2089 * mono_ArgIterator_Setup assumes the signature cookie is
2090 * passed first and all the arguments which were before it are
2091 * passed on the stack after the signature. So compensate by
2092 * passing a different signature.
2094 tmp_sig = mono_metadata_signature_dup (call->signature);
2095 tmp_sig->param_count -= call->signature->sentinelpos;
2096 tmp_sig->sentinelpos = 0;
2097 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2099 sig_reg = mono_alloc_ireg (cfg);
2100 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2102 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2107 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2112 LLVMCallInfo *linfo;
2114 n = sig->param_count + sig->hasthis;
2116 cinfo = get_call_info (cfg->mempool, sig);
2118 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2121 * LLVM always uses the native ABI while we use our own ABI, the
2122 * only difference is the handling of vtypes:
2123 * - we only pass/receive them in registers in some cases, and only
2124 * in 1 or 2 integer registers.
2126 switch (cinfo->ret.storage) {
2127 case RegTypeGeneral:
2130 case RegTypeIRegPair:
2132 case RegTypeStructByAddr:
2133 /* Vtype returned using a hidden argument */
2134 linfo->ret.storage = LLVMArgVtypeRetAddr;
2135 linfo->vret_arg_index = cinfo->vret_arg_index;
2138 case RegTypeStructByVal:
2139 /* LLVM models this by returning an int array */
2140 linfo->ret.storage = LLVMArgAsIArgs;
2141 linfo->ret.nslots = cinfo->ret.nregs;
2145 linfo->ret.storage = LLVMArgFpStruct;
2146 linfo->ret.nslots = cinfo->ret.nregs;
2147 linfo->ret.esize = cinfo->ret.esize;
2150 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2151 cfg->disable_llvm = TRUE;
2155 for (i = 0; i < n; ++i) {
2156 LLVMArgInfo *lainfo = &linfo->args [i];
2157 ainfo = cinfo->args + i;
2159 lainfo->storage = LLVMArgNone;
2161 switch (ainfo->storage) {
2162 case RegTypeGeneral:
2163 case RegTypeIRegPair:
2165 case RegTypeBaseGen:
2167 lainfo->storage = LLVMArgNormal;
2169 case RegTypeStructByVal:
2170 lainfo->storage = LLVMArgAsIArgs;
2171 if (eabi_supported && ainfo->align == 8) {
2172 /* LLVM models this by passing an int64 array */
2173 lainfo->nslots = ALIGN_TO (ainfo->struct_size, 8) / 8;
2176 lainfo->nslots = ainfo->struct_size / sizeof (gpointer);
2180 printf ("D: %d\n", ainfo->align);
2182 case RegTypeStructByAddr:
2183 case RegTypeStructByAddrOnStack:
2184 lainfo->storage = LLVMArgVtypeByRef;
2189 lainfo->storage = LLVMArgAsFpArgs;
2190 lainfo->nslots = ainfo->nregs;
2191 lainfo->esize = ainfo->esize;
2192 for (j = 0; j < ainfo->nregs; ++j)
2193 lainfo->pair_storage [j] = LLVMArgInFPReg;
2197 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2198 cfg->disable_llvm = TRUE;
2208 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2211 MonoMethodSignature *sig;
2215 sig = call->signature;
2216 n = sig->param_count + sig->hasthis;
2218 cinfo = get_call_info (cfg->mempool, sig);
2220 switch (cinfo->ret.storage) {
2221 case RegTypeStructByVal:
2223 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
2224 /* The JIT will transform this into a normal call */
2225 call->vret_in_reg = TRUE;
2228 if (call->inst.opcode == OP_TAILCALL)
2231 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2232 * the location pointed to by it after call in emit_move_return_value ().
2234 if (!cfg->arch.vret_addr_loc) {
2235 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2236 /* Prevent it from being register allocated or optimized away */
2237 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2240 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2242 case RegTypeStructByAddr: {
2244 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2245 vtarg->sreg1 = call->vret_var->dreg;
2246 vtarg->dreg = mono_alloc_preg (cfg);
2247 MONO_ADD_INS (cfg->cbb, vtarg);
2249 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2256 for (i = 0; i < n; ++i) {
2257 ArgInfo *ainfo = cinfo->args + i;
2260 if (i >= sig->hasthis)
2261 t = sig->params [i - sig->hasthis];
2263 t = &mono_defaults.int_class->byval_arg;
2264 t = mini_get_underlying_type (t);
2266 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2267 /* Emit the signature cookie just before the implicit arguments */
2268 emit_sig_cookie (cfg, call, cinfo);
2271 in = call->args [i];
2273 switch (ainfo->storage) {
2274 case RegTypeGeneral:
2275 case RegTypeIRegPair:
2276 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2277 MONO_INST_NEW (cfg, ins, OP_MOVE);
2278 ins->dreg = mono_alloc_ireg (cfg);
2279 ins->sreg1 = MONO_LVREG_LS (in->dreg);
2280 MONO_ADD_INS (cfg->cbb, ins);
2281 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2283 MONO_INST_NEW (cfg, ins, OP_MOVE);
2284 ins->dreg = mono_alloc_ireg (cfg);
2285 ins->sreg1 = MONO_LVREG_MS (in->dreg);
2286 MONO_ADD_INS (cfg->cbb, ins);
2287 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2288 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2289 if (ainfo->size == 4) {
2290 if (IS_SOFT_FLOAT) {
2291 /* mono_emit_call_args () have already done the r8->r4 conversion */
2292 /* The converted value is in an int vreg */
2293 MONO_INST_NEW (cfg, ins, OP_MOVE);
2294 ins->dreg = mono_alloc_ireg (cfg);
2295 ins->sreg1 = in->dreg;
2296 MONO_ADD_INS (cfg->cbb, ins);
2297 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2301 cfg->param_area = MAX (cfg->param_area, 8);
2302 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2303 creg = mono_alloc_ireg (cfg);
2304 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2305 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2308 if (IS_SOFT_FLOAT) {
2309 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2310 ins->dreg = mono_alloc_ireg (cfg);
2311 ins->sreg1 = in->dreg;
2312 MONO_ADD_INS (cfg->cbb, ins);
2313 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2315 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2316 ins->dreg = mono_alloc_ireg (cfg);
2317 ins->sreg1 = in->dreg;
2318 MONO_ADD_INS (cfg->cbb, ins);
2319 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2323 cfg->param_area = MAX (cfg->param_area, 8);
2324 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2325 creg = mono_alloc_ireg (cfg);
2326 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2327 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2328 creg = mono_alloc_ireg (cfg);
2329 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2330 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2333 cfg->flags |= MONO_CFG_HAS_FPOUT;
2335 MONO_INST_NEW (cfg, ins, OP_MOVE);
2336 ins->dreg = mono_alloc_ireg (cfg);
2337 ins->sreg1 = in->dreg;
2338 MONO_ADD_INS (cfg->cbb, ins);
2340 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2343 case RegTypeStructByVal:
2344 case RegTypeGSharedVtInReg:
2345 case RegTypeGSharedVtOnStack:
2347 case RegTypeStructByAddr:
2348 case RegTypeStructByAddrOnStack:
2349 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2350 ins->opcode = OP_OUTARG_VT;
2351 ins->sreg1 = in->dreg;
2352 ins->klass = in->klass;
2353 ins->inst_p0 = call;
2354 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2355 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2356 mono_call_inst_add_outarg_vt (cfg, call, ins);
2357 MONO_ADD_INS (cfg->cbb, ins);
2360 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2361 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2362 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2363 if (t->type == MONO_TYPE_R8) {
2364 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2367 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2369 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2372 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2375 case RegTypeBaseGen:
2376 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2377 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? MONO_LVREG_LS (in->dreg) : MONO_LVREG_MS (in->dreg));
2378 MONO_INST_NEW (cfg, ins, OP_MOVE);
2379 ins->dreg = mono_alloc_ireg (cfg);
2380 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? MONO_LVREG_MS (in->dreg) : MONO_LVREG_LS (in->dreg);
2381 MONO_ADD_INS (cfg->cbb, ins);
2382 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2383 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2386 /* This should work for soft-float as well */
2388 cfg->param_area = MAX (cfg->param_area, 8);
2389 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2390 creg = mono_alloc_ireg (cfg);
2391 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2392 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2393 creg = mono_alloc_ireg (cfg);
2394 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2395 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2396 cfg->flags |= MONO_CFG_HAS_FPOUT;
2398 g_assert_not_reached ();
2402 int fdreg = mono_alloc_freg (cfg);
2404 if (ainfo->size == 8) {
2405 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2406 ins->sreg1 = in->dreg;
2408 MONO_ADD_INS (cfg->cbb, ins);
2410 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2415 * Mono's register allocator doesn't speak single-precision registers that
2416 * overlap double-precision registers (i.e. armhf). So we have to work around
2417 * the register allocator and load the value from memory manually.
2419 * So we create a variable for the float argument and an instruction to store
2420 * the argument into the variable. We then store the list of these arguments
2421 * in call->float_args. This list is then used by emit_float_args later to
2422 * pass the arguments in the various call opcodes.
2424 * This is not very nice, and we should really try to fix the allocator.
2427 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2429 /* Make sure the instruction isn't seen as pointless and removed.
2431 float_arg->flags |= MONO_INST_VOLATILE;
2433 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2435 /* We use the dreg to look up the instruction later. The hreg is used to
2436 * emit the instruction that loads the value into the FP reg.
2438 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2439 fad->vreg = float_arg->dreg;
2440 fad->hreg = ainfo->reg;
2442 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2445 call->used_iregs |= 1 << ainfo->reg;
2446 cfg->flags |= MONO_CFG_HAS_FPOUT;
2450 g_assert_not_reached ();
2454 /* Handle the case where there are no implicit arguments */
2455 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2456 emit_sig_cookie (cfg, call, cinfo);
2458 call->call_info = cinfo;
2459 call->stack_usage = cinfo->stack_usage;
2463 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2469 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2470 ins->dreg = mono_alloc_freg (cfg);
2471 ins->sreg1 = arg->dreg;
2472 MONO_ADD_INS (cfg->cbb, ins);
2473 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2476 g_assert_not_reached ();
2482 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2484 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2486 ArgInfo *ainfo = ins->inst_p1;
2487 int ovf_size = ainfo->vtsize;
2488 int doffset = ainfo->offset;
2489 int struct_size = ainfo->struct_size;
2490 int i, soffset, dreg, tmpreg;
2492 switch (ainfo->storage) {
2493 case RegTypeGSharedVtInReg:
2494 case RegTypeStructByAddr:
2496 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2498 case RegTypeGSharedVtOnStack:
2499 case RegTypeStructByAddrOnStack:
2500 /* Pass by addr on stack */
2501 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2504 for (i = 0; i < ainfo->nregs; ++i) {
2505 if (ainfo->esize == 4)
2506 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2508 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2509 load->dreg = mono_alloc_freg (cfg);
2510 load->inst_basereg = src->dreg;
2511 load->inst_offset = i * ainfo->esize;
2512 MONO_ADD_INS (cfg->cbb, load);
2514 if (ainfo->esize == 4) {
2517 /* See RegTypeFP in mono_arch_emit_call () */
2518 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2519 float_arg->flags |= MONO_INST_VOLATILE;
2520 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2522 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2523 fad->vreg = float_arg->dreg;
2524 fad->hreg = ainfo->reg + i;
2526 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2528 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2534 for (i = 0; i < ainfo->size; ++i) {
2535 dreg = mono_alloc_ireg (cfg);
2536 switch (struct_size) {
2538 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2541 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2544 tmpreg = mono_alloc_ireg (cfg);
2545 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2546 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2547 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2548 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2549 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2550 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2551 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2554 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2557 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2558 soffset += sizeof (gpointer);
2559 struct_size -= sizeof (gpointer);
2561 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2563 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2569 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2571 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2574 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2577 if (COMPILE_LLVM (cfg)) {
2578 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2580 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2581 ins->sreg1 = MONO_LVREG_LS (val->dreg);
2582 ins->sreg2 = MONO_LVREG_MS (val->dreg);
2583 MONO_ADD_INS (cfg->cbb, ins);
2588 case MONO_ARM_FPU_NONE:
2589 if (ret->type == MONO_TYPE_R8) {
2592 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2593 ins->dreg = cfg->ret->dreg;
2594 ins->sreg1 = val->dreg;
2595 MONO_ADD_INS (cfg->cbb, ins);
2598 if (ret->type == MONO_TYPE_R4) {
2599 /* Already converted to an int in method_to_ir () */
2600 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2604 case MONO_ARM_FPU_VFP:
2605 case MONO_ARM_FPU_VFP_HARD:
2606 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2609 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2610 ins->dreg = cfg->ret->dreg;
2611 ins->sreg1 = val->dreg;
2612 MONO_ADD_INS (cfg->cbb, ins);
2617 g_assert_not_reached ();
2621 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2624 #endif /* #ifndef DISABLE_JIT */
2627 mono_arch_is_inst_imm (gint64 imm)
2633 MonoMethodSignature *sig;
2636 MonoType **param_types;
2640 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2644 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2647 switch (cinfo->ret.storage) {
2649 case RegTypeGeneral:
2650 case RegTypeIRegPair:
2651 case RegTypeStructByAddr:
2662 for (i = 0; i < cinfo->nargs; ++i) {
2663 ArgInfo *ainfo = &cinfo->args [i];
2666 switch (ainfo->storage) {
2667 case RegTypeGeneral:
2668 case RegTypeIRegPair:
2669 case RegTypeBaseGen:
2673 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2676 case RegTypeStructByVal:
2677 if (ainfo->size == 0)
2678 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2680 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2681 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2689 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2690 for (i = 0; i < sig->param_count; ++i) {
2691 MonoType *t = sig->params [i];
2696 t = mini_get_underlying_type (t);
2719 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2721 ArchDynCallInfo *info;
2725 cinfo = get_call_info (NULL, sig);
2727 if (!dyn_call_supported (cinfo, sig)) {
2732 info = g_new0 (ArchDynCallInfo, 1);
2733 // FIXME: Preprocess the info to speed up start_dyn_call ()
2735 info->cinfo = cinfo;
2736 info->rtype = mini_get_underlying_type (sig->ret);
2737 info->param_types = g_new0 (MonoType*, sig->param_count);
2738 for (i = 0; i < sig->param_count; ++i)
2739 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2741 return (MonoDynCallInfo*)info;
2745 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2747 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2749 g_free (ainfo->cinfo);
2754 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2756 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2757 DynCallArgs *p = (DynCallArgs*)buf;
2758 int arg_index, greg, i, j, pindex;
2759 MonoMethodSignature *sig = dinfo->sig;
2761 g_assert (buf_len >= sizeof (DynCallArgs));
2771 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2772 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2777 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2778 p->regs [greg ++] = (mgreg_t)ret;
2780 for (i = pindex; i < sig->param_count; i++) {
2781 MonoType *t = dinfo->param_types [i];
2782 gpointer *arg = args [arg_index ++];
2783 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2786 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2788 } else if (ainfo->storage == RegTypeFP) {
2789 } else if (ainfo->storage == RegTypeBase) {
2790 slot = PARAM_REGS + (ainfo->offset / 4);
2791 } else if (ainfo->storage == RegTypeBaseGen) {
2792 /* slot + 1 is the first stack slot, so the code below will work */
2795 g_assert_not_reached ();
2799 p->regs [slot] = (mgreg_t)*arg;
2804 case MONO_TYPE_STRING:
2805 case MONO_TYPE_CLASS:
2806 case MONO_TYPE_ARRAY:
2807 case MONO_TYPE_SZARRAY:
2808 case MONO_TYPE_OBJECT:
2812 p->regs [slot] = (mgreg_t)*arg;
2815 p->regs [slot] = *(guint8*)arg;
2818 p->regs [slot] = *(gint8*)arg;
2821 p->regs [slot] = *(gint16*)arg;
2824 p->regs [slot] = *(guint16*)arg;
2827 p->regs [slot] = *(gint32*)arg;
2830 p->regs [slot] = *(guint32*)arg;
2834 p->regs [slot ++] = (mgreg_t)arg [0];
2835 p->regs [slot] = (mgreg_t)arg [1];
2838 if (ainfo->storage == RegTypeFP) {
2839 float f = *(float*)arg;
2840 p->fpregs [ainfo->reg / 2] = *(double*)&f;
2843 p->regs [slot] = *(mgreg_t*)arg;
2847 if (ainfo->storage == RegTypeFP) {
2848 p->fpregs [ainfo->reg / 2] = *(double*)arg;
2851 p->regs [slot ++] = (mgreg_t)arg [0];
2852 p->regs [slot] = (mgreg_t)arg [1];
2855 case MONO_TYPE_GENERICINST:
2856 if (MONO_TYPE_IS_REFERENCE (t)) {
2857 p->regs [slot] = (mgreg_t)*arg;
2860 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2861 MonoClass *klass = mono_class_from_mono_type (t);
2862 guint8 *nullable_buf;
2865 size = mono_class_value_size (klass, NULL);
2866 nullable_buf = g_alloca (size);
2867 g_assert (nullable_buf);
2869 /* The argument pointed to by arg is either a boxed vtype or null */
2870 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2872 arg = (gpointer*)nullable_buf;
2878 case MONO_TYPE_VALUETYPE:
2879 g_assert (ainfo->storage == RegTypeStructByVal);
2881 if (ainfo->size == 0)
2882 slot = PARAM_REGS + (ainfo->offset / 4);
2886 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2887 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2890 g_assert_not_reached ();
2896 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2898 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2899 DynCallArgs *p = (DynCallArgs*)buf;
2900 MonoType *ptype = ainfo->rtype;
2901 guint8 *ret = p->ret;
2902 mgreg_t res = p->res;
2903 mgreg_t res2 = p->res2;
2905 switch (ptype->type) {
2906 case MONO_TYPE_VOID:
2907 *(gpointer*)ret = NULL;
2909 case MONO_TYPE_STRING:
2910 case MONO_TYPE_CLASS:
2911 case MONO_TYPE_ARRAY:
2912 case MONO_TYPE_SZARRAY:
2913 case MONO_TYPE_OBJECT:
2917 *(gpointer*)ret = (gpointer)res;
2923 *(guint8*)ret = res;
2926 *(gint16*)ret = res;
2929 *(guint16*)ret = res;
2932 *(gint32*)ret = res;
2935 *(guint32*)ret = res;
2939 /* This handles endianness as well */
2940 ((gint32*)ret) [0] = res;
2941 ((gint32*)ret) [1] = res2;
2943 case MONO_TYPE_GENERICINST:
2944 if (MONO_TYPE_IS_REFERENCE (ptype)) {
2945 *(gpointer*)ret = (gpointer)res;
2950 case MONO_TYPE_VALUETYPE:
2951 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
2957 *(float*)ret = *(float*)&p->fpregs [0];
2959 *(float*)ret = *(float*)&res;
2961 case MONO_TYPE_R8: {
2965 if (IS_HARD_FLOAT) {
2966 *(double*)ret = p->fpregs [0];
2971 *(double*)ret = *(double*)®s;
2976 g_assert_not_reached ();
2983 * Allow tracing to work with this interface (with an optional argument)
2987 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2991 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2992 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2993 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2994 code = emit_call_reg (code, ARMREG_R2);
3008 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3011 int save_mode = SAVE_NONE;
3013 MonoMethod *method = cfg->method;
3014 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
3015 int rtype = ret_type->type;
3016 int save_offset = cfg->param_area;
3020 offset = code - cfg->native_code;
3021 /* we need about 16 instructions */
3022 if (offset > (cfg->code_size - 16 * 4)) {
3023 cfg->code_size *= 2;
3024 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3025 code = cfg->native_code + offset;
3028 case MONO_TYPE_VOID:
3029 /* special case string .ctor icall */
3030 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3031 save_mode = SAVE_ONE;
3033 save_mode = SAVE_NONE;
3037 save_mode = SAVE_TWO;
3041 save_mode = SAVE_ONE_FP;
3043 save_mode = SAVE_ONE;
3047 save_mode = SAVE_TWO_FP;
3049 save_mode = SAVE_TWO;
3051 case MONO_TYPE_GENERICINST:
3052 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3053 save_mode = SAVE_ONE;
3057 case MONO_TYPE_VALUETYPE:
3058 save_mode = SAVE_STRUCT;
3061 save_mode = SAVE_ONE;
3065 switch (save_mode) {
3067 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3068 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3069 if (enable_arguments) {
3070 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3071 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3075 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3076 if (enable_arguments) {
3077 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3081 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3082 if (enable_arguments) {
3083 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3087 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3088 if (enable_arguments) {
3089 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3093 if (enable_arguments) {
3094 /* FIXME: get the actual address */
3095 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3103 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3104 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3105 code = emit_call_reg (code, ARMREG_IP);
3107 switch (save_mode) {
3109 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3110 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3113 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3116 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3119 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3130 * The immediate field for cond branches is big enough for all reasonable methods
3132 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3133 if (0 && ins->inst_true_bb->native_offset) { \
3134 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3136 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3137 ARM_B_COND (code, (condcode), 0); \
3140 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3142 /* emit an exception if condition is fail
3144 * We assign the extra code used to throw the implicit exceptions
3145 * to cfg->bb_exit as far as the big branch handling is concerned
3147 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3149 mono_add_patch_info (cfg, code - cfg->native_code, \
3150 MONO_PATCH_INFO_EXC, exc_name); \
3151 ARM_BL_COND (code, (condcode), 0); \
3154 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3157 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3162 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3166 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3167 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3169 switch (ins->opcode) {
3172 /* Already done by an arch-independent pass */
3174 case OP_LOAD_MEMBASE:
3175 case OP_LOADI4_MEMBASE:
3177 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3178 * OP_LOAD_MEMBASE offset(basereg), reg
3180 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3181 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3182 ins->inst_basereg == last_ins->inst_destbasereg &&
3183 ins->inst_offset == last_ins->inst_offset) {
3184 if (ins->dreg == last_ins->sreg1) {
3185 MONO_DELETE_INS (bb, ins);
3188 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3189 ins->opcode = OP_MOVE;
3190 ins->sreg1 = last_ins->sreg1;
3194 * Note: reg1 must be different from the basereg in the second load
3195 * OP_LOAD_MEMBASE offset(basereg), reg1
3196 * OP_LOAD_MEMBASE offset(basereg), reg2
3198 * OP_LOAD_MEMBASE offset(basereg), reg1
3199 * OP_MOVE reg1, reg2
3201 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3202 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3203 ins->inst_basereg != last_ins->dreg &&
3204 ins->inst_basereg == last_ins->inst_basereg &&
3205 ins->inst_offset == last_ins->inst_offset) {
3207 if (ins->dreg == last_ins->dreg) {
3208 MONO_DELETE_INS (bb, ins);
3211 ins->opcode = OP_MOVE;
3212 ins->sreg1 = last_ins->dreg;
3215 //g_assert_not_reached ();
3219 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3220 * OP_LOAD_MEMBASE offset(basereg), reg
3222 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3223 * OP_ICONST reg, imm
3225 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3226 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3227 ins->inst_basereg == last_ins->inst_destbasereg &&
3228 ins->inst_offset == last_ins->inst_offset) {
3229 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3230 ins->opcode = OP_ICONST;
3231 ins->inst_c0 = last_ins->inst_imm;
3232 g_assert_not_reached (); // check this rule
3236 case OP_LOADU1_MEMBASE:
3237 case OP_LOADI1_MEMBASE:
3238 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3239 ins->inst_basereg == last_ins->inst_destbasereg &&
3240 ins->inst_offset == last_ins->inst_offset) {
3241 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3242 ins->sreg1 = last_ins->sreg1;
3245 case OP_LOADU2_MEMBASE:
3246 case OP_LOADI2_MEMBASE:
3247 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3248 ins->inst_basereg == last_ins->inst_destbasereg &&
3249 ins->inst_offset == last_ins->inst_offset) {
3250 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3251 ins->sreg1 = last_ins->sreg1;
3255 ins->opcode = OP_MOVE;
3259 if (ins->dreg == ins->sreg1) {
3260 MONO_DELETE_INS (bb, ins);
3264 * OP_MOVE sreg, dreg
3265 * OP_MOVE dreg, sreg
3267 if (last_ins && last_ins->opcode == OP_MOVE &&
3268 ins->sreg1 == last_ins->dreg &&
3269 ins->dreg == last_ins->sreg1) {
3270 MONO_DELETE_INS (bb, ins);
3279 * the branch_cc_table should maintain the order of these
3293 branch_cc_table [] = {
3307 #define ADD_NEW_INS(cfg,dest,op) do { \
3308 MONO_INST_NEW ((cfg), (dest), (op)); \
3309 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3313 map_to_reg_reg_op (int op)
3322 case OP_COMPARE_IMM:
3324 case OP_ICOMPARE_IMM:
3338 case OP_LOAD_MEMBASE:
3339 return OP_LOAD_MEMINDEX;
3340 case OP_LOADI4_MEMBASE:
3341 return OP_LOADI4_MEMINDEX;
3342 case OP_LOADU4_MEMBASE:
3343 return OP_LOADU4_MEMINDEX;
3344 case OP_LOADU1_MEMBASE:
3345 return OP_LOADU1_MEMINDEX;
3346 case OP_LOADI2_MEMBASE:
3347 return OP_LOADI2_MEMINDEX;
3348 case OP_LOADU2_MEMBASE:
3349 return OP_LOADU2_MEMINDEX;
3350 case OP_LOADI1_MEMBASE:
3351 return OP_LOADI1_MEMINDEX;
3352 case OP_STOREI1_MEMBASE_REG:
3353 return OP_STOREI1_MEMINDEX;
3354 case OP_STOREI2_MEMBASE_REG:
3355 return OP_STOREI2_MEMINDEX;
3356 case OP_STOREI4_MEMBASE_REG:
3357 return OP_STOREI4_MEMINDEX;
3358 case OP_STORE_MEMBASE_REG:
3359 return OP_STORE_MEMINDEX;
3360 case OP_STORER4_MEMBASE_REG:
3361 return OP_STORER4_MEMINDEX;
3362 case OP_STORER8_MEMBASE_REG:
3363 return OP_STORER8_MEMINDEX;
3364 case OP_STORE_MEMBASE_IMM:
3365 return OP_STORE_MEMBASE_REG;
3366 case OP_STOREI1_MEMBASE_IMM:
3367 return OP_STOREI1_MEMBASE_REG;
3368 case OP_STOREI2_MEMBASE_IMM:
3369 return OP_STOREI2_MEMBASE_REG;
3370 case OP_STOREI4_MEMBASE_IMM:
3371 return OP_STOREI4_MEMBASE_REG;
3373 g_assert_not_reached ();
3377 * Remove from the instruction list the instructions that can't be
3378 * represented with very simple instructions with no register
3382 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3384 MonoInst *ins, *temp, *last_ins = NULL;
3385 int rot_amount, imm8, low_imm;
3387 MONO_BB_FOR_EACH_INS (bb, ins) {
3389 switch (ins->opcode) {
3393 case OP_COMPARE_IMM:
3394 case OP_ICOMPARE_IMM:
3408 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3409 int opcode2 = mono_op_imm_to_op (ins->opcode);
3410 ADD_NEW_INS (cfg, temp, OP_ICONST);
3411 temp->inst_c0 = ins->inst_imm;
3412 temp->dreg = mono_alloc_ireg (cfg);
3413 ins->sreg2 = temp->dreg;
3415 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3416 ins->opcode = opcode2;
3418 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3424 if (ins->inst_imm == 1) {
3425 ins->opcode = OP_MOVE;
3428 if (ins->inst_imm == 0) {
3429 ins->opcode = OP_ICONST;
3433 imm8 = mono_is_power_of_two (ins->inst_imm);
3435 ins->opcode = OP_SHL_IMM;
3436 ins->inst_imm = imm8;
3439 ADD_NEW_INS (cfg, temp, OP_ICONST);
3440 temp->inst_c0 = ins->inst_imm;
3441 temp->dreg = mono_alloc_ireg (cfg);
3442 ins->sreg2 = temp->dreg;
3443 ins->opcode = OP_IMUL;
3449 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3450 /* ARM sets the C flag to 1 if there was _no_ overflow */
3451 ins->next->opcode = OP_COND_EXC_NC;
3454 case OP_IDIV_UN_IMM:
3456 case OP_IREM_UN_IMM: {
3457 int opcode2 = mono_op_imm_to_op (ins->opcode);
3458 ADD_NEW_INS (cfg, temp, OP_ICONST);
3459 temp->inst_c0 = ins->inst_imm;
3460 temp->dreg = mono_alloc_ireg (cfg);
3461 ins->sreg2 = temp->dreg;
3463 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3464 ins->opcode = opcode2;
3467 case OP_LOCALLOC_IMM:
3468 ADD_NEW_INS (cfg, temp, OP_ICONST);
3469 temp->inst_c0 = ins->inst_imm;
3470 temp->dreg = mono_alloc_ireg (cfg);
3471 ins->sreg1 = temp->dreg;
3472 ins->opcode = OP_LOCALLOC;
3474 case OP_LOAD_MEMBASE:
3475 case OP_LOADI4_MEMBASE:
3476 case OP_LOADU4_MEMBASE:
3477 case OP_LOADU1_MEMBASE:
3478 /* we can do two things: load the immed in a register
3479 * and use an indexed load, or see if the immed can be
3480 * represented as an ad_imm + a load with a smaller offset
3481 * that fits. We just do the first for now, optimize later.
3483 if (arm_is_imm12 (ins->inst_offset))
3485 ADD_NEW_INS (cfg, temp, OP_ICONST);
3486 temp->inst_c0 = ins->inst_offset;
3487 temp->dreg = mono_alloc_ireg (cfg);
3488 ins->sreg2 = temp->dreg;
3489 ins->opcode = map_to_reg_reg_op (ins->opcode);
3491 case OP_LOADI2_MEMBASE:
3492 case OP_LOADU2_MEMBASE:
3493 case OP_LOADI1_MEMBASE:
3494 if (arm_is_imm8 (ins->inst_offset))
3496 ADD_NEW_INS (cfg, temp, OP_ICONST);
3497 temp->inst_c0 = ins->inst_offset;
3498 temp->dreg = mono_alloc_ireg (cfg);
3499 ins->sreg2 = temp->dreg;
3500 ins->opcode = map_to_reg_reg_op (ins->opcode);
3502 case OP_LOADR4_MEMBASE:
3503 case OP_LOADR8_MEMBASE:
3504 if (arm_is_fpimm8 (ins->inst_offset))
3506 low_imm = ins->inst_offset & 0x1ff;
3507 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3508 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3509 temp->inst_imm = ins->inst_offset & ~0x1ff;
3510 temp->sreg1 = ins->inst_basereg;
3511 temp->dreg = mono_alloc_ireg (cfg);
3512 ins->inst_basereg = temp->dreg;
3513 ins->inst_offset = low_imm;
3517 ADD_NEW_INS (cfg, temp, OP_ICONST);
3518 temp->inst_c0 = ins->inst_offset;
3519 temp->dreg = mono_alloc_ireg (cfg);
3521 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3522 add_ins->sreg1 = ins->inst_basereg;
3523 add_ins->sreg2 = temp->dreg;
3524 add_ins->dreg = mono_alloc_ireg (cfg);
3526 ins->inst_basereg = add_ins->dreg;
3527 ins->inst_offset = 0;
3530 case OP_STORE_MEMBASE_REG:
3531 case OP_STOREI4_MEMBASE_REG:
3532 case OP_STOREI1_MEMBASE_REG:
3533 if (arm_is_imm12 (ins->inst_offset))
3535 ADD_NEW_INS (cfg, temp, OP_ICONST);
3536 temp->inst_c0 = ins->inst_offset;
3537 temp->dreg = mono_alloc_ireg (cfg);
3538 ins->sreg2 = temp->dreg;
3539 ins->opcode = map_to_reg_reg_op (ins->opcode);
3541 case OP_STOREI2_MEMBASE_REG:
3542 if (arm_is_imm8 (ins->inst_offset))
3544 ADD_NEW_INS (cfg, temp, OP_ICONST);
3545 temp->inst_c0 = ins->inst_offset;
3546 temp->dreg = mono_alloc_ireg (cfg);
3547 ins->sreg2 = temp->dreg;
3548 ins->opcode = map_to_reg_reg_op (ins->opcode);
3550 case OP_STORER4_MEMBASE_REG:
3551 case OP_STORER8_MEMBASE_REG:
3552 if (arm_is_fpimm8 (ins->inst_offset))
3554 low_imm = ins->inst_offset & 0x1ff;
3555 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3556 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3557 temp->inst_imm = ins->inst_offset & ~0x1ff;
3558 temp->sreg1 = ins->inst_destbasereg;
3559 temp->dreg = mono_alloc_ireg (cfg);
3560 ins->inst_destbasereg = temp->dreg;
3561 ins->inst_offset = low_imm;
3565 ADD_NEW_INS (cfg, temp, OP_ICONST);
3566 temp->inst_c0 = ins->inst_offset;
3567 temp->dreg = mono_alloc_ireg (cfg);
3569 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3570 add_ins->sreg1 = ins->inst_destbasereg;
3571 add_ins->sreg2 = temp->dreg;
3572 add_ins->dreg = mono_alloc_ireg (cfg);
3574 ins->inst_destbasereg = add_ins->dreg;
3575 ins->inst_offset = 0;
3578 case OP_STORE_MEMBASE_IMM:
3579 case OP_STOREI1_MEMBASE_IMM:
3580 case OP_STOREI2_MEMBASE_IMM:
3581 case OP_STOREI4_MEMBASE_IMM:
3582 ADD_NEW_INS (cfg, temp, OP_ICONST);
3583 temp->inst_c0 = ins->inst_imm;
3584 temp->dreg = mono_alloc_ireg (cfg);
3585 ins->sreg1 = temp->dreg;
3586 ins->opcode = map_to_reg_reg_op (ins->opcode);
3588 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3591 gboolean swap = FALSE;
3595 /* Optimized away */
3600 /* Some fp compares require swapped operands */
3601 switch (ins->next->opcode) {
3603 ins->next->opcode = OP_FBLT;
3607 ins->next->opcode = OP_FBLT_UN;
3611 ins->next->opcode = OP_FBGE;
3615 ins->next->opcode = OP_FBGE_UN;
3623 ins->sreg1 = ins->sreg2;
3632 bb->last_ins = last_ins;
3633 bb->max_vreg = cfg->next_vreg;
3637 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3641 if (long_ins->opcode == OP_LNEG) {
3643 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), 0);
3644 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
3650 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3652 /* sreg is a float, dreg is an integer reg */
3654 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3656 ARM_TOSIZD (code, vfp_scratch1, sreg);
3658 ARM_TOUIZD (code, vfp_scratch1, sreg);
3659 ARM_FMRS (code, dreg, vfp_scratch1);
3660 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3664 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3665 else if (size == 2) {
3666 ARM_SHL_IMM (code, dreg, dreg, 16);
3667 ARM_SHR_IMM (code, dreg, dreg, 16);
3671 ARM_SHL_IMM (code, dreg, dreg, 24);
3672 ARM_SAR_IMM (code, dreg, dreg, 24);
3673 } else if (size == 2) {
3674 ARM_SHL_IMM (code, dreg, dreg, 16);
3675 ARM_SAR_IMM (code, dreg, dreg, 16);
3682 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3684 /* sreg is a float, dreg is an integer reg */
3686 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3688 ARM_TOSIZS (code, vfp_scratch1, sreg);
3690 ARM_TOUIZS (code, vfp_scratch1, sreg);
3691 ARM_FMRS (code, dreg, vfp_scratch1);
3692 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3696 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3697 else if (size == 2) {
3698 ARM_SHL_IMM (code, dreg, dreg, 16);
3699 ARM_SHR_IMM (code, dreg, dreg, 16);
3703 ARM_SHL_IMM (code, dreg, dreg, 24);
3704 ARM_SAR_IMM (code, dreg, dreg, 24);
3705 } else if (size == 2) {
3706 ARM_SHL_IMM (code, dreg, dreg, 16);
3707 ARM_SAR_IMM (code, dreg, dreg, 16);
3713 #endif /* #ifndef DISABLE_JIT */
3715 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3718 emit_thunk (guint8 *code, gconstpointer target)
3722 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3723 if (thumb_supported)
3724 ARM_BX (code, ARMREG_IP);
3726 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3727 *(guint32*)code = (guint32)target;
3729 mono_arch_flush_icache (p, code - p);
3733 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3735 MonoJitInfo *ji = NULL;
3736 MonoThunkJitInfo *info;
3739 guint8 *orig_target;
3740 guint8 *target_thunk;
3743 domain = mono_domain_get ();
3747 * This can be called multiple times during JITting,
3748 * save the current position in cfg->arch to avoid
3749 * doing a O(n^2) search.
3751 if (!cfg->arch.thunks) {
3752 cfg->arch.thunks = cfg->thunks;
3753 cfg->arch.thunks_size = cfg->thunk_area;
3755 thunks = cfg->arch.thunks;
3756 thunks_size = cfg->arch.thunks_size;
3758 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3759 g_assert_not_reached ();
3762 g_assert (*(guint32*)thunks == 0);
3763 emit_thunk (thunks, target);
3764 arm_patch (code, thunks);
3766 cfg->arch.thunks += THUNK_SIZE;
3767 cfg->arch.thunks_size -= THUNK_SIZE;
3769 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3771 info = mono_jit_info_get_thunk_info (ji);
3774 thunks = (guint8*)ji->code_start + info->thunks_offset;
3775 thunks_size = info->thunks_size;
3777 orig_target = mono_arch_get_call_target (code + 4);
3779 mono_mini_arch_lock ();
3781 target_thunk = NULL;
3782 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3783 /* The call already points to a thunk, because of trampolines etc. */
3784 target_thunk = orig_target;
3786 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3787 if (((guint32*)p) [0] == 0) {
3791 } else if (((guint32*)p) [2] == (guint32)target) {
3792 /* Thunk already points to target */
3799 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3801 if (!target_thunk) {
3802 mono_mini_arch_unlock ();
3803 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3804 g_assert_not_reached ();
3807 emit_thunk (target_thunk, target);
3808 arm_patch (code, target_thunk);
3809 mono_arch_flush_icache (code, 4);
3811 mono_mini_arch_unlock ();
3816 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3818 guint32 *code32 = (void*)code;
3819 guint32 ins = *code32;
3820 guint32 prim = (ins >> 25) & 7;
3821 guint32 tval = GPOINTER_TO_UINT (target);
3823 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3824 if (prim == 5) { /* 101b */
3825 /* the diff starts 8 bytes from the branch opcode */
3826 gint diff = target - code - 8;
3828 gint tmask = 0xffffffff;
3829 if (tval & 1) { /* entering thumb mode */
3830 diff = target - 1 - code - 8;
3831 g_assert (thumb_supported);
3832 tbits = 0xf << 28; /* bl->blx bit pattern */
3833 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3834 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3838 tmask = ~(1 << 24); /* clear the link bit */
3839 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3844 if (diff <= 33554431) {
3846 ins = (ins & 0xff000000) | diff;
3848 *code32 = ins | tbits;
3852 /* diff between 0 and -33554432 */
3853 if (diff >= -33554432) {
3855 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3857 *code32 = ins | tbits;
3862 handle_thunk (cfg, domain, code, target);
3867 * The alternative call sequences looks like this:
3869 * ldr ip, [pc] // loads the address constant
3870 * b 1f // jumps around the constant
3871 * address constant embedded in the code
3876 * There are two cases for patching:
3877 * a) at the end of method emission: in this case code points to the start
3878 * of the call sequence
3879 * b) during runtime patching of the call site: in this case code points
3880 * to the mov pc, ip instruction
3882 * We have to handle also the thunk jump code sequence:
3886 * address constant // execution never reaches here
3888 if ((ins & 0x0ffffff0) == 0x12fff10) {
3889 /* Branch and exchange: the address is constructed in a reg
3890 * We can patch BX when the code sequence is the following:
3891 * ldr ip, [pc, #0] ; 0x8
3898 guint8 *emit = (guint8*)ccode;
3899 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3901 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3902 ARM_BX (emit, ARMREG_IP);
3904 /*patching from magic trampoline*/
3905 if (ins == ccode [3]) {
3906 g_assert (code32 [-4] == ccode [0]);
3907 g_assert (code32 [-3] == ccode [1]);
3908 g_assert (code32 [-1] == ccode [2]);
3909 code32 [-2] = (guint32)target;
3912 /*patching from JIT*/
3913 if (ins == ccode [0]) {
3914 g_assert (code32 [1] == ccode [1]);
3915 g_assert (code32 [3] == ccode [2]);
3916 g_assert (code32 [4] == ccode [3]);
3917 code32 [2] = (guint32)target;
3920 g_assert_not_reached ();
3921 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3929 guint8 *emit = (guint8*)ccode;
3930 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3932 ARM_BLX_REG (emit, ARMREG_IP);
3934 g_assert (code32 [-3] == ccode [0]);
3935 g_assert (code32 [-2] == ccode [1]);
3936 g_assert (code32 [0] == ccode [2]);
3938 code32 [-1] = (guint32)target;
3941 guint32 *tmp = ccode;
3942 guint8 *emit = (guint8*)tmp;
3943 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3944 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3945 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3946 ARM_BX (emit, ARMREG_IP);
3947 if (ins == ccode [2]) {
3948 g_assert_not_reached (); // should be -2 ...
3949 code32 [-1] = (guint32)target;
3952 if (ins == ccode [0]) {
3953 /* handles both thunk jump code and the far call sequence */
3954 code32 [2] = (guint32)target;
3957 g_assert_not_reached ();
3959 // g_print ("patched with 0x%08x\n", ins);
3963 arm_patch (guchar *code, const guchar *target)
3965 arm_patch_general (NULL, NULL, code, target);
3969 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3970 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3971 * to be used with the emit macros.
3972 * Return -1 otherwise.
3975 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3978 for (i = 0; i < 31; i+= 2) {
3979 res = (val << (32 - i)) | (val >> i);
3982 *rot_amount = i? 32 - i: 0;
3989 * Emits in code a sequence of instructions that load the value 'val'
3990 * into the dreg register. Uses at most 4 instructions.
3993 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3995 int imm8, rot_amount;
3997 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3998 /* skip the constant pool */
4004 if (mini_get_debug_options()->single_imm_size && v7_supported) {
4005 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4006 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4010 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4011 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4012 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4013 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4016 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4018 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4022 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4024 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4026 if (val & 0xFF0000) {
4027 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4029 if (val & 0xFF000000) {
4030 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4032 } else if (val & 0xFF00) {
4033 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4034 if (val & 0xFF0000) {
4035 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4037 if (val & 0xFF000000) {
4038 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4040 } else if (val & 0xFF0000) {
4041 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4042 if (val & 0xFF000000) {
4043 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4046 //g_assert_not_reached ();
4052 mono_arm_thumb_supported (void)
4054 return thumb_supported;
4060 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4065 call = (MonoCallInst*)ins;
4066 cinfo = call->call_info;
4068 switch (cinfo->ret.storage) {
4069 case RegTypeStructByVal:
4071 MonoInst *loc = cfg->arch.vret_addr_loc;
4074 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
4075 /* The JIT treats this as a normal call */
4079 /* Load the destination address */
4080 g_assert (loc && loc->opcode == OP_REGOFFSET);
4082 if (arm_is_imm12 (loc->inst_offset)) {
4083 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4085 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4086 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4089 if (cinfo->ret.storage == RegTypeStructByVal) {
4090 int rsize = cinfo->ret.struct_size;
4092 for (i = 0; i < cinfo->ret.nregs; ++i) {
4093 g_assert (rsize >= 0);
4098 ARM_STRB_IMM (code, i, ARMREG_LR, i * 4);
4101 ARM_STRH_IMM (code, i, ARMREG_LR, i * 4);
4104 ARM_STR_IMM (code, i, ARMREG_LR, i * 4);
4110 for (i = 0; i < cinfo->ret.nregs; ++i) {
4111 if (cinfo->ret.esize == 4)
4112 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4114 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4123 switch (ins->opcode) {
4126 case OP_FCALL_MEMBASE:
4128 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4129 if (sig_ret->type == MONO_TYPE_R4) {
4130 if (IS_HARD_FLOAT) {
4131 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4133 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4134 ARM_CVTS (code, ins->dreg, ins->dreg);
4137 if (IS_HARD_FLOAT) {
4138 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4140 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4147 case OP_RCALL_MEMBASE: {
4152 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4153 g_assert (sig_ret->type == MONO_TYPE_R4);
4154 if (IS_HARD_FLOAT) {
4155 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4157 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4158 ARM_CPYS (code, ins->dreg, ins->dreg);
4170 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4175 guint8 *code = cfg->native_code + cfg->code_len;
4176 MonoInst *last_ins = NULL;
4177 guint last_offset = 0;
4179 int imm8, rot_amount;
4181 /* we don't align basic blocks of loops on arm */
4183 if (cfg->verbose_level > 2)
4184 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4186 cpos = bb->max_offset;
4188 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4189 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4190 //g_assert (!mono_compile_aot);
4193 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4194 /* this is not thread save, but good enough */
4195 /* fixme: howto handle overflows? */
4196 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4199 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4200 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4201 (gpointer)"mono_break");
4202 code = emit_call_seq (cfg, code);
4205 MONO_BB_FOR_EACH_INS (bb, ins) {
4206 offset = code - cfg->native_code;
4208 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4210 if (offset > (cfg->code_size - max_len - 16)) {
4211 cfg->code_size *= 2;
4212 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4213 code = cfg->native_code + offset;
4215 // if (ins->cil_code)
4216 // g_print ("cil code\n");
4217 mono_debug_record_line_number (cfg, ins, offset);
4219 switch (ins->opcode) {
4220 case OP_MEMORY_BARRIER:
4222 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4223 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4227 code = emit_tls_get (code, ins->dreg, ins->inst_offset);
4230 code = emit_tls_set (code, ins->sreg1, ins->inst_offset);
4232 case OP_ATOMIC_EXCHANGE_I4:
4233 case OP_ATOMIC_CAS_I4:
4234 case OP_ATOMIC_ADD_I4: {
4238 g_assert (v7_supported);
4241 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4243 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4245 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4249 g_assert (cfg->arch.atomic_tmp_offset != -1);
4250 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4252 switch (ins->opcode) {
4253 case OP_ATOMIC_EXCHANGE_I4:
4255 ARM_DMB (code, ARM_DMB_SY);
4256 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4257 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4258 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4260 ARM_B_COND (code, ARMCOND_NE, 0);
4261 arm_patch (buf [1], buf [0]);
4263 case OP_ATOMIC_CAS_I4:
4264 ARM_DMB (code, ARM_DMB_SY);
4266 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4267 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4269 ARM_B_COND (code, ARMCOND_NE, 0);
4270 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4271 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4273 ARM_B_COND (code, ARMCOND_NE, 0);
4274 arm_patch (buf [2], buf [0]);
4275 arm_patch (buf [1], code);
4277 case OP_ATOMIC_ADD_I4:
4279 ARM_DMB (code, ARM_DMB_SY);
4280 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4281 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4282 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4283 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4285 ARM_B_COND (code, ARMCOND_NE, 0);
4286 arm_patch (buf [1], buf [0]);
4289 g_assert_not_reached ();
4292 ARM_DMB (code, ARM_DMB_SY);
4293 if (tmpreg != ins->dreg)
4294 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4295 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4298 case OP_ATOMIC_LOAD_I1:
4299 case OP_ATOMIC_LOAD_U1:
4300 case OP_ATOMIC_LOAD_I2:
4301 case OP_ATOMIC_LOAD_U2:
4302 case OP_ATOMIC_LOAD_I4:
4303 case OP_ATOMIC_LOAD_U4:
4304 case OP_ATOMIC_LOAD_R4:
4305 case OP_ATOMIC_LOAD_R8: {
4306 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4307 ARM_DMB (code, ARM_DMB_SY);
4309 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4311 switch (ins->opcode) {
4312 case OP_ATOMIC_LOAD_I1:
4313 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4315 case OP_ATOMIC_LOAD_U1:
4316 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4318 case OP_ATOMIC_LOAD_I2:
4319 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4321 case OP_ATOMIC_LOAD_U2:
4322 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4324 case OP_ATOMIC_LOAD_I4:
4325 case OP_ATOMIC_LOAD_U4:
4326 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4328 case OP_ATOMIC_LOAD_R4:
4330 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4331 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4333 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4334 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4335 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4336 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4337 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4340 case OP_ATOMIC_LOAD_R8:
4341 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4342 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4346 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4347 ARM_DMB (code, ARM_DMB_SY);
4350 case OP_ATOMIC_STORE_I1:
4351 case OP_ATOMIC_STORE_U1:
4352 case OP_ATOMIC_STORE_I2:
4353 case OP_ATOMIC_STORE_U2:
4354 case OP_ATOMIC_STORE_I4:
4355 case OP_ATOMIC_STORE_U4:
4356 case OP_ATOMIC_STORE_R4:
4357 case OP_ATOMIC_STORE_R8: {
4358 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4359 ARM_DMB (code, ARM_DMB_SY);
4361 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4363 switch (ins->opcode) {
4364 case OP_ATOMIC_STORE_I1:
4365 case OP_ATOMIC_STORE_U1:
4366 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4368 case OP_ATOMIC_STORE_I2:
4369 case OP_ATOMIC_STORE_U2:
4370 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4372 case OP_ATOMIC_STORE_I4:
4373 case OP_ATOMIC_STORE_U4:
4374 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4376 case OP_ATOMIC_STORE_R4:
4378 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4379 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4381 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4382 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4383 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4384 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4385 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4388 case OP_ATOMIC_STORE_R8:
4389 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4390 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4394 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4395 ARM_DMB (code, ARM_DMB_SY);
4399 ARM_SMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4402 ARM_UMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4404 case OP_STOREI1_MEMBASE_IMM:
4405 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4406 g_assert (arm_is_imm12 (ins->inst_offset));
4407 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4409 case OP_STOREI2_MEMBASE_IMM:
4410 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4411 g_assert (arm_is_imm8 (ins->inst_offset));
4412 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4414 case OP_STORE_MEMBASE_IMM:
4415 case OP_STOREI4_MEMBASE_IMM:
4416 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4417 g_assert (arm_is_imm12 (ins->inst_offset));
4418 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4420 case OP_STOREI1_MEMBASE_REG:
4421 g_assert (arm_is_imm12 (ins->inst_offset));
4422 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4424 case OP_STOREI2_MEMBASE_REG:
4425 g_assert (arm_is_imm8 (ins->inst_offset));
4426 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4428 case OP_STORE_MEMBASE_REG:
4429 case OP_STOREI4_MEMBASE_REG:
4430 /* this case is special, since it happens for spill code after lowering has been called */
4431 if (arm_is_imm12 (ins->inst_offset)) {
4432 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4434 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4435 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4438 case OP_STOREI1_MEMINDEX:
4439 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4441 case OP_STOREI2_MEMINDEX:
4442 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4444 case OP_STORE_MEMINDEX:
4445 case OP_STOREI4_MEMINDEX:
4446 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4449 g_assert_not_reached ();
4451 case OP_LOAD_MEMINDEX:
4452 case OP_LOADI4_MEMINDEX:
4453 case OP_LOADU4_MEMINDEX:
4454 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4456 case OP_LOADI1_MEMINDEX:
4457 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4459 case OP_LOADU1_MEMINDEX:
4460 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4462 case OP_LOADI2_MEMINDEX:
4463 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4465 case OP_LOADU2_MEMINDEX:
4466 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4468 case OP_LOAD_MEMBASE:
4469 case OP_LOADI4_MEMBASE:
4470 case OP_LOADU4_MEMBASE:
4471 /* this case is special, since it happens for spill code after lowering has been called */
4472 if (arm_is_imm12 (ins->inst_offset)) {
4473 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4475 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4476 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4479 case OP_LOADI1_MEMBASE:
4480 g_assert (arm_is_imm8 (ins->inst_offset));
4481 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4483 case OP_LOADU1_MEMBASE:
4484 g_assert (arm_is_imm12 (ins->inst_offset));
4485 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4487 case OP_LOADU2_MEMBASE:
4488 g_assert (arm_is_imm8 (ins->inst_offset));
4489 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4491 case OP_LOADI2_MEMBASE:
4492 g_assert (arm_is_imm8 (ins->inst_offset));
4493 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4495 case OP_ICONV_TO_I1:
4496 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4497 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4499 case OP_ICONV_TO_I2:
4500 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4501 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4503 case OP_ICONV_TO_U1:
4504 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4506 case OP_ICONV_TO_U2:
4507 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4508 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4512 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4514 case OP_COMPARE_IMM:
4515 case OP_ICOMPARE_IMM:
4516 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4517 g_assert (imm8 >= 0);
4518 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4522 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4523 * So instead of emitting a trap, we emit a call a C function and place a
4526 //*(int*)code = 0xef9f0001;
4529 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4530 (gpointer)"mono_break");
4531 code = emit_call_seq (cfg, code);
4533 case OP_RELAXED_NOP:
4538 case OP_DUMMY_STORE:
4539 case OP_DUMMY_ICONST:
4540 case OP_DUMMY_R8CONST:
4541 case OP_NOT_REACHED:
4544 case OP_IL_SEQ_POINT:
4545 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4547 case OP_SEQ_POINT: {
4549 MonoInst *info_var = cfg->arch.seq_point_info_var;
4550 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4551 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4552 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4554 int dreg = ARMREG_LR;
4557 if (cfg->soft_breakpoints) {
4558 g_assert (!cfg->compile_aot);
4563 * For AOT, we use one got slot per method, which will point to a
4564 * SeqPointInfo structure, containing all the information required
4565 * by the code below.
4567 if (cfg->compile_aot) {
4568 g_assert (info_var);
4569 g_assert (info_var->opcode == OP_REGOFFSET);
4570 g_assert (arm_is_imm12 (info_var->inst_offset));
4573 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4575 * Read from the single stepping trigger page. This will cause a
4576 * SIGSEGV when single stepping is enabled.
4577 * We do this _before_ the breakpoint, so single stepping after
4578 * a breakpoint is hit will step to the next IL offset.
4580 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4583 /* Single step check */
4584 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4585 if (cfg->soft_breakpoints) {
4586 /* Load the address of the sequence point method variable. */
4587 var = ss_method_var;
4589 g_assert (var->opcode == OP_REGOFFSET);
4590 g_assert (arm_is_imm12 (var->inst_offset));
4591 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4593 /* Read the value and check whether it is non-zero. */
4594 ARM_LDR_IMM (code, dreg, dreg, 0);
4595 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4596 /* Call it conditionally. */
4597 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4599 if (cfg->compile_aot) {
4600 /* Load the trigger page addr from the variable initialized in the prolog */
4601 var = ss_trigger_page_var;
4603 g_assert (var->opcode == OP_REGOFFSET);
4604 g_assert (arm_is_imm12 (var->inst_offset));
4605 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4607 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4609 *(int*)code = (int)ss_trigger_page;
4612 ARM_LDR_IMM (code, dreg, dreg, 0);
4616 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4618 /* Breakpoint check */
4619 if (cfg->compile_aot) {
4620 guint32 offset = code - cfg->native_code;
4623 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4624 /* Add the offset */
4625 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4626 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4627 if (arm_is_imm12 ((int)val)) {
4628 ARM_LDR_IMM (code, dreg, dreg, val);
4630 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4632 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4634 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4635 g_assert (!(val & 0xFF000000));
4637 ARM_LDR_IMM (code, dreg, dreg, 0);
4639 /* What is faster, a branch or a load ? */
4640 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4641 /* The breakpoint instruction */
4642 if (cfg->soft_breakpoints)
4643 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4645 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4646 } else if (cfg->soft_breakpoints) {
4647 /* Load the address of the breakpoint method into ip. */
4648 var = bp_method_var;
4650 g_assert (var->opcode == OP_REGOFFSET);
4651 g_assert (arm_is_imm12 (var->inst_offset));
4652 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4655 * A placeholder for a possible breakpoint inserted by
4656 * mono_arch_set_breakpoint ().
4661 * A placeholder for a possible breakpoint inserted by
4662 * mono_arch_set_breakpoint ().
4664 for (i = 0; i < 4; ++i)
4669 * Add an additional nop so skipping the bp doesn't cause the ip to point
4670 * to another IL offset.
4678 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4681 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4685 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4688 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4689 g_assert (imm8 >= 0);
4690 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4694 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4695 g_assert (imm8 >= 0);
4696 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4700 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4701 g_assert (imm8 >= 0);
4702 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4705 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4706 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4708 case OP_IADD_OVF_UN:
4709 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4710 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4713 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4714 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4716 case OP_ISUB_OVF_UN:
4717 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4718 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4720 case OP_ADD_OVF_CARRY:
4721 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4722 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4724 case OP_ADD_OVF_UN_CARRY:
4725 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4726 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4728 case OP_SUB_OVF_CARRY:
4729 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4730 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4732 case OP_SUB_OVF_UN_CARRY:
4733 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4734 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4738 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4741 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4742 g_assert (imm8 >= 0);
4743 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4746 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4750 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4754 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4755 g_assert (imm8 >= 0);
4756 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4760 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4761 g_assert (imm8 >= 0);
4762 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4764 case OP_ARM_RSBS_IMM:
4765 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4766 g_assert (imm8 >= 0);
4767 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4769 case OP_ARM_RSC_IMM:
4770 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4771 g_assert (imm8 >= 0);
4772 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4775 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4779 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4780 g_assert (imm8 >= 0);
4781 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4784 g_assert (v7s_supported || v7k_supported);
4785 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4788 g_assert (v7s_supported || v7k_supported);
4789 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4792 g_assert (v7s_supported || v7k_supported);
4793 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4794 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4797 g_assert (v7s_supported || v7k_supported);
4798 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4799 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4803 g_assert_not_reached ();
4805 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4809 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4810 g_assert (imm8 >= 0);
4811 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4814 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4818 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4819 g_assert (imm8 >= 0);
4820 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4823 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4828 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4829 else if (ins->dreg != ins->sreg1)
4830 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4833 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4838 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4839 else if (ins->dreg != ins->sreg1)
4840 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4843 case OP_ISHR_UN_IMM:
4845 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4846 else if (ins->dreg != ins->sreg1)
4847 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4850 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4853 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4856 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4859 if (ins->dreg == ins->sreg2)
4860 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4862 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4865 g_assert_not_reached ();
4868 /* FIXME: handle ovf/ sreg2 != dreg */
4869 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4870 /* FIXME: MUL doesn't set the C/O flags on ARM */
4872 case OP_IMUL_OVF_UN:
4873 /* FIXME: handle ovf/ sreg2 != dreg */
4874 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4875 /* FIXME: MUL doesn't set the C/O flags on ARM */
4878 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4881 /* Load the GOT offset */
4882 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4883 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4885 *(gpointer*)code = NULL;
4887 /* Load the value from the GOT */
4888 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4890 case OP_OBJC_GET_SELECTOR:
4891 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4892 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4894 *(gpointer*)code = NULL;
4896 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4898 case OP_ICONV_TO_I4:
4899 case OP_ICONV_TO_U4:
4901 if (ins->dreg != ins->sreg1)
4902 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4905 int saved = ins->sreg2;
4906 if (ins->sreg2 == ARM_LSW_REG) {
4907 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4910 if (ins->sreg1 != ARM_LSW_REG)
4911 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4912 if (saved != ARM_MSW_REG)
4913 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4917 if (IS_VFP && ins->dreg != ins->sreg1)
4918 ARM_CPYD (code, ins->dreg, ins->sreg1);
4921 if (IS_VFP && ins->dreg != ins->sreg1)
4922 ARM_CPYS (code, ins->dreg, ins->sreg1);
4924 case OP_MOVE_F_TO_I4:
4926 ARM_FMRS (code, ins->dreg, ins->sreg1);
4928 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4929 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4930 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4931 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4934 case OP_MOVE_I4_TO_F:
4936 ARM_FMSR (code, ins->dreg, ins->sreg1);
4938 ARM_FMSR (code, ins->dreg, ins->sreg1);
4939 ARM_CVTS (code, ins->dreg, ins->dreg);
4942 case OP_FCONV_TO_R4:
4945 ARM_CVTD (code, ins->dreg, ins->sreg1);
4947 ARM_CVTD (code, ins->dreg, ins->sreg1);
4948 ARM_CVTS (code, ins->dreg, ins->dreg);
4953 MonoCallInst *call = (MonoCallInst*)ins;
4956 * The stack looks like the following:
4957 * <caller argument area>
4960 * <callee argument area>
4961 * Need to copy the arguments from the callee argument area to
4962 * the caller argument area, and pop the frame.
4964 if (call->stack_usage) {
4965 int i, prev_sp_offset = 0;
4967 /* Compute size of saved registers restored below */
4969 prev_sp_offset = 2 * 4;
4971 prev_sp_offset = 1 * 4;
4972 for (i = 0; i < 16; ++i) {
4973 if (cfg->used_int_regs & (1 << i))
4974 prev_sp_offset += 4;
4977 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
4979 /* Copy arguments on the stack to our argument area */
4980 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
4981 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
4982 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
4987 * Keep in sync with mono_arch_emit_epilog
4989 g_assert (!cfg->method->save_lmf);
4991 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4993 if (cfg->used_int_regs)
4994 ARM_POP (code, cfg->used_int_regs);
4995 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4997 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
5000 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
5001 if (cfg->compile_aot) {
5002 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5004 *(gpointer*)code = NULL;
5006 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5008 code = mono_arm_patchable_b (code, ARMCOND_AL);
5009 cfg->thunk_area += THUNK_SIZE;
5014 /* ensure ins->sreg1 is not NULL */
5015 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5018 g_assert (cfg->sig_cookie < 128);
5019 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5020 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5030 call = (MonoCallInst*)ins;
5033 code = emit_float_args (cfg, call, code, &max_len, &offset);
5035 if (ins->flags & MONO_INST_HAS_METHOD)
5036 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5038 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5039 code = emit_call_seq (cfg, code);
5040 ins->flags |= MONO_INST_GC_CALLSITE;
5041 ins->backend.pc_offset = code - cfg->native_code;
5042 code = emit_move_return_value (cfg, ins, code);
5049 case OP_VOIDCALL_REG:
5052 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5054 code = emit_call_reg (code, ins->sreg1);
5055 ins->flags |= MONO_INST_GC_CALLSITE;
5056 ins->backend.pc_offset = code - cfg->native_code;
5057 code = emit_move_return_value (cfg, ins, code);
5059 case OP_FCALL_MEMBASE:
5060 case OP_RCALL_MEMBASE:
5061 case OP_LCALL_MEMBASE:
5062 case OP_VCALL_MEMBASE:
5063 case OP_VCALL2_MEMBASE:
5064 case OP_VOIDCALL_MEMBASE:
5065 case OP_CALL_MEMBASE: {
5066 g_assert (ins->sreg1 != ARMREG_LR);
5067 call = (MonoCallInst*)ins;
5070 code = emit_float_args (cfg, call, code, &max_len, &offset);
5071 if (!arm_is_imm12 (ins->inst_offset)) {
5072 /* sreg1 might be IP */
5073 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5074 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5075 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_LR);
5076 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5077 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, 0);
5079 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5080 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5082 ins->flags |= MONO_INST_GC_CALLSITE;
5083 ins->backend.pc_offset = code - cfg->native_code;
5084 code = emit_move_return_value (cfg, ins, code);
5087 case OP_GENERIC_CLASS_INIT: {
5091 byte_offset = MONO_STRUCT_OFFSET (MonoVTable, initialized);
5093 g_assert (arm_is_imm8 (byte_offset));
5094 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5095 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5097 ARM_B_COND (code, ARMCOND_NE, 0);
5099 /* Uninitialized case */
5100 g_assert (ins->sreg1 == ARMREG_R0);
5102 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5103 (gpointer)"mono_generic_class_init");
5104 code = emit_call_seq (cfg, code);
5106 /* Initialized case */
5107 arm_patch (jump, code);
5111 /* round the size to 8 bytes */
5112 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5113 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5114 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5115 /* memzero the area: dreg holds the size, sp is the pointer */
5116 if (ins->flags & MONO_INST_INIT) {
5117 guint8 *start_loop, *branch_to_cond;
5118 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5119 branch_to_cond = code;
5122 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5123 arm_patch (branch_to_cond, code);
5124 /* decrement by 4 and set flags */
5125 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5126 ARM_B_COND (code, ARMCOND_GE, 0);
5127 arm_patch (code - 4, start_loop);
5129 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5130 if (cfg->param_area)
5131 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5136 MonoInst *var = cfg->dyn_call_var;
5139 g_assert (var->opcode == OP_REGOFFSET);
5140 g_assert (arm_is_imm12 (var->inst_offset));
5142 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5143 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5145 ARM_MOV_REG_REG (code, ARMREG_IP, ins->sreg2);
5147 /* Save args buffer */
5148 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5150 /* Set stack slots using R0 as scratch reg */
5151 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5152 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5153 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5154 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5157 /* Set fp argument registers */
5158 if (IS_HARD_FLOAT) {
5159 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, has_fpregs));
5160 ARM_CMP_REG_IMM (code, ARMREG_R0, 0, 0);
5162 ARM_B_COND (code, ARMCOND_EQ, 0);
5163 for (i = 0; i < FP_PARAM_REGS; ++i) {
5164 int offset = MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * sizeof (double));
5165 g_assert (arm_is_fpimm8 (offset));
5166 ARM_FLDD (code, i * 2, ARMREG_LR, offset);
5168 arm_patch (buf [0], code);
5171 /* Set argument registers */
5172 for (i = 0; i < PARAM_REGS; ++i)
5173 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5176 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5177 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5180 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5181 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5182 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5184 ARM_FSTD (code, ARM_VFP_D0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, fpregs));
5188 if (ins->sreg1 != ARMREG_R0)
5189 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5190 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5191 (gpointer)"mono_arch_throw_exception");
5192 code = emit_call_seq (cfg, code);
5196 if (ins->sreg1 != ARMREG_R0)
5197 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5198 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5199 (gpointer)"mono_arch_rethrow_exception");
5200 code = emit_call_seq (cfg, code);
5203 case OP_START_HANDLER: {
5204 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5205 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5208 /* Reserve a param area, see filter-stack.exe */
5210 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5211 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5213 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5214 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5218 if (arm_is_imm12 (spvar->inst_offset)) {
5219 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5221 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5222 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5226 case OP_ENDFILTER: {
5227 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5228 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5231 /* Free the param area */
5233 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5234 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5236 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5237 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5241 if (ins->sreg1 != ARMREG_R0)
5242 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5243 if (arm_is_imm12 (spvar->inst_offset)) {
5244 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5246 g_assert (ARMREG_IP != spvar->inst_basereg);
5247 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5248 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5250 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5253 case OP_ENDFINALLY: {
5254 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5255 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5258 /* Free the param area */
5260 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5261 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5263 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5264 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5268 if (arm_is_imm12 (spvar->inst_offset)) {
5269 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5271 g_assert (ARMREG_IP != spvar->inst_basereg);
5272 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5273 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5275 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5278 case OP_CALL_HANDLER:
5279 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5280 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5281 cfg->thunk_area += THUNK_SIZE;
5282 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5285 if (ins->dreg != ARMREG_R0)
5286 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5290 ins->inst_c0 = code - cfg->native_code;
5293 /*if (ins->inst_target_bb->native_offset) {
5295 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5297 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5298 code = mono_arm_patchable_b (code, ARMCOND_AL);
5302 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5306 * In the normal case we have:
5307 * ldr pc, [pc, ins->sreg1 << 2]
5310 * ldr lr, [pc, ins->sreg1 << 2]
5312 * After follows the data.
5313 * FIXME: add aot support.
5315 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5316 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5317 if (offset + max_len > (cfg->code_size - 16)) {
5318 cfg->code_size += max_len;
5319 cfg->code_size *= 2;
5320 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5321 code = cfg->native_code + offset;
5323 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5325 code += 4 * GPOINTER_TO_INT (ins->klass);
5329 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5330 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5334 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5335 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5339 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5340 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5344 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5345 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5349 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5350 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5353 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5354 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5357 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5358 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5361 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5362 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5365 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5366 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5369 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5370 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5372 case OP_COND_EXC_EQ:
5373 case OP_COND_EXC_NE_UN:
5374 case OP_COND_EXC_LT:
5375 case OP_COND_EXC_LT_UN:
5376 case OP_COND_EXC_GT:
5377 case OP_COND_EXC_GT_UN:
5378 case OP_COND_EXC_GE:
5379 case OP_COND_EXC_GE_UN:
5380 case OP_COND_EXC_LE:
5381 case OP_COND_EXC_LE_UN:
5382 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5384 case OP_COND_EXC_IEQ:
5385 case OP_COND_EXC_INE_UN:
5386 case OP_COND_EXC_ILT:
5387 case OP_COND_EXC_ILT_UN:
5388 case OP_COND_EXC_IGT:
5389 case OP_COND_EXC_IGT_UN:
5390 case OP_COND_EXC_IGE:
5391 case OP_COND_EXC_IGE_UN:
5392 case OP_COND_EXC_ILE:
5393 case OP_COND_EXC_ILE_UN:
5394 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5397 case OP_COND_EXC_IC:
5398 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5400 case OP_COND_EXC_OV:
5401 case OP_COND_EXC_IOV:
5402 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5404 case OP_COND_EXC_NC:
5405 case OP_COND_EXC_INC:
5406 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5408 case OP_COND_EXC_NO:
5409 case OP_COND_EXC_INO:
5410 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5422 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5425 /* floating point opcodes */
5427 if (cfg->compile_aot) {
5428 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5430 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5432 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5435 /* FIXME: we can optimize the imm load by dealing with part of
5436 * the displacement in LDFD (aligning to 512).
5438 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5439 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5443 if (cfg->compile_aot) {
5444 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5446 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5449 ARM_CVTS (code, ins->dreg, ins->dreg);
5451 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5452 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5454 ARM_CVTS (code, ins->dreg, ins->dreg);
5457 case OP_STORER8_MEMBASE_REG:
5458 /* This is generated by the local regalloc pass which runs after the lowering pass */
5459 if (!arm_is_fpimm8 (ins->inst_offset)) {
5460 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5461 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5462 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5464 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5467 case OP_LOADR8_MEMBASE:
5468 /* This is generated by the local regalloc pass which runs after the lowering pass */
5469 if (!arm_is_fpimm8 (ins->inst_offset)) {
5470 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5471 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5472 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5474 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5477 case OP_STORER4_MEMBASE_REG:
5478 g_assert (arm_is_fpimm8 (ins->inst_offset));
5480 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5482 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5483 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5484 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5485 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5488 case OP_LOADR4_MEMBASE:
5490 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5492 g_assert (arm_is_fpimm8 (ins->inst_offset));
5493 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5494 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5495 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5496 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5499 case OP_ICONV_TO_R_UN: {
5500 g_assert_not_reached ();
5503 case OP_ICONV_TO_R4:
5505 ARM_FMSR (code, ins->dreg, ins->sreg1);
5506 ARM_FSITOS (code, ins->dreg, ins->dreg);
5508 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5509 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5510 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5511 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5512 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5515 case OP_ICONV_TO_R8:
5516 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5517 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5518 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5519 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5523 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5524 if (sig_ret->type == MONO_TYPE_R4) {
5526 if (IS_HARD_FLOAT) {
5527 if (ins->sreg1 != ARM_VFP_D0)
5528 ARM_CPYS (code, ARM_VFP_D0, ins->sreg1);
5530 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5533 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5536 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5540 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5542 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5546 case OP_FCONV_TO_I1:
5547 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5549 case OP_FCONV_TO_U1:
5550 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5552 case OP_FCONV_TO_I2:
5553 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5555 case OP_FCONV_TO_U2:
5556 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5558 case OP_FCONV_TO_I4:
5560 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5562 case OP_FCONV_TO_U4:
5564 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5566 case OP_FCONV_TO_I8:
5567 case OP_FCONV_TO_U8:
5568 g_assert_not_reached ();
5569 /* Implemented as helper calls */
5571 case OP_LCONV_TO_R_UN:
5572 g_assert_not_reached ();
5573 /* Implemented as helper calls */
5575 case OP_LCONV_TO_OVF_I4_2: {
5576 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5578 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5581 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5582 high_bit_not_set = code;
5583 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5585 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5586 valid_negative = code;
5587 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5588 invalid_negative = code;
5589 ARM_B_COND (code, ARMCOND_AL, 0);
5591 arm_patch (high_bit_not_set, code);
5593 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5594 valid_positive = code;
5595 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5597 arm_patch (invalid_negative, code);
5598 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5600 arm_patch (valid_negative, code);
5601 arm_patch (valid_positive, code);
5603 if (ins->dreg != ins->sreg1)
5604 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5608 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5611 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5614 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5617 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5620 ARM_NEGD (code, ins->dreg, ins->sreg1);
5624 g_assert_not_reached ();
5628 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5634 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5639 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5642 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5643 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5647 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5650 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5651 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5655 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5658 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5659 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5660 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5664 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5667 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5668 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5672 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5675 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5676 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5677 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5681 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5684 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5685 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5689 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5692 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5693 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5697 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5700 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5701 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5704 /* ARM FPA flags table:
5705 * N Less than ARMCOND_MI
5706 * Z Equal ARMCOND_EQ
5707 * C Greater Than or Equal ARMCOND_CS
5708 * V Unordered ARMCOND_VS
5711 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5714 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5717 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5720 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5721 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5727 g_assert_not_reached ();
5731 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5733 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5734 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5735 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5739 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5740 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5745 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5746 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5748 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5749 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5751 *(guint32*)code = 0xffffffff;
5753 *(guint32*)code = 0x7fefffff;
5755 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5757 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "OverflowException");
5758 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5760 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "OverflowException");
5761 ARM_CPYD (code, ins->dreg, ins->sreg1);
5763 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5764 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5769 case OP_RCONV_TO_I1:
5770 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5772 case OP_RCONV_TO_U1:
5773 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5775 case OP_RCONV_TO_I2:
5776 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5778 case OP_RCONV_TO_U2:
5779 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5781 case OP_RCONV_TO_I4:
5782 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5784 case OP_RCONV_TO_U4:
5785 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5787 case OP_RCONV_TO_R4:
5789 if (ins->dreg != ins->sreg1)
5790 ARM_CPYS (code, ins->dreg, ins->sreg1);
5792 case OP_RCONV_TO_R8:
5794 ARM_CVTS (code, ins->dreg, ins->sreg1);
5797 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5800 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5803 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5806 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5809 ARM_NEGS (code, ins->dreg, ins->sreg1);
5813 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5816 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5817 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5821 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5824 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5825 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5829 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5832 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5833 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5834 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5838 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5841 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5842 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5846 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5849 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5850 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5851 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5855 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5858 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5859 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5863 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5866 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5867 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5871 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5874 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5875 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5878 case OP_GC_LIVENESS_DEF:
5879 case OP_GC_LIVENESS_USE:
5880 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5881 ins->backend.pc_offset = code - cfg->native_code;
5883 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5884 ins->backend.pc_offset = code - cfg->native_code;
5885 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5887 case OP_GC_SAFE_POINT: {
5890 g_assert (mono_threads_is_coop_enabled ());
5892 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5893 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5895 ARM_B_COND (code, ARMCOND_EQ, 0);
5896 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
5897 code = emit_call_seq (cfg, code);
5898 arm_patch (buf [0], code);
5903 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5904 g_assert_not_reached ();
5907 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5908 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5909 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5910 g_assert_not_reached ();
5916 last_offset = offset;
5919 cfg->code_len = code - cfg->native_code;
5922 #endif /* DISABLE_JIT */
5925 mono_arch_register_lowlevel_calls (void)
5927 /* The signature doesn't matter */
5928 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5929 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5930 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
5933 #define patch_lis_ori(ip,val) do {\
5934 guint16 *__lis_ori = (guint16*)(ip); \
5935 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
5936 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
5940 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5942 unsigned char *ip = ji->ip.i + code;
5944 if (ji->type == MONO_PATCH_INFO_SWITCH) {
5948 case MONO_PATCH_INFO_SWITCH: {
5949 gpointer *jt = (gpointer*)(ip + 8);
5951 /* jt is the inlined jump table, 2 instructions after ip
5952 * In the normal case we store the absolute addresses,
5953 * otherwise the displacements.
5955 for (i = 0; i < ji->data.table->table_size; i++)
5956 jt [i] = code + (int)ji->data.table->table [i];
5959 case MONO_PATCH_INFO_IP:
5960 g_assert_not_reached ();
5961 patch_lis_ori (ip, ip);
5963 case MONO_PATCH_INFO_METHOD_REL:
5964 g_assert_not_reached ();
5965 *((gpointer *)(ip)) = target;
5967 case MONO_PATCH_INFO_METHODCONST:
5968 case MONO_PATCH_INFO_CLASS:
5969 case MONO_PATCH_INFO_IMAGE:
5970 case MONO_PATCH_INFO_FIELD:
5971 case MONO_PATCH_INFO_VTABLE:
5972 case MONO_PATCH_INFO_IID:
5973 case MONO_PATCH_INFO_SFLDA:
5974 case MONO_PATCH_INFO_LDSTR:
5975 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
5976 case MONO_PATCH_INFO_LDTOKEN:
5977 g_assert_not_reached ();
5978 /* from OP_AOTCONST : lis + ori */
5979 patch_lis_ori (ip, target);
5981 case MONO_PATCH_INFO_R4:
5982 case MONO_PATCH_INFO_R8:
5983 g_assert_not_reached ();
5984 *((gconstpointer *)(ip + 2)) = target;
5986 case MONO_PATCH_INFO_EXC_NAME:
5987 g_assert_not_reached ();
5988 *((gconstpointer *)(ip + 1)) = target;
5990 case MONO_PATCH_INFO_NONE:
5991 case MONO_PATCH_INFO_BB_OVF:
5992 case MONO_PATCH_INFO_EXC_OVF:
5993 /* everything is dealt with at epilog output time */
5996 arm_patch_general (cfg, domain, ip, target);
6002 mono_arm_unaligned_stack (MonoMethod *method)
6004 g_assert_not_reached ();
6010 * Stack frame layout:
6012 * ------------------- fp
6013 * MonoLMF structure or saved registers
6014 * -------------------
6016 * -------------------
6018 * -------------------
6019 * optional 8 bytes for tracing
6020 * -------------------
6021 * param area size is cfg->param_area
6022 * ------------------- sp
6025 mono_arch_emit_prolog (MonoCompile *cfg)
6027 MonoMethod *method = cfg->method;
6029 MonoMethodSignature *sig;
6031 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6036 int prev_sp_offset, reg_offset;
6038 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6041 sig = mono_method_signature (method);
6042 cfg->code_size = 256 + sig->param_count * 64;
6043 code = cfg->native_code = g_malloc (cfg->code_size);
6045 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6047 alloc_size = cfg->stack_offset;
6053 * The iphone uses R7 as the frame pointer, and it points at the saved
6058 * We can't use r7 as a frame pointer since it points into the middle of
6059 * the frame, so we keep using our own frame pointer.
6060 * FIXME: Optimize this.
6062 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6063 prev_sp_offset += 8; /* r7 and lr */
6064 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6065 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6066 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6069 if (!method->save_lmf) {
6071 /* No need to push LR again */
6072 if (cfg->used_int_regs)
6073 ARM_PUSH (code, cfg->used_int_regs);
6075 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6076 prev_sp_offset += 4;
6078 for (i = 0; i < 16; ++i) {
6079 if (cfg->used_int_regs & (1 << i))
6080 prev_sp_offset += 4;
6082 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6084 for (i = 0; i < 16; ++i) {
6085 if ((cfg->used_int_regs & (1 << i))) {
6086 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6087 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6091 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6092 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6094 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6095 ARM_PUSH (code, 0x5ff0);
6096 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6097 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6099 for (i = 0; i < 16; ++i) {
6100 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6101 /* The original r7 is saved at the start */
6102 if (!(iphone_abi && i == ARMREG_R7))
6103 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6107 g_assert (reg_offset == 4 * 10);
6108 pos += sizeof (MonoLMF) - (4 * 10);
6112 orig_alloc_size = alloc_size;
6113 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6114 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6115 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6116 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6119 /* the stack used in the pushed regs */
6120 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6121 cfg->stack_usage = alloc_size;
6123 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6124 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6126 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6127 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6129 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6131 if (cfg->frame_reg != ARMREG_SP) {
6132 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6133 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6135 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6136 prev_sp_offset += alloc_size;
6138 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6139 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6141 /* compute max_offset in order to use short forward jumps
6142 * we could skip do it on arm because the immediate displacement
6143 * for jumps is large enough, it may be useful later for constant pools
6146 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6147 MonoInst *ins = bb->code;
6148 bb->max_offset = max_offset;
6150 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6153 MONO_BB_FOR_EACH_INS (bb, ins)
6154 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6157 /* stack alignment check */
6161 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6162 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6163 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6164 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6166 ARM_B_COND (code, ARMCOND_EQ, 0);
6167 if (cfg->compile_aot)
6168 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6170 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6171 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6172 code = emit_call_seq (cfg, code);
6173 arm_patch (buf [0], code);
6177 /* store runtime generic context */
6178 if (cfg->rgctx_var) {
6179 MonoInst *ins = cfg->rgctx_var;
6181 g_assert (ins->opcode == OP_REGOFFSET);
6183 if (arm_is_imm12 (ins->inst_offset)) {
6184 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6186 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6187 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6191 /* load arguments allocated to register from the stack */
6194 cinfo = get_call_info (NULL, sig);
6196 if (cinfo->ret.storage == RegTypeStructByAddr) {
6197 ArgInfo *ainfo = &cinfo->ret;
6198 inst = cfg->vret_addr;
6199 g_assert (arm_is_imm12 (inst->inst_offset));
6200 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6203 if (sig->call_convention == MONO_CALL_VARARG) {
6204 ArgInfo *cookie = &cinfo->sig_cookie;
6206 /* Save the sig cookie address */
6207 g_assert (cookie->storage == RegTypeBase);
6209 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6210 g_assert (arm_is_imm12 (cfg->sig_cookie));
6211 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6212 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6215 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6216 ArgInfo *ainfo = cinfo->args + i;
6217 inst = cfg->args [pos];
6219 if (cfg->verbose_level > 2)
6220 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6222 if (inst->opcode == OP_REGVAR) {
6223 if (ainfo->storage == RegTypeGeneral)
6224 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6225 else if (ainfo->storage == RegTypeFP) {
6226 g_assert_not_reached ();
6227 } else if (ainfo->storage == RegTypeBase) {
6228 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6229 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6231 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6232 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6235 g_assert_not_reached ();
6237 if (cfg->verbose_level > 2)
6238 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6240 switch (ainfo->storage) {
6242 for (part = 0; part < ainfo->nregs; part ++) {
6243 if (ainfo->esize == 4)
6244 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6246 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6249 case RegTypeGeneral:
6250 case RegTypeIRegPair:
6251 case RegTypeGSharedVtInReg:
6252 case RegTypeStructByAddr:
6253 switch (ainfo->size) {
6255 if (arm_is_imm12 (inst->inst_offset))
6256 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6258 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6259 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6263 if (arm_is_imm8 (inst->inst_offset)) {
6264 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6266 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6267 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6271 if (arm_is_imm12 (inst->inst_offset)) {
6272 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6274 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6275 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6277 if (arm_is_imm12 (inst->inst_offset + 4)) {
6278 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6280 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6281 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6285 if (arm_is_imm12 (inst->inst_offset)) {
6286 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6288 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6289 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6294 case RegTypeBaseGen:
6295 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6296 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6298 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6299 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6301 if (arm_is_imm12 (inst->inst_offset + 4)) {
6302 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6303 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6305 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6306 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6307 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6308 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6312 case RegTypeGSharedVtOnStack:
6313 case RegTypeStructByAddrOnStack:
6314 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6315 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6317 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6318 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6321 switch (ainfo->size) {
6323 if (arm_is_imm8 (inst->inst_offset)) {
6324 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6326 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6327 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6331 if (arm_is_imm8 (inst->inst_offset)) {
6332 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6334 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6335 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6339 if (arm_is_imm12 (inst->inst_offset)) {
6340 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6342 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6343 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6345 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6346 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6348 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6349 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6351 if (arm_is_imm12 (inst->inst_offset + 4)) {
6352 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6354 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6355 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6359 if (arm_is_imm12 (inst->inst_offset)) {
6360 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6362 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6363 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6369 int imm8, rot_amount;
6371 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6372 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6373 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6375 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6377 if (ainfo->size == 8)
6378 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6380 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6383 case RegTypeStructByVal: {
6384 int doffset = inst->inst_offset;
6388 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6389 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6390 if (arm_is_imm12 (doffset)) {
6391 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6393 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6394 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6396 soffset += sizeof (gpointer);
6397 doffset += sizeof (gpointer);
6399 if (ainfo->vtsize) {
6400 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6401 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6402 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6407 g_assert_not_reached ();
6414 if (method->save_lmf)
6415 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6418 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6420 if (cfg->arch.seq_point_info_var) {
6421 MonoInst *ins = cfg->arch.seq_point_info_var;
6423 /* Initialize the variable from a GOT slot */
6424 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6425 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6427 *(gpointer*)code = NULL;
6429 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6431 g_assert (ins->opcode == OP_REGOFFSET);
6433 if (arm_is_imm12 (ins->inst_offset)) {
6434 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6436 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6437 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6441 /* Initialize ss_trigger_page_var */
6442 if (!cfg->soft_breakpoints) {
6443 MonoInst *info_var = cfg->arch.seq_point_info_var;
6444 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6445 int dreg = ARMREG_LR;
6448 g_assert (info_var->opcode == OP_REGOFFSET);
6449 g_assert (arm_is_imm12 (info_var->inst_offset));
6451 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6452 /* Load the trigger page addr */
6453 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6454 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6458 if (cfg->arch.seq_point_ss_method_var) {
6459 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6460 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6462 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6463 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6465 if (cfg->compile_aot) {
6466 MonoInst *info_var = cfg->arch.seq_point_info_var;
6467 int dreg = ARMREG_LR;
6469 g_assert (info_var->opcode == OP_REGOFFSET);
6470 g_assert (arm_is_imm12 (info_var->inst_offset));
6472 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6473 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr));
6474 ARM_STR_IMM (code, dreg, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6476 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6477 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6479 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6481 *(gpointer*)code = &single_step_tramp;
6483 *(gpointer*)code = breakpoint_tramp;
6486 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6487 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6488 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6489 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6493 cfg->code_len = code - cfg->native_code;
6494 g_assert (cfg->code_len < cfg->code_size);
6501 mono_arch_emit_epilog (MonoCompile *cfg)
6503 MonoMethod *method = cfg->method;
6504 int pos, i, rot_amount;
6505 int max_epilog_size = 16 + 20*4;
6509 if (cfg->method->save_lmf)
6510 max_epilog_size += 128;
6512 if (mono_jit_trace_calls != NULL)
6513 max_epilog_size += 50;
6515 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6516 max_epilog_size += 50;
6518 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6519 cfg->code_size *= 2;
6520 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6521 cfg->stat_code_reallocs++;
6525 * Keep in sync with OP_JMP
6527 code = cfg->native_code + cfg->code_len;
6529 /* Save the uwind state which is needed by the out-of-line code */
6530 mono_emit_unwind_op_remember_state (cfg, code);
6532 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6533 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6537 /* Load returned vtypes into registers if needed */
6538 cinfo = cfg->arch.cinfo;
6539 switch (cinfo->ret.storage) {
6540 case RegTypeStructByVal: {
6541 MonoInst *ins = cfg->ret;
6543 if (cinfo->ret.nregs == 1) {
6544 if (arm_is_imm12 (ins->inst_offset)) {
6545 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6547 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6548 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6551 for (i = 0; i < cinfo->ret.nregs; ++i) {
6552 int offset = ins->inst_offset + (i * 4);
6553 if (arm_is_imm12 (offset)) {
6554 ARM_LDR_IMM (code, i, ins->inst_basereg, offset);
6556 code = mono_arm_emit_load_imm (code, ARMREG_LR, offset);
6557 ARM_LDR_REG_REG (code, i, ins->inst_basereg, ARMREG_LR);
6564 MonoInst *ins = cfg->ret;
6566 for (i = 0; i < cinfo->ret.nregs; ++i) {
6567 if (cinfo->ret.esize == 4)
6568 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6570 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6578 if (method->save_lmf) {
6579 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6580 /* all but r0-r3, sp and pc */
6581 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6584 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6586 /* This points to r4 inside MonoLMF->iregs */
6587 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6589 regmask = 0x9ff0; /* restore lr to pc */
6590 /* Skip caller saved registers not used by the method */
6591 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6592 regmask &= ~(1 << reg);
6597 /* Restored later */
6598 regmask &= ~(1 << ARMREG_PC);
6599 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6600 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6601 for (i = 0; i < 16; i++) {
6602 if (regmask & (1 << i))
6605 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6607 ARM_POP (code, regmask);
6609 for (i = 0; i < 16; i++) {
6610 if (regmask & (1 << i))
6611 mono_emit_unwind_op_same_value (cfg, code, i);
6613 /* Restore saved r7, restore LR to PC */
6614 /* Skip lr from the lmf */
6615 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6616 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6617 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6618 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6621 int i, nused_int_regs = 0;
6623 for (i = 0; i < 16; i++) {
6624 if (cfg->used_int_regs & (1 << i))
6628 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6629 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6631 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6632 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6635 if (cfg->frame_reg != ARMREG_SP) {
6636 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6640 /* Restore saved gregs */
6641 if (cfg->used_int_regs) {
6642 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6643 ARM_POP (code, cfg->used_int_regs);
6644 for (i = 0; i < 16; i++) {
6645 if (cfg->used_int_regs & (1 << i))
6646 mono_emit_unwind_op_same_value (cfg, code, i);
6649 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6650 /* Restore saved r7, restore LR to PC */
6651 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6653 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6654 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6658 /* Restore the unwind state to be the same as before the epilog */
6659 mono_emit_unwind_op_restore_state (cfg, code);
6661 cfg->code_len = code - cfg->native_code;
6663 g_assert (cfg->code_len < cfg->code_size);
6668 mono_arch_emit_exceptions (MonoCompile *cfg)
6670 MonoJumpInfo *patch_info;
6673 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6674 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6675 int max_epilog_size = 50;
6677 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6678 exc_throw_pos [i] = NULL;
6679 exc_throw_found [i] = 0;
6682 /* count the number of exception infos */
6685 * make sure we have enough space for exceptions
6687 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6688 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6689 i = mini_exception_id_by_name (patch_info->data.target);
6690 if (!exc_throw_found [i]) {
6691 max_epilog_size += 32;
6692 exc_throw_found [i] = TRUE;
6697 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6698 cfg->code_size *= 2;
6699 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6700 cfg->stat_code_reallocs++;
6703 code = cfg->native_code + cfg->code_len;
6705 /* add code to raise exceptions */
6706 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6707 switch (patch_info->type) {
6708 case MONO_PATCH_INFO_EXC: {
6709 MonoClass *exc_class;
6710 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6712 i = mini_exception_id_by_name (patch_info->data.target);
6713 if (exc_throw_pos [i]) {
6714 arm_patch (ip, exc_throw_pos [i]);
6715 patch_info->type = MONO_PATCH_INFO_NONE;
6718 exc_throw_pos [i] = code;
6720 arm_patch (ip, code);
6722 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6724 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6725 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6726 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6727 patch_info->data.name = "mono_arch_throw_corlib_exception";
6728 patch_info->ip.i = code - cfg->native_code;
6730 cfg->thunk_area += THUNK_SIZE;
6731 *(guint32*)(gpointer)code = exc_class->type_token - MONO_TOKEN_TYPE_DEF;
6741 cfg->code_len = code - cfg->native_code;
6743 g_assert (cfg->code_len < cfg->code_size);
6747 #endif /* #ifndef DISABLE_JIT */
6750 mono_arch_finish_init (void)
6755 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6760 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6767 mono_arch_print_tree (MonoInst *tree, int arity)
6777 mono_arch_get_patch_offset (guint8 *code)
6784 mono_arch_flush_register_windows (void)
6789 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6791 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6795 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6797 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6801 mono_arch_get_cie_program (void)
6805 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6810 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6811 #define BASE_SIZE (6 * 4)
6812 #define BSEARCH_ENTRY_SIZE (4 * 4)
6813 #define CMP_SIZE (3 * 4)
6814 #define BRANCH_SIZE (1 * 4)
6815 #define CALL_SIZE (2 * 4)
6816 #define WMC_SIZE (8 * 4)
6817 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6820 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6822 guint32 delta = DISTANCE (target, code);
6824 g_assert (delta >= 0 && delta <= 0xFFF);
6825 *target = *target | delta;
6830 #ifdef ENABLE_WRONG_METHOD_CHECK
6832 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6834 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6840 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6841 gpointer fail_tramp)
6844 arminstr_t *code, *start;
6845 gboolean large_offsets = FALSE;
6846 guint32 **constant_pool_starts;
6847 arminstr_t *vtable_target = NULL;
6848 int extra_space = 0;
6849 #ifdef ENABLE_WRONG_METHOD_CHECK
6855 constant_pool_starts = g_new0 (guint32*, count);
6857 for (i = 0; i < count; ++i) {
6858 MonoIMTCheckItem *item = imt_entries [i];
6859 if (item->is_equals) {
6860 gboolean fail_case = !item->check_target_idx && fail_tramp;
6862 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6863 item->chunk_size += 32;
6864 large_offsets = TRUE;
6867 if (item->check_target_idx || fail_case) {
6868 if (!item->compare_done || fail_case)
6869 item->chunk_size += CMP_SIZE;
6870 item->chunk_size += BRANCH_SIZE;
6872 #ifdef ENABLE_WRONG_METHOD_CHECK
6873 item->chunk_size += WMC_SIZE;
6877 item->chunk_size += 16;
6878 large_offsets = TRUE;
6880 item->chunk_size += CALL_SIZE;
6882 item->chunk_size += BSEARCH_ENTRY_SIZE;
6883 imt_entries [item->check_target_idx]->compare_done = TRUE;
6885 size += item->chunk_size;
6889 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6892 code = mono_method_alloc_generic_virtual_trampoline (domain, size);
6894 code = mono_domain_code_reserve (domain, size);
6897 unwind_ops = mono_arch_get_cie_program ();
6900 g_print ("Building IMT trampoline for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6901 for (i = 0; i < count; ++i) {
6902 MonoIMTCheckItem *item = imt_entries [i];
6903 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
6907 if (large_offsets) {
6908 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6909 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
6911 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
6912 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6914 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
6915 vtable_target = code;
6916 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
6917 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
6919 for (i = 0; i < count; ++i) {
6920 MonoIMTCheckItem *item = imt_entries [i];
6921 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
6922 gint32 vtable_offset;
6924 item->code_target = (guint8*)code;
6926 if (item->is_equals) {
6927 gboolean fail_case = !item->check_target_idx && fail_tramp;
6929 if (item->check_target_idx || fail_case) {
6930 if (!item->compare_done || fail_case) {
6932 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6933 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6935 item->jmp_code = (guint8*)code;
6936 ARM_B_COND (code, ARMCOND_NE, 0);
6938 /*Enable the commented code to assert on wrong method*/
6939 #ifdef ENABLE_WRONG_METHOD_CHECK
6941 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6942 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6944 ARM_B_COND (code, ARMCOND_EQ, 0);
6946 /* Define this if your system is so bad that gdb is failing. */
6947 #ifdef BROKEN_DEV_ENV
6948 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
6950 arm_patch (code - 1, mini_dump_bad_imt);
6954 arm_patch (cond, code);
6958 if (item->has_target_code) {
6959 /* Load target address */
6960 target_code_ins = code;
6961 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6962 /* Save it to the fourth slot */
6963 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6964 /* Restore registers and branch */
6965 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6967 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
6969 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
6970 if (!arm_is_imm12 (vtable_offset)) {
6972 * We need to branch to a computed address but we don't have
6973 * a free register to store it, since IP must contain the
6974 * vtable address. So we push the two values to the stack, and
6975 * load them both using LDM.
6977 /* Compute target address */
6978 vtable_offset_ins = code;
6979 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6980 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
6981 /* Save it to the fourth slot */
6982 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6983 /* Restore registers and branch */
6984 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6986 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
6988 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
6989 if (large_offsets) {
6990 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6991 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
6993 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
6994 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
6999 arm_patch (item->jmp_code, (guchar*)code);
7001 target_code_ins = code;
7002 /* Load target address */
7003 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7004 /* Save it to the fourth slot */
7005 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7006 /* Restore registers and branch */
7007 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7009 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7010 item->jmp_code = NULL;
7014 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7016 /*must emit after unconditional branch*/
7017 if (vtable_target) {
7018 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7019 item->chunk_size += 4;
7020 vtable_target = NULL;
7023 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7024 constant_pool_starts [i] = code;
7026 code += extra_space;
7030 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7031 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7033 item->jmp_code = (guint8*)code;
7034 ARM_B_COND (code, ARMCOND_HS, 0);
7039 for (i = 0; i < count; ++i) {
7040 MonoIMTCheckItem *item = imt_entries [i];
7041 if (item->jmp_code) {
7042 if (item->check_target_idx)
7043 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7045 if (i > 0 && item->is_equals) {
7047 arminstr_t *space_start = constant_pool_starts [i];
7048 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7049 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7056 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7057 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7062 g_free (constant_pool_starts);
7064 mono_arch_flush_icache ((guint8*)start, size);
7065 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7066 mono_stats.imt_trampolines_size += code - start;
7068 g_assert (DISTANCE (start, code) <= size);
7070 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7076 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7078 return ctx->regs [reg];
7082 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7084 ctx->regs [reg] = val;
7088 * mono_arch_get_trampolines:
7090 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7094 mono_arch_get_trampolines (gboolean aot)
7096 return mono_arm_get_exception_trampolines (aot);
7100 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7107 bp = MONO_CONTEXT_GET_BP (ctx);
7108 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7110 old_value = *lr_loc;
7111 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7114 *lr_loc = new_value;
7119 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7121 * mono_arch_set_breakpoint:
7123 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7124 * The location should contain code emitted by OP_SEQ_POINT.
7127 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7130 guint32 native_offset = ip - (guint8*)ji->code_start;
7131 MonoDebugOptions *opt = mini_get_debug_options ();
7134 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7136 if (!breakpoint_tramp)
7137 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7139 g_assert (native_offset % 4 == 0);
7140 g_assert (info->bp_addrs [native_offset / 4] == 0);
7141 info->bp_addrs [native_offset / 4] = opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page;
7142 } else if (opt->soft_breakpoints) {
7144 ARM_BLX_REG (code, ARMREG_LR);
7145 mono_arch_flush_icache (code - 4, 4);
7147 int dreg = ARMREG_LR;
7149 /* Read from another trigger page */
7150 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7152 *(int*)code = (int)bp_trigger_page;
7154 ARM_LDR_IMM (code, dreg, dreg, 0);
7156 mono_arch_flush_icache (code - 16, 16);
7159 /* This is currently implemented by emitting an SWI instruction, which
7160 * qemu/linux seems to convert to a SIGILL.
7162 *(int*)code = (0xef << 24) | 8;
7164 mono_arch_flush_icache (code - 4, 4);
7170 * mono_arch_clear_breakpoint:
7172 * Clear the breakpoint at IP.
7175 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7177 MonoDebugOptions *opt = mini_get_debug_options ();
7182 guint32 native_offset = ip - (guint8*)ji->code_start;
7183 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7185 if (!breakpoint_tramp)
7186 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7188 g_assert (native_offset % 4 == 0);
7189 g_assert (info->bp_addrs [native_offset / 4] == (opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page));
7190 info->bp_addrs [native_offset / 4] = 0;
7191 } else if (opt->soft_breakpoints) {
7194 mono_arch_flush_icache (code - 4, 4);
7196 for (i = 0; i < 4; ++i)
7199 mono_arch_flush_icache (ip, code - ip);
7204 * mono_arch_start_single_stepping:
7206 * Start single stepping.
7209 mono_arch_start_single_stepping (void)
7211 if (ss_trigger_page)
7212 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7214 single_step_tramp = mini_get_single_step_trampoline ();
7218 * mono_arch_stop_single_stepping:
7220 * Stop single stepping.
7223 mono_arch_stop_single_stepping (void)
7225 if (ss_trigger_page)
7226 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7228 single_step_tramp = NULL;
7232 #define DBG_SIGNAL SIGBUS
7234 #define DBG_SIGNAL SIGSEGV
7238 * mono_arch_is_single_step_event:
7240 * Return whenever the machine state in SIGCTX corresponds to a single
7244 mono_arch_is_single_step_event (void *info, void *sigctx)
7246 siginfo_t *sinfo = info;
7248 if (!ss_trigger_page)
7251 /* Sometimes the address is off by 4 */
7252 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7259 * mono_arch_is_breakpoint_event:
7261 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7264 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7266 siginfo_t *sinfo = info;
7268 if (!ss_trigger_page)
7271 if (sinfo->si_signo == DBG_SIGNAL) {
7272 /* Sometimes the address is off by 4 */
7273 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7283 * mono_arch_skip_breakpoint:
7285 * See mini-amd64.c for docs.
7288 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7290 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7294 * mono_arch_skip_single_step:
7296 * See mini-amd64.c for docs.
7299 mono_arch_skip_single_step (MonoContext *ctx)
7301 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7304 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7307 * mono_arch_get_seq_point_info:
7309 * See mini-amd64.c for docs.
7312 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7317 // FIXME: Add a free function
7319 mono_domain_lock (domain);
7320 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7322 mono_domain_unlock (domain);
7325 ji = mono_jit_info_table_find (domain, (char*)code);
7328 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7330 info->ss_trigger_page = ss_trigger_page;
7331 info->bp_trigger_page = bp_trigger_page;
7332 info->ss_tramp_addr = &single_step_tramp;
7334 mono_domain_lock (domain);
7335 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7337 mono_domain_unlock (domain);
7344 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7346 ext->lmf.previous_lmf = prev_lmf;
7347 /* Mark that this is a MonoLMFExt */
7348 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7349 ext->lmf.sp = (gssize)ext;
7353 * mono_arch_set_target:
7355 * Set the target architecture the JIT backend should generate code for, in the form
7356 * of a GNU target triplet. Only used in AOT mode.
7359 mono_arch_set_target (char *mtriple)
7361 /* The GNU target triple format is not very well documented */
7362 if (strstr (mtriple, "armv7")) {
7363 v5_supported = TRUE;
7364 v6_supported = TRUE;
7365 v7_supported = TRUE;
7367 if (strstr (mtriple, "armv6")) {
7368 v5_supported = TRUE;
7369 v6_supported = TRUE;
7371 if (strstr (mtriple, "armv7s")) {
7372 v7s_supported = TRUE;
7374 if (strstr (mtriple, "armv7k")) {
7375 v7k_supported = TRUE;
7377 if (strstr (mtriple, "thumbv7s")) {
7378 v5_supported = TRUE;
7379 v6_supported = TRUE;
7380 v7_supported = TRUE;
7381 v7s_supported = TRUE;
7382 thumb_supported = TRUE;
7383 thumb2_supported = TRUE;
7385 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7386 v5_supported = TRUE;
7387 v6_supported = TRUE;
7388 thumb_supported = TRUE;
7391 if (strstr (mtriple, "gnueabi"))
7392 eabi_supported = TRUE;
7396 mono_arch_opcode_supported (int opcode)
7399 case OP_ATOMIC_ADD_I4:
7400 case OP_ATOMIC_EXCHANGE_I4:
7401 case OP_ATOMIC_CAS_I4:
7402 case OP_ATOMIC_LOAD_I1:
7403 case OP_ATOMIC_LOAD_I2:
7404 case OP_ATOMIC_LOAD_I4:
7405 case OP_ATOMIC_LOAD_U1:
7406 case OP_ATOMIC_LOAD_U2:
7407 case OP_ATOMIC_LOAD_U4:
7408 case OP_ATOMIC_STORE_I1:
7409 case OP_ATOMIC_STORE_I2:
7410 case OP_ATOMIC_STORE_I4:
7411 case OP_ATOMIC_STORE_U1:
7412 case OP_ATOMIC_STORE_U2:
7413 case OP_ATOMIC_STORE_U4:
7414 return v7_supported;
7415 case OP_ATOMIC_LOAD_R4:
7416 case OP_ATOMIC_LOAD_R8:
7417 case OP_ATOMIC_STORE_R4:
7418 case OP_ATOMIC_STORE_R8:
7419 return v7_supported && IS_VFP;
7426 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
7428 return get_call_info (mp, sig);
7432 mono_arch_get_get_tls_tramp (void)
7438 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data)
7441 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
7442 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7444 *(gpointer*)code = NULL;
7446 /* Load the value from the GOT */
7447 ARM_LDR_REG_REG (code, dreg, ARMREG_PC, dreg);
7452 mono_arm_emit_aotconst (gpointer ji_list, guint8 *code, guint8 *buf, int dreg, int patch_type, gconstpointer data)
7454 MonoJumpInfo **ji = (MonoJumpInfo**)ji_list;
7456 *ji = mono_patch_info_list_prepend (*ji, code - buf, patch_type, data);
7457 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7459 *(gpointer*)code = NULL;
7461 ARM_LDR_REG_REG (code, dreg, ARMREG_PC, dreg);