2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
11 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
16 #include <mono/metadata/abi-details.h>
17 #include <mono/metadata/appdomain.h>
18 #include <mono/metadata/profiler-private.h>
19 #include <mono/metadata/debug-helpers.h>
20 #include <mono/utils/mono-mmap.h>
21 #include <mono/utils/mono-hwcap-arm.h>
22 #include <mono/utils/mono-memory-model.h>
23 #include <mono/utils/mono-threads-coop.h>
26 #include "mini-arm-tls.h"
30 #include "debugger-agent.h"
32 #include "mono/arch/arm/arm-vfp-codegen.h"
34 #if (defined(HAVE_KW_THREAD) && defined(__linux__) && defined(__ARM_EABI__)) \
35 || defined(TARGET_ANDROID) \
36 || (defined(TARGET_IOS) && !defined(TARGET_WATCHOS))
40 /* Sanity check: This makes no sense */
41 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
42 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
46 * IS_SOFT_FLOAT: Is full software floating point used?
47 * IS_HARD_FLOAT: Is full hardware floating point used?
48 * IS_VFP: Is hardware floating point with software ABI used?
50 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
51 * IS_VFP may delegate to mono_arch_is_soft_float ().
54 #if defined(ARM_FPU_VFP_HARD)
55 #define IS_SOFT_FLOAT (FALSE)
56 #define IS_HARD_FLOAT (TRUE)
58 #elif defined(ARM_FPU_NONE)
59 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
60 #define IS_HARD_FLOAT (FALSE)
61 #define IS_VFP (!mono_arch_is_soft_float ())
63 #define IS_SOFT_FLOAT (FALSE)
64 #define IS_HARD_FLOAT (FALSE)
68 #define THUNK_SIZE (3 * 4)
70 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
73 void sys_icache_invalidate (void *start, size_t len);
76 /* This mutex protects architecture specific caches */
77 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
78 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
79 static mono_mutex_t mini_arch_mutex;
81 static gboolean v5_supported = FALSE;
82 static gboolean v6_supported = FALSE;
83 static gboolean v7_supported = FALSE;
84 static gboolean v7s_supported = FALSE;
85 static gboolean v7k_supported = FALSE;
86 static gboolean thumb_supported = FALSE;
87 static gboolean thumb2_supported = FALSE;
89 * Whenever to use the ARM EABI
91 static gboolean eabi_supported = FALSE;
94 * Whenever to use the iphone ABI extensions:
95 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
96 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
97 * This is required for debugging/profiling tools to work, but it has some overhead so it should
98 * only be turned on in debug builds.
100 static gboolean iphone_abi = FALSE;
103 * The FPU we are generating code for. This is NOT runtime configurable right now,
104 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
106 static MonoArmFPU arm_fpu;
108 #if defined(ARM_FPU_VFP_HARD)
110 * On armhf, d0-d7 are used for argument passing and d8-d15
111 * must be preserved across calls, which leaves us no room
112 * for scratch registers. So we use d14-d15 but back up their
113 * previous contents to a stack slot before using them - see
114 * mono_arm_emit_vfp_scratch_save/_restore ().
116 static int vfp_scratch1 = ARM_VFP_D14;
117 static int vfp_scratch2 = ARM_VFP_D15;
120 * On armel, d0-d7 do not need to be preserved, so we can
121 * freely make use of them as scratch registers.
123 static int vfp_scratch1 = ARM_VFP_D0;
124 static int vfp_scratch2 = ARM_VFP_D1;
129 static gpointer single_step_tramp, breakpoint_tramp;
132 * The code generated for sequence points reads from this location, which is
133 * made read-only when single stepping is enabled.
135 static gpointer ss_trigger_page;
137 /* Enabled breakpoints read from this trigger page */
138 static gpointer bp_trigger_page;
142 * floating point support: on ARM it is a mess, there are at least 3
143 * different setups, each of which binary incompat with the other.
144 * 1) FPA: old and ugly, but unfortunately what current distros use
145 * the double binary format has the two words swapped. 8 double registers.
146 * Implemented usually by kernel emulation.
147 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
148 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
149 * 3) VFP: the new and actually sensible and useful FP support. Implemented
150 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
152 * We do not care about FPA. We will support soft float and VFP.
154 int mono_exc_esp_offset = 0;
156 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
157 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
158 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
160 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
161 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
162 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
164 //#define DEBUG_IMT 0
167 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
171 mono_arch_regname (int reg)
173 static const char * rnames[] = {
174 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
175 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
176 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
179 if (reg >= 0 && reg < 16)
185 mono_arch_fregname (int reg)
187 static const char * rnames[] = {
188 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
189 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
190 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
191 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
192 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
193 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
196 if (reg >= 0 && reg < 32)
204 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
206 int imm8, rot_amount;
207 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
208 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
212 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
213 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
215 code = mono_arm_emit_load_imm (code, dreg, imm);
216 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
221 /* If dreg == sreg, this clobbers IP */
223 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
225 int imm8, rot_amount;
226 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
227 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
231 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
232 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
234 code = mono_arm_emit_load_imm (code, dreg, imm);
235 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
241 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
243 /* we can use r0-r3, since this is called only for incoming args on the stack */
244 if (size > sizeof (gpointer) * 4) {
246 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
247 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
248 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
249 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
250 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
251 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
252 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
253 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
254 ARM_B_COND (code, ARMCOND_NE, 0);
255 arm_patch (code - 4, start_loop);
258 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
259 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
261 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
262 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
268 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
269 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
270 doffset = soffset = 0;
272 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
273 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
279 g_assert (size == 0);
284 emit_call_reg (guint8 *code, int reg)
287 ARM_BLX_REG (code, reg);
289 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
293 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
299 emit_call_seq (MonoCompile *cfg, guint8 *code)
301 if (cfg->method->dynamic) {
302 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
304 *(gpointer*)code = NULL;
306 code = emit_call_reg (code, ARMREG_IP);
310 cfg->thunk_area += THUNK_SIZE;
315 mono_arm_patchable_b (guint8 *code, int cond)
317 ARM_B_COND (code, cond, 0);
322 mono_arm_patchable_bl (guint8 *code, int cond)
324 ARM_BL_COND (code, cond, 0);
329 mono_arm_emit_tls_get (MonoCompile *cfg, guint8* code, int dreg, int tls_offset)
332 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
333 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
335 code = emit_call_seq (cfg, code);
336 if (dreg != ARMREG_R0)
337 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
339 g_assert_not_reached ();
345 mono_arm_emit_tls_get_reg (MonoCompile *cfg, guint8* code, int dreg, int tls_offset_reg)
348 if (tls_offset_reg != ARMREG_R0)
349 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
350 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
352 code = emit_call_seq (cfg, code);
353 if (dreg != ARMREG_R0)
354 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
356 g_assert_not_reached ();
362 mono_arm_emit_tls_set (MonoCompile *cfg, guint8* code, int sreg, int tls_offset)
365 if (sreg != ARMREG_R1)
366 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
367 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
368 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
370 code = emit_call_seq (cfg, code);
372 g_assert_not_reached ();
378 mono_arm_emit_tls_set_reg (MonoCompile *cfg, guint8* code, int sreg, int tls_offset_reg)
381 /* Get sreg in R1 and tls_offset_reg in R0 */
382 if (tls_offset_reg == ARMREG_R1) {
383 if (sreg == ARMREG_R0) {
384 /* swap sreg and tls_offset_reg */
385 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
386 ARM_EOR_REG_REG (code, tls_offset_reg, sreg, tls_offset_reg);
387 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
389 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
390 if (sreg != ARMREG_R1)
391 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
394 if (sreg != ARMREG_R1)
395 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
396 if (tls_offset_reg != ARMREG_R0)
397 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
399 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
401 code = emit_call_seq (cfg, code);
403 g_assert_not_reached ();
411 * Emit code to push an LMF structure on the LMF stack.
412 * On arm, this is intermixed with the initialization of other fields of the structure.
415 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
417 gboolean get_lmf_fast = FALSE;
420 if (mono_arm_have_tls_get ()) {
422 if (cfg->compile_aot) {
424 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_TLS_OFFSET, (gpointer)TLS_KEY_LMF_ADDR);
425 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
427 *(gpointer*)code = NULL;
429 /* Load the value from the GOT */
430 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_PC, ARMREG_R1);
431 code = mono_arm_emit_tls_get_reg (cfg, code, ARMREG_R0, ARMREG_R1);
433 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
434 g_assert (lmf_addr_tls_offset != -1);
435 code = mono_arm_emit_tls_get (cfg, code, ARMREG_R0, lmf_addr_tls_offset);
440 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
441 (gpointer)"mono_get_lmf_addr");
442 code = emit_call_seq (cfg, code);
444 /* we build the MonoLMF structure on the stack - see mini-arm.h */
445 /* lmf_offset is the offset from the previous stack pointer,
446 * alloc_size is the total stack space allocated, so the offset
447 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
448 * The pointer to the struct is put in r1 (new_lmf).
449 * ip is used as scratch
450 * The callee-saved registers are already in the MonoLMF structure
452 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
453 /* r0 is the result from mono_get_lmf_addr () */
454 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
455 /* new_lmf->previous_lmf = *lmf_addr */
456 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
457 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
458 /* *(lmf_addr) = r1 */
459 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
460 /* Skip method (only needed for trampoline LMF frames) */
461 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
462 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
463 /* save the current IP */
464 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
465 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
467 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
468 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
479 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
483 for (list = inst->float_args; list; list = list->next) {
484 FloatArgData *fad = list->data;
485 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
486 gboolean imm = arm_is_fpimm8 (var->inst_offset);
488 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
494 if (*offset + *max_len > cfg->code_size) {
495 cfg->code_size += *max_len;
496 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
498 code = cfg->native_code + *offset;
502 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
503 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
505 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
507 *offset = code - cfg->native_code;
514 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
518 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
520 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
523 if (!arm_is_fpimm8 (inst->inst_offset)) {
524 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
525 ARM_FSTD (code, reg, ARMREG_LR, 0);
527 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
534 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
538 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
540 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
543 if (!arm_is_fpimm8 (inst->inst_offset)) {
544 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
545 ARM_FLDD (code, reg, ARMREG_LR, 0);
547 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
556 * Emit code to pop an LMF structure from the LMF stack.
559 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
563 if (lmf_offset < 32) {
564 basereg = cfg->frame_reg;
569 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
572 /* ip = previous_lmf */
573 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
575 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
576 /* *(lmf_addr) = previous_lmf */
577 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
582 #endif /* #ifndef DISABLE_JIT */
585 * mono_arm_have_tls_get:
587 * Returns whether we have tls access implemented on the current
591 mono_arm_have_tls_get (void)
601 * mono_arch_get_argument_info:
602 * @csig: a method signature
603 * @param_count: the number of parameters to consider
604 * @arg_info: an array to store the result infos
606 * Gathers information on parameters such as size, alignment and
607 * padding. arg_info should be large enought to hold param_count + 1 entries.
609 * Returns the size of the activation frame.
612 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
614 int k, frame_size = 0;
615 guint32 size, align, pad;
619 t = mini_get_underlying_type (csig->ret);
620 if (MONO_TYPE_ISSTRUCT (t)) {
621 frame_size += sizeof (gpointer);
625 arg_info [0].offset = offset;
628 frame_size += sizeof (gpointer);
632 arg_info [0].size = frame_size;
634 for (k = 0; k < param_count; k++) {
635 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
637 /* ignore alignment for now */
640 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
641 arg_info [k].pad = pad;
643 arg_info [k + 1].pad = 0;
644 arg_info [k + 1].size = size;
646 arg_info [k + 1].offset = offset;
650 align = MONO_ARCH_FRAME_ALIGNMENT;
651 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
652 arg_info [k].pad = pad;
657 #define MAX_ARCH_DELEGATE_PARAMS 3
660 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
662 guint8 *code, *start;
663 GSList *unwind_ops = mono_arch_get_cie_program ();
666 start = code = mono_global_codeman_reserve (12);
668 /* Replace the this argument with the target */
669 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
670 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
671 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
673 g_assert ((code - start) <= 12);
675 mono_arch_flush_icache (start, 12);
679 size = 8 + param_count * 4;
680 start = code = mono_global_codeman_reserve (size);
682 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
683 /* slide down the arguments */
684 for (i = 0; i < param_count; ++i) {
685 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
687 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
689 g_assert ((code - start) <= size);
691 mono_arch_flush_icache (start, size);
695 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
697 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
698 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
702 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
708 * mono_arch_get_delegate_invoke_impls:
710 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
714 mono_arch_get_delegate_invoke_impls (void)
720 get_delegate_invoke_impl (&info, TRUE, 0);
721 res = g_slist_prepend (res, info);
723 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
724 get_delegate_invoke_impl (&info, FALSE, i);
725 res = g_slist_prepend (res, info);
732 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
734 guint8 *code, *start;
737 /* FIXME: Support more cases */
738 sig_ret = mini_get_underlying_type (sig->ret);
739 if (MONO_TYPE_ISSTRUCT (sig_ret))
743 static guint8* cached = NULL;
744 mono_mini_arch_lock ();
746 mono_mini_arch_unlock ();
751 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
754 start = get_delegate_invoke_impl (&info, TRUE, 0);
755 mono_tramp_info_register (info, NULL);
758 mono_mini_arch_unlock ();
761 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
764 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
766 for (i = 0; i < sig->param_count; ++i)
767 if (!mono_is_regsize_var (sig->params [i]))
770 mono_mini_arch_lock ();
771 code = cache [sig->param_count];
773 mono_mini_arch_unlock ();
778 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
779 start = mono_aot_get_trampoline (name);
783 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
784 mono_tramp_info_register (info, NULL);
786 cache [sig->param_count] = start;
787 mono_mini_arch_unlock ();
795 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
801 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
803 return (gpointer)regs [ARMREG_R0];
807 * Initialize the cpu to execute managed code.
810 mono_arch_cpu_init (void)
812 i8_align = MONO_ABI_ALIGNOF (gint64);
813 #ifdef MONO_CROSS_COMPILE
814 /* Need to set the alignment of i8 since it can different on the target */
815 #ifdef TARGET_ANDROID
817 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
823 * Initialize architecture specific code.
826 mono_arch_init (void)
828 const char *cpu_arch;
830 #ifdef TARGET_WATCHOS
831 mini_get_debug_options ()->soft_breakpoints = TRUE;
834 mono_os_mutex_init_recursive (&mini_arch_mutex);
835 if (mini_get_debug_options ()->soft_breakpoints) {
837 breakpoint_tramp = mini_get_breakpoint_trampoline ();
839 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
840 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
841 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
844 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
845 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
846 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
847 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
848 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
850 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
852 #if defined(__ARM_EABI__)
853 eabi_supported = TRUE;
856 #if defined(ARM_FPU_VFP_HARD)
857 arm_fpu = MONO_ARM_FPU_VFP_HARD;
859 arm_fpu = MONO_ARM_FPU_VFP;
861 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
863 * If we're compiling with a soft float fallback and it
864 * turns out that no VFP unit is available, we need to
865 * switch to soft float. We don't do this for iOS, since
866 * iOS devices always have a VFP unit.
868 if (!mono_hwcap_arm_has_vfp)
869 arm_fpu = MONO_ARM_FPU_NONE;
872 * This environment variable can be useful in testing
873 * environments to make sure the soft float fallback
874 * works. Most ARM devices have VFP units these days, so
875 * normally soft float code would not be exercised much.
877 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
879 if (soft && !strncmp (soft, "1", 1))
880 arm_fpu = MONO_ARM_FPU_NONE;
884 v5_supported = mono_hwcap_arm_is_v5;
885 v6_supported = mono_hwcap_arm_is_v6;
886 v7_supported = mono_hwcap_arm_is_v7;
889 * On weird devices, the hwcap code may fail to detect
890 * the ARM version. In that case, we can at least safely
891 * assume the version the runtime was compiled for.
903 #if defined(__APPLE__)
904 /* iOS is special-cased here because we don't yet
905 have a way to properly detect CPU features on it. */
906 thumb_supported = TRUE;
909 thumb_supported = mono_hwcap_arm_has_thumb;
910 thumb2_supported = mono_hwcap_arm_has_thumb2;
913 /* Format: armv(5|6|7[s])[-thumb[2]] */
914 cpu_arch = g_getenv ("MONO_CPU_ARCH");
916 /* Do this here so it overrides any detection. */
918 if (strncmp (cpu_arch, "armv", 4) == 0) {
919 v5_supported = cpu_arch [4] >= '5';
920 v6_supported = cpu_arch [4] >= '6';
921 v7_supported = cpu_arch [4] >= '7';
922 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
923 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
926 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
927 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
932 * Cleanup architecture specific code.
935 mono_arch_cleanup (void)
940 * This function returns the optimizations supported on this cpu.
943 mono_arch_cpu_optimizations (guint32 *exclude_mask)
945 /* no arm-specific optimizations yet */
951 * This function test for all SIMD functions supported.
953 * Returns a bitmask corresponding to all supported versions.
957 mono_arch_cpu_enumerate_simd_versions (void)
959 /* SIMD is currently unimplemented */
964 mono_arm_is_hard_float (void)
966 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
972 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
974 if (v7s_supported || v7k_supported) {
988 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
990 mono_arch_is_soft_float (void)
992 return arm_fpu == MONO_ARM_FPU_NONE;
997 is_regsize_var (MonoType *t)
1001 t = mini_get_underlying_type (t);
1008 case MONO_TYPE_FNPTR:
1010 case MONO_TYPE_OBJECT:
1011 case MONO_TYPE_STRING:
1012 case MONO_TYPE_CLASS:
1013 case MONO_TYPE_SZARRAY:
1014 case MONO_TYPE_ARRAY:
1016 case MONO_TYPE_GENERICINST:
1017 if (!mono_type_generic_inst_is_valuetype (t))
1020 case MONO_TYPE_VALUETYPE:
1027 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1032 for (i = 0; i < cfg->num_varinfo; i++) {
1033 MonoInst *ins = cfg->varinfo [i];
1034 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1037 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1040 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1043 /* we can only allocate 32 bit values */
1044 if (is_regsize_var (ins->inst_vtype)) {
1045 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1046 g_assert (i == vmv->idx);
1047 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1055 mono_arch_get_global_int_regs (MonoCompile *cfg)
1059 mono_arch_compute_omit_fp (cfg);
1062 * FIXME: Interface calls might go through a static rgctx trampoline which
1063 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1066 if (cfg->flags & MONO_CFG_HAS_CALLS)
1067 cfg->uses_rgctx_reg = TRUE;
1069 if (cfg->arch.omit_fp)
1070 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1071 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1072 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1073 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1075 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1076 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1078 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1079 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1080 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1081 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1082 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1083 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1089 * mono_arch_regalloc_cost:
1091 * Return the cost, in number of memory references, of the action of
1092 * allocating the variable VMV into a register during global register
1096 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1102 #endif /* #ifndef DISABLE_JIT */
1105 mono_arch_flush_icache (guint8 *code, gint size)
1107 #if defined(MONO_CROSS_COMPILE)
1109 sys_icache_invalidate (code, size);
1111 __builtin___clear_cache (code, code + size);
1118 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1121 if (*gr > ARMREG_R3) {
1123 ainfo->offset = *stack_size;
1124 ainfo->reg = ARMREG_SP; /* in the caller */
1125 ainfo->storage = RegTypeBase;
1128 ainfo->storage = RegTypeGeneral;
1135 split = i8_align == 4;
1140 if (*gr == ARMREG_R3 && split) {
1141 /* first word in r3 and the second on the stack */
1142 ainfo->offset = *stack_size;
1143 ainfo->reg = ARMREG_SP; /* in the caller */
1144 ainfo->storage = RegTypeBaseGen;
1146 } else if (*gr >= ARMREG_R3) {
1147 if (eabi_supported) {
1148 /* darwin aligns longs to 4 byte only */
1149 if (i8_align == 8) {
1154 ainfo->offset = *stack_size;
1155 ainfo->reg = ARMREG_SP; /* in the caller */
1156 ainfo->storage = RegTypeBase;
1159 if (eabi_supported) {
1160 if (i8_align == 8 && ((*gr) & 1))
1163 ainfo->storage = RegTypeIRegPair;
1172 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1175 * If we're calling a function like this:
1177 * void foo(float a, double b, float c)
1179 * We pass a in s0 and b in d1. That leaves us
1180 * with s1 being unused. The armhf ABI recognizes
1181 * this and requires register assignment to then
1182 * use that for the next single-precision arg,
1183 * i.e. c in this example. So float_spare either
1184 * tells us which reg to use for the next single-
1185 * precision arg, or it's -1, meaning use *fpr.
1187 * Note that even though most of the JIT speaks
1188 * double-precision, fpr represents single-
1189 * precision registers.
1191 * See parts 5.5 and 6.1.2 of the AAPCS for how
1195 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1196 ainfo->storage = RegTypeFP;
1200 * If we're passing a double-precision value
1201 * and *fpr is odd (e.g. it's s1, s3, ...)
1202 * we need to use the next even register. So
1203 * we mark the current *fpr as a spare that
1204 * can be used for the next single-precision
1208 *float_spare = *fpr;
1213 * At this point, we have an even register
1214 * so we assign that and move along.
1218 } else if (*float_spare >= 0) {
1220 * We're passing a single-precision value
1221 * and it looks like a spare single-
1222 * precision register is available. Let's
1226 ainfo->reg = *float_spare;
1230 * If we hit this branch, we're passing a
1231 * single-precision value and we can simply
1232 * use the next available register.
1240 * We've exhausted available floating point
1241 * regs, so pass the rest on the stack.
1249 ainfo->offset = *stack_size;
1250 ainfo->reg = ARMREG_SP;
1251 ainfo->storage = RegTypeBase;
1258 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1262 MonoClassField *field;
1263 MonoType *ftype, *prev_ftype = NULL;
1266 klass = mono_class_from_mono_type (t);
1268 while ((field = mono_class_get_fields (klass, &iter))) {
1269 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1271 ftype = mono_field_get_type (field);
1272 ftype = mini_get_underlying_type (ftype);
1274 if (MONO_TYPE_ISSTRUCT (ftype)) {
1275 int nested_nfields, nested_esize;
1277 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1279 if (nested_esize == 4)
1280 ftype = &mono_defaults.single_class->byval_arg;
1282 ftype = &mono_defaults.double_class->byval_arg;
1283 if (prev_ftype && prev_ftype->type != ftype->type)
1286 nfields += nested_nfields;
1288 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1290 if (prev_ftype && prev_ftype->type != ftype->type)
1296 if (nfields == 0 || nfields > 4)
1298 *out_nfields = nfields;
1299 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1304 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1306 guint i, gr, fpr, pstart;
1308 int n = sig->hasthis + sig->param_count;
1312 guint32 stack_size = 0;
1314 gboolean is_pinvoke = sig->pinvoke;
1315 gboolean vtype_retaddr = FALSE;
1318 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1320 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1327 t = mini_get_underlying_type (sig->ret);
1338 case MONO_TYPE_FNPTR:
1339 case MONO_TYPE_CLASS:
1340 case MONO_TYPE_OBJECT:
1341 case MONO_TYPE_SZARRAY:
1342 case MONO_TYPE_ARRAY:
1343 case MONO_TYPE_STRING:
1344 cinfo->ret.storage = RegTypeGeneral;
1345 cinfo->ret.reg = ARMREG_R0;
1349 cinfo->ret.storage = RegTypeIRegPair;
1350 cinfo->ret.reg = ARMREG_R0;
1354 cinfo->ret.storage = RegTypeFP;
1356 if (t->type == MONO_TYPE_R4)
1357 cinfo->ret.size = 4;
1359 cinfo->ret.size = 8;
1361 if (IS_HARD_FLOAT) {
1362 cinfo->ret.reg = ARM_VFP_F0;
1364 cinfo->ret.reg = ARMREG_R0;
1367 case MONO_TYPE_GENERICINST:
1368 if (!mono_type_generic_inst_is_valuetype (t)) {
1369 cinfo->ret.storage = RegTypeGeneral;
1370 cinfo->ret.reg = ARMREG_R0;
1373 if (mini_is_gsharedvt_variable_type (t)) {
1374 cinfo->ret.storage = RegTypeStructByAddr;
1378 case MONO_TYPE_VALUETYPE:
1379 case MONO_TYPE_TYPEDBYREF:
1380 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1381 cinfo->ret.storage = RegTypeHFA;
1383 cinfo->ret.nregs = nfields;
1384 cinfo->ret.esize = esize;
1387 int native_size = mono_class_native_size (mono_class_from_mono_type (t), &align);
1390 #ifdef TARGET_WATCHOS
1395 if (native_size <= max_size) {
1396 cinfo->ret.storage = RegTypeStructByVal;
1397 cinfo->ret.struct_size = native_size;
1398 cinfo->ret.nregs = ALIGN_TO (native_size, 4) / 4;
1400 cinfo->ret.storage = RegTypeStructByAddr;
1403 cinfo->ret.storage = RegTypeStructByAddr;
1408 case MONO_TYPE_MVAR:
1409 g_assert (mini_is_gsharedvt_type (t));
1410 cinfo->ret.storage = RegTypeStructByAddr;
1412 case MONO_TYPE_VOID:
1415 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1418 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1423 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1424 * the first argument, allowing 'this' to be always passed in the first arg reg.
1425 * Also do this if the first argument is a reference type, since virtual calls
1426 * are sometimes made using calli without sig->hasthis set, like in the delegate
1429 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1431 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1433 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1437 cinfo->ret.reg = gr;
1439 cinfo->vret_arg_index = 1;
1443 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1446 if (vtype_retaddr) {
1447 cinfo->ret.reg = gr;
1452 DEBUG(g_print("params: %d\n", sig->param_count));
1453 for (i = pstart; i < sig->param_count; ++i) {
1454 ArgInfo *ainfo = &cinfo->args [n];
1456 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1457 /* Prevent implicit arguments and sig_cookie from
1458 being passed in registers */
1461 /* Emit the signature cookie just before the implicit arguments */
1462 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1464 DEBUG(g_print("param %d: ", i));
1465 if (sig->params [i]->byref) {
1466 DEBUG(g_print("byref\n"));
1467 add_general (&gr, &stack_size, ainfo, TRUE);
1471 t = mini_get_underlying_type (sig->params [i]);
1475 cinfo->args [n].size = 1;
1476 add_general (&gr, &stack_size, ainfo, TRUE);
1480 cinfo->args [n].size = 2;
1481 add_general (&gr, &stack_size, ainfo, TRUE);
1485 cinfo->args [n].size = 4;
1486 add_general (&gr, &stack_size, ainfo, TRUE);
1491 case MONO_TYPE_FNPTR:
1492 case MONO_TYPE_CLASS:
1493 case MONO_TYPE_OBJECT:
1494 case MONO_TYPE_STRING:
1495 case MONO_TYPE_SZARRAY:
1496 case MONO_TYPE_ARRAY:
1497 cinfo->args [n].size = sizeof (gpointer);
1498 add_general (&gr, &stack_size, ainfo, TRUE);
1500 case MONO_TYPE_GENERICINST:
1501 if (!mono_type_generic_inst_is_valuetype (t)) {
1502 cinfo->args [n].size = sizeof (gpointer);
1503 add_general (&gr, &stack_size, ainfo, TRUE);
1506 if (mini_is_gsharedvt_variable_type (t)) {
1507 /* gsharedvt arguments are passed by ref */
1508 g_assert (mini_is_gsharedvt_type (t));
1509 add_general (&gr, &stack_size, ainfo, TRUE);
1510 switch (ainfo->storage) {
1511 case RegTypeGeneral:
1512 ainfo->storage = RegTypeGSharedVtInReg;
1515 ainfo->storage = RegTypeGSharedVtOnStack;
1518 g_assert_not_reached ();
1523 case MONO_TYPE_TYPEDBYREF:
1524 case MONO_TYPE_VALUETYPE: {
1527 int nwords, nfields, esize;
1530 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1531 if (fpr + nfields < ARM_VFP_F16) {
1532 ainfo->storage = RegTypeHFA;
1534 ainfo->nregs = nfields;
1535 ainfo->esize = esize;
1546 if (t->type == MONO_TYPE_TYPEDBYREF) {
1547 size = sizeof (MonoTypedRef);
1548 align = sizeof (gpointer);
1550 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1552 size = mono_class_native_size (klass, &align);
1554 size = mini_type_stack_size_full (t, &align, FALSE);
1556 DEBUG(g_print ("load %d bytes struct\n", size));
1558 #ifdef TARGET_WATCHOS
1559 /* Watchos pass large structures by ref */
1560 /* We only do this for pinvoke to make gsharedvt/dyncall simpler */
1561 if (sig->pinvoke && size > 16) {
1562 add_general (&gr, &stack_size, ainfo, TRUE);
1563 switch (ainfo->storage) {
1564 case RegTypeGeneral:
1565 ainfo->storage = RegTypeStructByAddr;
1568 ainfo->storage = RegTypeStructByAddrOnStack;
1571 g_assert_not_reached ();
1580 align_size += (sizeof (gpointer) - 1);
1581 align_size &= ~(sizeof (gpointer) - 1);
1582 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1583 ainfo->storage = RegTypeStructByVal;
1584 ainfo->struct_size = size;
1585 /* FIXME: align stack_size if needed */
1586 if (eabi_supported) {
1587 if (align >= 8 && (gr & 1))
1590 if (gr > ARMREG_R3) {
1592 ainfo->vtsize = nwords;
1594 int rest = ARMREG_R3 - gr + 1;
1595 int n_in_regs = rest >= nwords? nwords: rest;
1597 ainfo->size = n_in_regs;
1598 ainfo->vtsize = nwords - n_in_regs;
1601 nwords -= n_in_regs;
1603 if (sig->call_convention == MONO_CALL_VARARG)
1604 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1605 stack_size = ALIGN_TO (stack_size, align);
1606 ainfo->offset = stack_size;
1607 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1608 stack_size += nwords * sizeof (gpointer);
1614 add_general (&gr, &stack_size, ainfo, FALSE);
1620 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1622 add_general (&gr, &stack_size, ainfo, TRUE);
1628 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1630 add_general (&gr, &stack_size, ainfo, FALSE);
1633 case MONO_TYPE_MVAR:
1634 /* gsharedvt arguments are passed by ref */
1635 g_assert (mini_is_gsharedvt_type (t));
1636 add_general (&gr, &stack_size, ainfo, TRUE);
1637 switch (ainfo->storage) {
1638 case RegTypeGeneral:
1639 ainfo->storage = RegTypeGSharedVtInReg;
1642 ainfo->storage = RegTypeGSharedVtOnStack;
1645 g_assert_not_reached ();
1649 g_error ("Can't handle 0x%x", sig->params [i]->type);
1654 /* Handle the case where there are no implicit arguments */
1655 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1656 /* Prevent implicit arguments and sig_cookie from
1657 being passed in registers */
1660 /* Emit the signature cookie just before the implicit arguments */
1661 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1664 /* align stack size to 8 */
1665 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1666 stack_size = (stack_size + 7) & ~7;
1668 cinfo->stack_usage = stack_size;
1674 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1676 MonoType *callee_ret;
1680 c1 = get_call_info (NULL, caller_sig);
1681 c2 = get_call_info (NULL, callee_sig);
1684 * Tail calls with more callee stack usage than the caller cannot be supported, since
1685 * the extra stack space would be left on the stack after the tail call.
1687 res = c1->stack_usage >= c2->stack_usage;
1688 callee_ret = mini_get_underlying_type (callee_sig->ret);
1689 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1690 /* An address on the callee's stack is passed as the first argument */
1693 if (c2->stack_usage > 16 * 4)
1705 debug_omit_fp (void)
1708 return mono_debug_count ();
1715 * mono_arch_compute_omit_fp:
1717 * Determine whenever the frame pointer can be eliminated.
1720 mono_arch_compute_omit_fp (MonoCompile *cfg)
1722 MonoMethodSignature *sig;
1723 MonoMethodHeader *header;
1727 if (cfg->arch.omit_fp_computed)
1730 header = cfg->header;
1732 sig = mono_method_signature (cfg->method);
1734 if (!cfg->arch.cinfo)
1735 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1736 cinfo = cfg->arch.cinfo;
1739 * FIXME: Remove some of the restrictions.
1741 cfg->arch.omit_fp = TRUE;
1742 cfg->arch.omit_fp_computed = TRUE;
1744 if (cfg->disable_omit_fp)
1745 cfg->arch.omit_fp = FALSE;
1746 if (!debug_omit_fp ())
1747 cfg->arch.omit_fp = FALSE;
1749 if (cfg->method->save_lmf)
1750 cfg->arch.omit_fp = FALSE;
1752 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1753 cfg->arch.omit_fp = FALSE;
1754 if (header->num_clauses)
1755 cfg->arch.omit_fp = FALSE;
1756 if (cfg->param_area)
1757 cfg->arch.omit_fp = FALSE;
1758 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1759 cfg->arch.omit_fp = FALSE;
1760 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1761 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1762 cfg->arch.omit_fp = FALSE;
1763 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1764 ArgInfo *ainfo = &cinfo->args [i];
1766 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1768 * The stack offset can only be determined when the frame
1771 cfg->arch.omit_fp = FALSE;
1776 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1777 MonoInst *ins = cfg->varinfo [i];
1780 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1785 * Set var information according to the calling convention. arm version.
1786 * The locals var stuff should most likely be split in another method.
1789 mono_arch_allocate_vars (MonoCompile *cfg)
1791 MonoMethodSignature *sig;
1792 MonoMethodHeader *header;
1795 int i, offset, size, align, curinst;
1800 sig = mono_method_signature (cfg->method);
1802 if (!cfg->arch.cinfo)
1803 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1804 cinfo = cfg->arch.cinfo;
1805 sig_ret = mini_get_underlying_type (sig->ret);
1807 mono_arch_compute_omit_fp (cfg);
1809 if (cfg->arch.omit_fp)
1810 cfg->frame_reg = ARMREG_SP;
1812 cfg->frame_reg = ARMREG_FP;
1814 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1816 /* allow room for the vararg method args: void* and long/double */
1817 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1818 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1820 header = cfg->header;
1822 /* See mono_arch_get_global_int_regs () */
1823 if (cfg->flags & MONO_CFG_HAS_CALLS)
1824 cfg->uses_rgctx_reg = TRUE;
1826 if (cfg->frame_reg != ARMREG_SP)
1827 cfg->used_int_regs |= 1 << cfg->frame_reg;
1829 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1830 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1831 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1835 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1836 if (sig_ret->type != MONO_TYPE_VOID) {
1837 cfg->ret->opcode = OP_REGVAR;
1838 cfg->ret->inst_c0 = ARMREG_R0;
1841 /* local vars are at a positive offset from the stack pointer */
1843 * also note that if the function uses alloca, we use FP
1844 * to point at the local variables.
1846 offset = 0; /* linkage area */
1847 /* align the offset to 16 bytes: not sure this is needed here */
1849 //offset &= ~(8 - 1);
1851 /* add parameter area size for called functions */
1852 offset += cfg->param_area;
1855 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1858 /* allow room to save the return value */
1859 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1862 switch (cinfo->ret.storage) {
1863 case RegTypeStructByVal:
1865 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1866 offset = ALIGN_TO (offset, 8);
1867 cfg->ret->opcode = OP_REGOFFSET;
1868 cfg->ret->inst_basereg = cfg->frame_reg;
1869 cfg->ret->inst_offset = offset;
1870 if (cinfo->ret.storage == RegTypeStructByVal)
1871 offset += cinfo->ret.nregs * sizeof (gpointer);
1875 case RegTypeStructByAddr:
1876 ins = cfg->vret_addr;
1877 offset += sizeof(gpointer) - 1;
1878 offset &= ~(sizeof(gpointer) - 1);
1879 ins->inst_offset = offset;
1880 ins->opcode = OP_REGOFFSET;
1881 ins->inst_basereg = cfg->frame_reg;
1882 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1883 g_print ("vret_addr =");
1884 mono_print_ins (cfg->vret_addr);
1886 offset += sizeof(gpointer);
1892 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1893 if (cfg->arch.seq_point_info_var) {
1896 ins = cfg->arch.seq_point_info_var;
1900 offset += align - 1;
1901 offset &= ~(align - 1);
1902 ins->opcode = OP_REGOFFSET;
1903 ins->inst_basereg = cfg->frame_reg;
1904 ins->inst_offset = offset;
1907 if (cfg->arch.ss_trigger_page_var) {
1910 ins = cfg->arch.ss_trigger_page_var;
1913 offset += align - 1;
1914 offset &= ~(align - 1);
1915 ins->opcode = OP_REGOFFSET;
1916 ins->inst_basereg = cfg->frame_reg;
1917 ins->inst_offset = offset;
1921 if (cfg->arch.seq_point_ss_method_var) {
1924 ins = cfg->arch.seq_point_ss_method_var;
1927 offset += align - 1;
1928 offset &= ~(align - 1);
1929 ins->opcode = OP_REGOFFSET;
1930 ins->inst_basereg = cfg->frame_reg;
1931 ins->inst_offset = offset;
1934 if (cfg->arch.seq_point_bp_method_var) {
1937 ins = cfg->arch.seq_point_bp_method_var;
1940 offset += align - 1;
1941 offset &= ~(align - 1);
1942 ins->opcode = OP_REGOFFSET;
1943 ins->inst_basereg = cfg->frame_reg;
1944 ins->inst_offset = offset;
1948 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
1949 /* Allocate a temporary used by the atomic ops */
1953 /* Allocate a local slot to hold the sig cookie address */
1954 offset += align - 1;
1955 offset &= ~(align - 1);
1956 cfg->arch.atomic_tmp_offset = offset;
1959 cfg->arch.atomic_tmp_offset = -1;
1962 cfg->locals_min_stack_offset = offset;
1964 curinst = cfg->locals_start;
1965 for (i = curinst; i < cfg->num_varinfo; ++i) {
1968 ins = cfg->varinfo [i];
1969 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1972 t = ins->inst_vtype;
1973 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
1976 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1977 * pinvoke wrappers when they call functions returning structure */
1978 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
1979 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
1983 size = mono_type_size (t, &align);
1985 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1986 * since it loads/stores misaligned words, which don't do the right thing.
1988 if (align < 4 && size >= 4)
1990 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1991 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1992 offset += align - 1;
1993 offset &= ~(align - 1);
1994 ins->opcode = OP_REGOFFSET;
1995 ins->inst_offset = offset;
1996 ins->inst_basereg = cfg->frame_reg;
1998 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
2001 cfg->locals_max_stack_offset = offset;
2005 ins = cfg->args [curinst];
2006 if (ins->opcode != OP_REGVAR) {
2007 ins->opcode = OP_REGOFFSET;
2008 ins->inst_basereg = cfg->frame_reg;
2009 offset += sizeof (gpointer) - 1;
2010 offset &= ~(sizeof (gpointer) - 1);
2011 ins->inst_offset = offset;
2012 offset += sizeof (gpointer);
2017 if (sig->call_convention == MONO_CALL_VARARG) {
2021 /* Allocate a local slot to hold the sig cookie address */
2022 offset += align - 1;
2023 offset &= ~(align - 1);
2024 cfg->sig_cookie = offset;
2028 for (i = 0; i < sig->param_count; ++i) {
2029 ainfo = cinfo->args + i;
2031 ins = cfg->args [curinst];
2033 switch (ainfo->storage) {
2035 offset = ALIGN_TO (offset, 8);
2036 ins->opcode = OP_REGOFFSET;
2037 ins->inst_basereg = cfg->frame_reg;
2038 /* These arguments are saved to the stack in the prolog */
2039 ins->inst_offset = offset;
2040 if (cfg->verbose_level >= 2)
2041 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2049 if (ins->opcode != OP_REGVAR) {
2050 ins->opcode = OP_REGOFFSET;
2051 ins->inst_basereg = cfg->frame_reg;
2052 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
2054 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2055 * since it loads/stores misaligned words, which don't do the right thing.
2057 if (align < 4 && size >= 4)
2059 /* The code in the prolog () stores words when storing vtypes received in a register */
2060 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2062 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2063 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2064 offset += align - 1;
2065 offset &= ~(align - 1);
2066 ins->inst_offset = offset;
2072 /* align the offset to 8 bytes */
2073 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2074 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2079 cfg->stack_offset = offset;
2083 mono_arch_create_vars (MonoCompile *cfg)
2085 MonoMethodSignature *sig;
2089 sig = mono_method_signature (cfg->method);
2091 if (!cfg->arch.cinfo)
2092 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2093 cinfo = cfg->arch.cinfo;
2095 if (IS_HARD_FLOAT) {
2096 for (i = 0; i < 2; i++) {
2097 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2098 inst->flags |= MONO_INST_VOLATILE;
2100 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2104 if (cinfo->ret.storage == RegTypeStructByVal)
2105 cfg->ret_var_is_local = TRUE;
2107 if (cinfo->ret.storage == RegTypeStructByAddr) {
2108 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2109 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2110 g_print ("vret_addr = ");
2111 mono_print_ins (cfg->vret_addr);
2115 if (cfg->gen_sdb_seq_points) {
2116 if (cfg->compile_aot) {
2117 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2118 ins->flags |= MONO_INST_VOLATILE;
2119 cfg->arch.seq_point_info_var = ins;
2121 if (!cfg->soft_breakpoints) {
2122 /* Allocate a separate variable for this to save 1 load per seq point */
2123 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2124 ins->flags |= MONO_INST_VOLATILE;
2125 cfg->arch.ss_trigger_page_var = ins;
2128 if (cfg->soft_breakpoints) {
2131 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2132 ins->flags |= MONO_INST_VOLATILE;
2133 cfg->arch.seq_point_ss_method_var = ins;
2135 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2136 ins->flags |= MONO_INST_VOLATILE;
2137 cfg->arch.seq_point_bp_method_var = ins;
2143 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2145 MonoMethodSignature *tmp_sig;
2148 if (call->tail_call)
2151 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2154 * mono_ArgIterator_Setup assumes the signature cookie is
2155 * passed first and all the arguments which were before it are
2156 * passed on the stack after the signature. So compensate by
2157 * passing a different signature.
2159 tmp_sig = mono_metadata_signature_dup (call->signature);
2160 tmp_sig->param_count -= call->signature->sentinelpos;
2161 tmp_sig->sentinelpos = 0;
2162 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2164 sig_reg = mono_alloc_ireg (cfg);
2165 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2167 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2172 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2177 LLVMCallInfo *linfo;
2179 n = sig->param_count + sig->hasthis;
2181 cinfo = get_call_info (cfg->mempool, sig);
2183 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2186 * LLVM always uses the native ABI while we use our own ABI, the
2187 * only difference is the handling of vtypes:
2188 * - we only pass/receive them in registers in some cases, and only
2189 * in 1 or 2 integer registers.
2191 switch (cinfo->ret.storage) {
2192 case RegTypeGeneral:
2195 case RegTypeIRegPair:
2197 case RegTypeStructByAddr:
2198 /* Vtype returned using a hidden argument */
2199 linfo->ret.storage = LLVMArgVtypeRetAddr;
2200 linfo->vret_arg_index = cinfo->vret_arg_index;
2203 case RegTypeStructByVal:
2204 /* LLVM models this by returning an int array */
2205 linfo->ret.storage = LLVMArgAsIArgs;
2206 linfo->ret.nslots = cinfo->ret.nregs;
2210 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2211 cfg->disable_llvm = TRUE;
2215 for (i = 0; i < n; ++i) {
2216 LLVMArgInfo *lainfo = &linfo->args [i];
2217 ainfo = cinfo->args + i;
2219 lainfo->storage = LLVMArgNone;
2221 switch (ainfo->storage) {
2222 case RegTypeGeneral:
2223 case RegTypeIRegPair:
2225 case RegTypeBaseGen:
2227 lainfo->storage = LLVMArgNormal;
2229 case RegTypeStructByVal:
2230 lainfo->storage = LLVMArgAsIArgs;
2231 lainfo->nslots = ainfo->struct_size / sizeof (gpointer);
2233 case RegTypeStructByAddr:
2234 case RegTypeStructByAddrOnStack:
2235 lainfo->storage = LLVMArgVtypeByRef;
2238 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2239 cfg->disable_llvm = TRUE;
2249 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2252 MonoMethodSignature *sig;
2256 sig = call->signature;
2257 n = sig->param_count + sig->hasthis;
2259 cinfo = get_call_info (cfg->mempool, sig);
2261 switch (cinfo->ret.storage) {
2262 case RegTypeStructByVal:
2264 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
2265 /* The JIT will transform this into a normal call */
2266 call->vret_in_reg = TRUE;
2269 if (call->inst.opcode == OP_TAILCALL)
2272 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2273 * the location pointed to by it after call in emit_move_return_value ().
2275 if (!cfg->arch.vret_addr_loc) {
2276 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2277 /* Prevent it from being register allocated or optimized away */
2278 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2281 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2283 case RegTypeStructByAddr: {
2285 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2286 vtarg->sreg1 = call->vret_var->dreg;
2287 vtarg->dreg = mono_alloc_preg (cfg);
2288 MONO_ADD_INS (cfg->cbb, vtarg);
2290 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2297 for (i = 0; i < n; ++i) {
2298 ArgInfo *ainfo = cinfo->args + i;
2301 if (i >= sig->hasthis)
2302 t = sig->params [i - sig->hasthis];
2304 t = &mono_defaults.int_class->byval_arg;
2305 t = mini_get_underlying_type (t);
2307 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2308 /* Emit the signature cookie just before the implicit arguments */
2309 emit_sig_cookie (cfg, call, cinfo);
2312 in = call->args [i];
2314 switch (ainfo->storage) {
2315 case RegTypeGeneral:
2316 case RegTypeIRegPair:
2317 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2318 MONO_INST_NEW (cfg, ins, OP_MOVE);
2319 ins->dreg = mono_alloc_ireg (cfg);
2320 ins->sreg1 = MONO_LVREG_LS (in->dreg);
2321 MONO_ADD_INS (cfg->cbb, ins);
2322 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2324 MONO_INST_NEW (cfg, ins, OP_MOVE);
2325 ins->dreg = mono_alloc_ireg (cfg);
2326 ins->sreg1 = MONO_LVREG_MS (in->dreg);
2327 MONO_ADD_INS (cfg->cbb, ins);
2328 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2329 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2330 if (ainfo->size == 4) {
2331 if (IS_SOFT_FLOAT) {
2332 /* mono_emit_call_args () have already done the r8->r4 conversion */
2333 /* The converted value is in an int vreg */
2334 MONO_INST_NEW (cfg, ins, OP_MOVE);
2335 ins->dreg = mono_alloc_ireg (cfg);
2336 ins->sreg1 = in->dreg;
2337 MONO_ADD_INS (cfg->cbb, ins);
2338 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2342 cfg->param_area = MAX (cfg->param_area, 8);
2343 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2344 creg = mono_alloc_ireg (cfg);
2345 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2346 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2349 if (IS_SOFT_FLOAT) {
2350 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2351 ins->dreg = mono_alloc_ireg (cfg);
2352 ins->sreg1 = in->dreg;
2353 MONO_ADD_INS (cfg->cbb, ins);
2354 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2356 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2357 ins->dreg = mono_alloc_ireg (cfg);
2358 ins->sreg1 = in->dreg;
2359 MONO_ADD_INS (cfg->cbb, ins);
2360 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2364 cfg->param_area = MAX (cfg->param_area, 8);
2365 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2366 creg = mono_alloc_ireg (cfg);
2367 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2368 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2369 creg = mono_alloc_ireg (cfg);
2370 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2371 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2374 cfg->flags |= MONO_CFG_HAS_FPOUT;
2376 MONO_INST_NEW (cfg, ins, OP_MOVE);
2377 ins->dreg = mono_alloc_ireg (cfg);
2378 ins->sreg1 = in->dreg;
2379 MONO_ADD_INS (cfg->cbb, ins);
2381 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2384 case RegTypeStructByVal:
2385 case RegTypeGSharedVtInReg:
2386 case RegTypeGSharedVtOnStack:
2388 case RegTypeStructByAddr:
2389 case RegTypeStructByAddrOnStack:
2390 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2391 ins->opcode = OP_OUTARG_VT;
2392 ins->sreg1 = in->dreg;
2393 ins->klass = in->klass;
2394 ins->inst_p0 = call;
2395 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2396 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2397 mono_call_inst_add_outarg_vt (cfg, call, ins);
2398 MONO_ADD_INS (cfg->cbb, ins);
2401 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2402 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2403 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2404 if (t->type == MONO_TYPE_R8) {
2405 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2408 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2410 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2413 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2416 case RegTypeBaseGen:
2417 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2418 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? MONO_LVREG_LS (in->dreg) : MONO_LVREG_MS (in->dreg));
2419 MONO_INST_NEW (cfg, ins, OP_MOVE);
2420 ins->dreg = mono_alloc_ireg (cfg);
2421 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? MONO_LVREG_MS (in->dreg) : MONO_LVREG_LS (in->dreg);
2422 MONO_ADD_INS (cfg->cbb, ins);
2423 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2424 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2427 /* This should work for soft-float as well */
2429 cfg->param_area = MAX (cfg->param_area, 8);
2430 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2431 creg = mono_alloc_ireg (cfg);
2432 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2433 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2434 creg = mono_alloc_ireg (cfg);
2435 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2436 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2437 cfg->flags |= MONO_CFG_HAS_FPOUT;
2439 g_assert_not_reached ();
2443 int fdreg = mono_alloc_freg (cfg);
2445 if (ainfo->size == 8) {
2446 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2447 ins->sreg1 = in->dreg;
2449 MONO_ADD_INS (cfg->cbb, ins);
2451 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2456 * Mono's register allocator doesn't speak single-precision registers that
2457 * overlap double-precision registers (i.e. armhf). So we have to work around
2458 * the register allocator and load the value from memory manually.
2460 * So we create a variable for the float argument and an instruction to store
2461 * the argument into the variable. We then store the list of these arguments
2462 * in call->float_args. This list is then used by emit_float_args later to
2463 * pass the arguments in the various call opcodes.
2465 * This is not very nice, and we should really try to fix the allocator.
2468 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2470 /* Make sure the instruction isn't seen as pointless and removed.
2472 float_arg->flags |= MONO_INST_VOLATILE;
2474 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2476 /* We use the dreg to look up the instruction later. The hreg is used to
2477 * emit the instruction that loads the value into the FP reg.
2479 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2480 fad->vreg = float_arg->dreg;
2481 fad->hreg = ainfo->reg;
2483 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2486 call->used_iregs |= 1 << ainfo->reg;
2487 cfg->flags |= MONO_CFG_HAS_FPOUT;
2491 g_assert_not_reached ();
2495 /* Handle the case where there are no implicit arguments */
2496 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2497 emit_sig_cookie (cfg, call, cinfo);
2499 call->call_info = cinfo;
2500 call->stack_usage = cinfo->stack_usage;
2504 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2510 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2511 ins->dreg = mono_alloc_freg (cfg);
2512 ins->sreg1 = arg->dreg;
2513 MONO_ADD_INS (cfg->cbb, ins);
2514 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2517 g_assert_not_reached ();
2523 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2525 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2527 ArgInfo *ainfo = ins->inst_p1;
2528 int ovf_size = ainfo->vtsize;
2529 int doffset = ainfo->offset;
2530 int struct_size = ainfo->struct_size;
2531 int i, soffset, dreg, tmpreg;
2533 switch (ainfo->storage) {
2534 case RegTypeGSharedVtInReg:
2535 case RegTypeStructByAddr:
2537 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2539 case RegTypeGSharedVtOnStack:
2540 case RegTypeStructByAddrOnStack:
2541 /* Pass by addr on stack */
2542 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2545 for (i = 0; i < ainfo->nregs; ++i) {
2546 if (ainfo->esize == 4)
2547 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2549 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2550 load->dreg = mono_alloc_freg (cfg);
2551 load->inst_basereg = src->dreg;
2552 load->inst_offset = i * ainfo->esize;
2553 MONO_ADD_INS (cfg->cbb, load);
2555 if (ainfo->esize == 4) {
2558 /* See RegTypeFP in mono_arch_emit_call () */
2559 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2560 float_arg->flags |= MONO_INST_VOLATILE;
2561 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2563 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2564 fad->vreg = float_arg->dreg;
2565 fad->hreg = ainfo->reg + i;
2567 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2569 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2575 for (i = 0; i < ainfo->size; ++i) {
2576 dreg = mono_alloc_ireg (cfg);
2577 switch (struct_size) {
2579 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2582 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2585 tmpreg = mono_alloc_ireg (cfg);
2586 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2587 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2588 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2589 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2590 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2591 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2592 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2595 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2598 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2599 soffset += sizeof (gpointer);
2600 struct_size -= sizeof (gpointer);
2602 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2604 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2610 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2612 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2615 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2618 if (COMPILE_LLVM (cfg)) {
2619 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2621 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2622 ins->sreg1 = MONO_LVREG_LS (val->dreg);
2623 ins->sreg2 = MONO_LVREG_MS (val->dreg);
2624 MONO_ADD_INS (cfg->cbb, ins);
2629 case MONO_ARM_FPU_NONE:
2630 if (ret->type == MONO_TYPE_R8) {
2633 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2634 ins->dreg = cfg->ret->dreg;
2635 ins->sreg1 = val->dreg;
2636 MONO_ADD_INS (cfg->cbb, ins);
2639 if (ret->type == MONO_TYPE_R4) {
2640 /* Already converted to an int in method_to_ir () */
2641 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2645 case MONO_ARM_FPU_VFP:
2646 case MONO_ARM_FPU_VFP_HARD:
2647 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2650 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2651 ins->dreg = cfg->ret->dreg;
2652 ins->sreg1 = val->dreg;
2653 MONO_ADD_INS (cfg->cbb, ins);
2658 g_assert_not_reached ();
2662 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2665 #endif /* #ifndef DISABLE_JIT */
2668 mono_arch_is_inst_imm (gint64 imm)
2674 MonoMethodSignature *sig;
2677 MonoType **param_types;
2681 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2685 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2688 switch (cinfo->ret.storage) {
2690 case RegTypeGeneral:
2691 case RegTypeIRegPair:
2692 case RegTypeStructByAddr:
2703 for (i = 0; i < cinfo->nargs; ++i) {
2704 ArgInfo *ainfo = &cinfo->args [i];
2707 switch (ainfo->storage) {
2708 case RegTypeGeneral:
2709 case RegTypeIRegPair:
2710 case RegTypeBaseGen:
2714 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2717 case RegTypeStructByVal:
2718 if (ainfo->size == 0)
2719 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2721 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2722 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2730 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2731 for (i = 0; i < sig->param_count; ++i) {
2732 MonoType *t = sig->params [i];
2737 t = mini_get_underlying_type (t);
2760 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2762 ArchDynCallInfo *info;
2766 cinfo = get_call_info (NULL, sig);
2768 if (!dyn_call_supported (cinfo, sig)) {
2773 info = g_new0 (ArchDynCallInfo, 1);
2774 // FIXME: Preprocess the info to speed up start_dyn_call ()
2776 info->cinfo = cinfo;
2777 info->rtype = mini_get_underlying_type (sig->ret);
2778 info->param_types = g_new0 (MonoType*, sig->param_count);
2779 for (i = 0; i < sig->param_count; ++i)
2780 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2782 return (MonoDynCallInfo*)info;
2786 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2788 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2790 g_free (ainfo->cinfo);
2795 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2797 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2798 DynCallArgs *p = (DynCallArgs*)buf;
2799 int arg_index, greg, i, j, pindex;
2800 MonoMethodSignature *sig = dinfo->sig;
2802 g_assert (buf_len >= sizeof (DynCallArgs));
2812 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2813 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2818 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2819 p->regs [greg ++] = (mgreg_t)ret;
2821 for (i = pindex; i < sig->param_count; i++) {
2822 MonoType *t = dinfo->param_types [i];
2823 gpointer *arg = args [arg_index ++];
2824 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2827 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2829 } else if (ainfo->storage == RegTypeFP) {
2830 } else if (ainfo->storage == RegTypeBase) {
2831 slot = PARAM_REGS + (ainfo->offset / 4);
2832 } else if (ainfo->storage == RegTypeBaseGen) {
2833 /* slot + 1 is the first stack slot, so the code below will work */
2836 g_assert_not_reached ();
2840 p->regs [slot] = (mgreg_t)*arg;
2845 case MONO_TYPE_STRING:
2846 case MONO_TYPE_CLASS:
2847 case MONO_TYPE_ARRAY:
2848 case MONO_TYPE_SZARRAY:
2849 case MONO_TYPE_OBJECT:
2853 p->regs [slot] = (mgreg_t)*arg;
2856 p->regs [slot] = *(guint8*)arg;
2859 p->regs [slot] = *(gint8*)arg;
2862 p->regs [slot] = *(gint16*)arg;
2865 p->regs [slot] = *(guint16*)arg;
2868 p->regs [slot] = *(gint32*)arg;
2871 p->regs [slot] = *(guint32*)arg;
2875 p->regs [slot ++] = (mgreg_t)arg [0];
2876 p->regs [slot] = (mgreg_t)arg [1];
2879 if (ainfo->storage == RegTypeFP) {
2880 float f = *(float*)arg;
2881 p->fpregs [ainfo->reg / 2] = *(double*)&f;
2884 p->regs [slot] = *(mgreg_t*)arg;
2888 if (ainfo->storage == RegTypeFP) {
2889 p->fpregs [ainfo->reg / 2] = *(double*)arg;
2892 p->regs [slot ++] = (mgreg_t)arg [0];
2893 p->regs [slot] = (mgreg_t)arg [1];
2896 case MONO_TYPE_GENERICINST:
2897 if (MONO_TYPE_IS_REFERENCE (t)) {
2898 p->regs [slot] = (mgreg_t)*arg;
2901 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2902 MonoClass *klass = mono_class_from_mono_type (t);
2903 guint8 *nullable_buf;
2906 size = mono_class_value_size (klass, NULL);
2907 nullable_buf = g_alloca (size);
2908 g_assert (nullable_buf);
2910 /* The argument pointed to by arg is either a boxed vtype or null */
2911 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2913 arg = (gpointer*)nullable_buf;
2919 case MONO_TYPE_VALUETYPE:
2920 g_assert (ainfo->storage == RegTypeStructByVal);
2922 if (ainfo->size == 0)
2923 slot = PARAM_REGS + (ainfo->offset / 4);
2927 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2928 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2931 g_assert_not_reached ();
2937 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2939 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2940 DynCallArgs *p = (DynCallArgs*)buf;
2941 MonoType *ptype = ainfo->rtype;
2942 guint8 *ret = p->ret;
2943 mgreg_t res = p->res;
2944 mgreg_t res2 = p->res2;
2946 switch (ptype->type) {
2947 case MONO_TYPE_VOID:
2948 *(gpointer*)ret = NULL;
2950 case MONO_TYPE_STRING:
2951 case MONO_TYPE_CLASS:
2952 case MONO_TYPE_ARRAY:
2953 case MONO_TYPE_SZARRAY:
2954 case MONO_TYPE_OBJECT:
2958 *(gpointer*)ret = (gpointer)res;
2964 *(guint8*)ret = res;
2967 *(gint16*)ret = res;
2970 *(guint16*)ret = res;
2973 *(gint32*)ret = res;
2976 *(guint32*)ret = res;
2980 /* This handles endianness as well */
2981 ((gint32*)ret) [0] = res;
2982 ((gint32*)ret) [1] = res2;
2984 case MONO_TYPE_GENERICINST:
2985 if (MONO_TYPE_IS_REFERENCE (ptype)) {
2986 *(gpointer*)ret = (gpointer)res;
2991 case MONO_TYPE_VALUETYPE:
2992 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
2998 *(float*)ret = *(float*)&p->fpregs [0];
3000 *(float*)ret = *(float*)&res;
3002 case MONO_TYPE_R8: {
3006 if (IS_HARD_FLOAT) {
3007 *(double*)ret = p->fpregs [0];
3012 *(double*)ret = *(double*)®s;
3017 g_assert_not_reached ();
3024 * Allow tracing to work with this interface (with an optional argument)
3028 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
3032 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3033 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
3034 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
3035 code = emit_call_reg (code, ARMREG_R2);
3049 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3052 int save_mode = SAVE_NONE;
3054 MonoMethod *method = cfg->method;
3055 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
3056 int rtype = ret_type->type;
3057 int save_offset = cfg->param_area;
3061 offset = code - cfg->native_code;
3062 /* we need about 16 instructions */
3063 if (offset > (cfg->code_size - 16 * 4)) {
3064 cfg->code_size *= 2;
3065 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3066 code = cfg->native_code + offset;
3069 case MONO_TYPE_VOID:
3070 /* special case string .ctor icall */
3071 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3072 save_mode = SAVE_ONE;
3074 save_mode = SAVE_NONE;
3078 save_mode = SAVE_TWO;
3082 save_mode = SAVE_ONE_FP;
3084 save_mode = SAVE_ONE;
3088 save_mode = SAVE_TWO_FP;
3090 save_mode = SAVE_TWO;
3092 case MONO_TYPE_GENERICINST:
3093 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3094 save_mode = SAVE_ONE;
3098 case MONO_TYPE_VALUETYPE:
3099 save_mode = SAVE_STRUCT;
3102 save_mode = SAVE_ONE;
3106 switch (save_mode) {
3108 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3109 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3110 if (enable_arguments) {
3111 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3112 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3116 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3117 if (enable_arguments) {
3118 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3122 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3123 if (enable_arguments) {
3124 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3128 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3129 if (enable_arguments) {
3130 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3134 if (enable_arguments) {
3135 /* FIXME: get the actual address */
3136 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3144 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3145 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3146 code = emit_call_reg (code, ARMREG_IP);
3148 switch (save_mode) {
3150 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3151 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3154 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3157 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3160 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3171 * The immediate field for cond branches is big enough for all reasonable methods
3173 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3174 if (0 && ins->inst_true_bb->native_offset) { \
3175 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3177 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3178 ARM_B_COND (code, (condcode), 0); \
3181 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3183 /* emit an exception if condition is fail
3185 * We assign the extra code used to throw the implicit exceptions
3186 * to cfg->bb_exit as far as the big branch handling is concerned
3188 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3190 mono_add_patch_info (cfg, code - cfg->native_code, \
3191 MONO_PATCH_INFO_EXC, exc_name); \
3192 ARM_BL_COND (code, (condcode), 0); \
3195 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3198 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3203 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3207 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3208 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3210 switch (ins->opcode) {
3213 /* Already done by an arch-independent pass */
3215 case OP_LOAD_MEMBASE:
3216 case OP_LOADI4_MEMBASE:
3218 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3219 * OP_LOAD_MEMBASE offset(basereg), reg
3221 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3222 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3223 ins->inst_basereg == last_ins->inst_destbasereg &&
3224 ins->inst_offset == last_ins->inst_offset) {
3225 if (ins->dreg == last_ins->sreg1) {
3226 MONO_DELETE_INS (bb, ins);
3229 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3230 ins->opcode = OP_MOVE;
3231 ins->sreg1 = last_ins->sreg1;
3235 * Note: reg1 must be different from the basereg in the second load
3236 * OP_LOAD_MEMBASE offset(basereg), reg1
3237 * OP_LOAD_MEMBASE offset(basereg), reg2
3239 * OP_LOAD_MEMBASE offset(basereg), reg1
3240 * OP_MOVE reg1, reg2
3242 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3243 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3244 ins->inst_basereg != last_ins->dreg &&
3245 ins->inst_basereg == last_ins->inst_basereg &&
3246 ins->inst_offset == last_ins->inst_offset) {
3248 if (ins->dreg == last_ins->dreg) {
3249 MONO_DELETE_INS (bb, ins);
3252 ins->opcode = OP_MOVE;
3253 ins->sreg1 = last_ins->dreg;
3256 //g_assert_not_reached ();
3260 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3261 * OP_LOAD_MEMBASE offset(basereg), reg
3263 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3264 * OP_ICONST reg, imm
3266 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3267 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3268 ins->inst_basereg == last_ins->inst_destbasereg &&
3269 ins->inst_offset == last_ins->inst_offset) {
3270 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3271 ins->opcode = OP_ICONST;
3272 ins->inst_c0 = last_ins->inst_imm;
3273 g_assert_not_reached (); // check this rule
3277 case OP_LOADU1_MEMBASE:
3278 case OP_LOADI1_MEMBASE:
3279 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3280 ins->inst_basereg == last_ins->inst_destbasereg &&
3281 ins->inst_offset == last_ins->inst_offset) {
3282 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3283 ins->sreg1 = last_ins->sreg1;
3286 case OP_LOADU2_MEMBASE:
3287 case OP_LOADI2_MEMBASE:
3288 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3289 ins->inst_basereg == last_ins->inst_destbasereg &&
3290 ins->inst_offset == last_ins->inst_offset) {
3291 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3292 ins->sreg1 = last_ins->sreg1;
3296 ins->opcode = OP_MOVE;
3300 if (ins->dreg == ins->sreg1) {
3301 MONO_DELETE_INS (bb, ins);
3305 * OP_MOVE sreg, dreg
3306 * OP_MOVE dreg, sreg
3308 if (last_ins && last_ins->opcode == OP_MOVE &&
3309 ins->sreg1 == last_ins->dreg &&
3310 ins->dreg == last_ins->sreg1) {
3311 MONO_DELETE_INS (bb, ins);
3320 * the branch_cc_table should maintain the order of these
3334 branch_cc_table [] = {
3348 #define ADD_NEW_INS(cfg,dest,op) do { \
3349 MONO_INST_NEW ((cfg), (dest), (op)); \
3350 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3354 map_to_reg_reg_op (int op)
3363 case OP_COMPARE_IMM:
3365 case OP_ICOMPARE_IMM:
3379 case OP_LOAD_MEMBASE:
3380 return OP_LOAD_MEMINDEX;
3381 case OP_LOADI4_MEMBASE:
3382 return OP_LOADI4_MEMINDEX;
3383 case OP_LOADU4_MEMBASE:
3384 return OP_LOADU4_MEMINDEX;
3385 case OP_LOADU1_MEMBASE:
3386 return OP_LOADU1_MEMINDEX;
3387 case OP_LOADI2_MEMBASE:
3388 return OP_LOADI2_MEMINDEX;
3389 case OP_LOADU2_MEMBASE:
3390 return OP_LOADU2_MEMINDEX;
3391 case OP_LOADI1_MEMBASE:
3392 return OP_LOADI1_MEMINDEX;
3393 case OP_STOREI1_MEMBASE_REG:
3394 return OP_STOREI1_MEMINDEX;
3395 case OP_STOREI2_MEMBASE_REG:
3396 return OP_STOREI2_MEMINDEX;
3397 case OP_STOREI4_MEMBASE_REG:
3398 return OP_STOREI4_MEMINDEX;
3399 case OP_STORE_MEMBASE_REG:
3400 return OP_STORE_MEMINDEX;
3401 case OP_STORER4_MEMBASE_REG:
3402 return OP_STORER4_MEMINDEX;
3403 case OP_STORER8_MEMBASE_REG:
3404 return OP_STORER8_MEMINDEX;
3405 case OP_STORE_MEMBASE_IMM:
3406 return OP_STORE_MEMBASE_REG;
3407 case OP_STOREI1_MEMBASE_IMM:
3408 return OP_STOREI1_MEMBASE_REG;
3409 case OP_STOREI2_MEMBASE_IMM:
3410 return OP_STOREI2_MEMBASE_REG;
3411 case OP_STOREI4_MEMBASE_IMM:
3412 return OP_STOREI4_MEMBASE_REG;
3414 g_assert_not_reached ();
3418 * Remove from the instruction list the instructions that can't be
3419 * represented with very simple instructions with no register
3423 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3425 MonoInst *ins, *temp, *last_ins = NULL;
3426 int rot_amount, imm8, low_imm;
3428 MONO_BB_FOR_EACH_INS (bb, ins) {
3430 switch (ins->opcode) {
3434 case OP_COMPARE_IMM:
3435 case OP_ICOMPARE_IMM:
3449 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3450 int opcode2 = mono_op_imm_to_op (ins->opcode);
3451 ADD_NEW_INS (cfg, temp, OP_ICONST);
3452 temp->inst_c0 = ins->inst_imm;
3453 temp->dreg = mono_alloc_ireg (cfg);
3454 ins->sreg2 = temp->dreg;
3456 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3457 ins->opcode = opcode2;
3459 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3465 if (ins->inst_imm == 1) {
3466 ins->opcode = OP_MOVE;
3469 if (ins->inst_imm == 0) {
3470 ins->opcode = OP_ICONST;
3474 imm8 = mono_is_power_of_two (ins->inst_imm);
3476 ins->opcode = OP_SHL_IMM;
3477 ins->inst_imm = imm8;
3480 ADD_NEW_INS (cfg, temp, OP_ICONST);
3481 temp->inst_c0 = ins->inst_imm;
3482 temp->dreg = mono_alloc_ireg (cfg);
3483 ins->sreg2 = temp->dreg;
3484 ins->opcode = OP_IMUL;
3490 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3491 /* ARM sets the C flag to 1 if there was _no_ overflow */
3492 ins->next->opcode = OP_COND_EXC_NC;
3495 case OP_IDIV_UN_IMM:
3497 case OP_IREM_UN_IMM: {
3498 int opcode2 = mono_op_imm_to_op (ins->opcode);
3499 ADD_NEW_INS (cfg, temp, OP_ICONST);
3500 temp->inst_c0 = ins->inst_imm;
3501 temp->dreg = mono_alloc_ireg (cfg);
3502 ins->sreg2 = temp->dreg;
3504 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3505 ins->opcode = opcode2;
3508 case OP_LOCALLOC_IMM:
3509 ADD_NEW_INS (cfg, temp, OP_ICONST);
3510 temp->inst_c0 = ins->inst_imm;
3511 temp->dreg = mono_alloc_ireg (cfg);
3512 ins->sreg1 = temp->dreg;
3513 ins->opcode = OP_LOCALLOC;
3515 case OP_LOAD_MEMBASE:
3516 case OP_LOADI4_MEMBASE:
3517 case OP_LOADU4_MEMBASE:
3518 case OP_LOADU1_MEMBASE:
3519 /* we can do two things: load the immed in a register
3520 * and use an indexed load, or see if the immed can be
3521 * represented as an ad_imm + a load with a smaller offset
3522 * that fits. We just do the first for now, optimize later.
3524 if (arm_is_imm12 (ins->inst_offset))
3526 ADD_NEW_INS (cfg, temp, OP_ICONST);
3527 temp->inst_c0 = ins->inst_offset;
3528 temp->dreg = mono_alloc_ireg (cfg);
3529 ins->sreg2 = temp->dreg;
3530 ins->opcode = map_to_reg_reg_op (ins->opcode);
3532 case OP_LOADI2_MEMBASE:
3533 case OP_LOADU2_MEMBASE:
3534 case OP_LOADI1_MEMBASE:
3535 if (arm_is_imm8 (ins->inst_offset))
3537 ADD_NEW_INS (cfg, temp, OP_ICONST);
3538 temp->inst_c0 = ins->inst_offset;
3539 temp->dreg = mono_alloc_ireg (cfg);
3540 ins->sreg2 = temp->dreg;
3541 ins->opcode = map_to_reg_reg_op (ins->opcode);
3543 case OP_LOADR4_MEMBASE:
3544 case OP_LOADR8_MEMBASE:
3545 if (arm_is_fpimm8 (ins->inst_offset))
3547 low_imm = ins->inst_offset & 0x1ff;
3548 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3549 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3550 temp->inst_imm = ins->inst_offset & ~0x1ff;
3551 temp->sreg1 = ins->inst_basereg;
3552 temp->dreg = mono_alloc_ireg (cfg);
3553 ins->inst_basereg = temp->dreg;
3554 ins->inst_offset = low_imm;
3558 ADD_NEW_INS (cfg, temp, OP_ICONST);
3559 temp->inst_c0 = ins->inst_offset;
3560 temp->dreg = mono_alloc_ireg (cfg);
3562 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3563 add_ins->sreg1 = ins->inst_basereg;
3564 add_ins->sreg2 = temp->dreg;
3565 add_ins->dreg = mono_alloc_ireg (cfg);
3567 ins->inst_basereg = add_ins->dreg;
3568 ins->inst_offset = 0;
3571 case OP_STORE_MEMBASE_REG:
3572 case OP_STOREI4_MEMBASE_REG:
3573 case OP_STOREI1_MEMBASE_REG:
3574 if (arm_is_imm12 (ins->inst_offset))
3576 ADD_NEW_INS (cfg, temp, OP_ICONST);
3577 temp->inst_c0 = ins->inst_offset;
3578 temp->dreg = mono_alloc_ireg (cfg);
3579 ins->sreg2 = temp->dreg;
3580 ins->opcode = map_to_reg_reg_op (ins->opcode);
3582 case OP_STOREI2_MEMBASE_REG:
3583 if (arm_is_imm8 (ins->inst_offset))
3585 ADD_NEW_INS (cfg, temp, OP_ICONST);
3586 temp->inst_c0 = ins->inst_offset;
3587 temp->dreg = mono_alloc_ireg (cfg);
3588 ins->sreg2 = temp->dreg;
3589 ins->opcode = map_to_reg_reg_op (ins->opcode);
3591 case OP_STORER4_MEMBASE_REG:
3592 case OP_STORER8_MEMBASE_REG:
3593 if (arm_is_fpimm8 (ins->inst_offset))
3595 low_imm = ins->inst_offset & 0x1ff;
3596 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3597 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3598 temp->inst_imm = ins->inst_offset & ~0x1ff;
3599 temp->sreg1 = ins->inst_destbasereg;
3600 temp->dreg = mono_alloc_ireg (cfg);
3601 ins->inst_destbasereg = temp->dreg;
3602 ins->inst_offset = low_imm;
3606 ADD_NEW_INS (cfg, temp, OP_ICONST);
3607 temp->inst_c0 = ins->inst_offset;
3608 temp->dreg = mono_alloc_ireg (cfg);
3610 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3611 add_ins->sreg1 = ins->inst_destbasereg;
3612 add_ins->sreg2 = temp->dreg;
3613 add_ins->dreg = mono_alloc_ireg (cfg);
3615 ins->inst_destbasereg = add_ins->dreg;
3616 ins->inst_offset = 0;
3619 case OP_STORE_MEMBASE_IMM:
3620 case OP_STOREI1_MEMBASE_IMM:
3621 case OP_STOREI2_MEMBASE_IMM:
3622 case OP_STOREI4_MEMBASE_IMM:
3623 ADD_NEW_INS (cfg, temp, OP_ICONST);
3624 temp->inst_c0 = ins->inst_imm;
3625 temp->dreg = mono_alloc_ireg (cfg);
3626 ins->sreg1 = temp->dreg;
3627 ins->opcode = map_to_reg_reg_op (ins->opcode);
3629 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3632 gboolean swap = FALSE;
3636 /* Optimized away */
3641 /* Some fp compares require swapped operands */
3642 switch (ins->next->opcode) {
3644 ins->next->opcode = OP_FBLT;
3648 ins->next->opcode = OP_FBLT_UN;
3652 ins->next->opcode = OP_FBGE;
3656 ins->next->opcode = OP_FBGE_UN;
3664 ins->sreg1 = ins->sreg2;
3673 bb->last_ins = last_ins;
3674 bb->max_vreg = cfg->next_vreg;
3678 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3682 if (long_ins->opcode == OP_LNEG) {
3684 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), 0);
3685 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
3691 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3693 /* sreg is a float, dreg is an integer reg */
3695 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3697 ARM_TOSIZD (code, vfp_scratch1, sreg);
3699 ARM_TOUIZD (code, vfp_scratch1, sreg);
3700 ARM_FMRS (code, dreg, vfp_scratch1);
3701 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3705 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3706 else if (size == 2) {
3707 ARM_SHL_IMM (code, dreg, dreg, 16);
3708 ARM_SHR_IMM (code, dreg, dreg, 16);
3712 ARM_SHL_IMM (code, dreg, dreg, 24);
3713 ARM_SAR_IMM (code, dreg, dreg, 24);
3714 } else if (size == 2) {
3715 ARM_SHL_IMM (code, dreg, dreg, 16);
3716 ARM_SAR_IMM (code, dreg, dreg, 16);
3723 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3725 /* sreg is a float, dreg is an integer reg */
3727 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3729 ARM_TOSIZS (code, vfp_scratch1, sreg);
3731 ARM_TOUIZS (code, vfp_scratch1, sreg);
3732 ARM_FMRS (code, dreg, vfp_scratch1);
3733 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3737 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3738 else if (size == 2) {
3739 ARM_SHL_IMM (code, dreg, dreg, 16);
3740 ARM_SHR_IMM (code, dreg, dreg, 16);
3744 ARM_SHL_IMM (code, dreg, dreg, 24);
3745 ARM_SAR_IMM (code, dreg, dreg, 24);
3746 } else if (size == 2) {
3747 ARM_SHL_IMM (code, dreg, dreg, 16);
3748 ARM_SAR_IMM (code, dreg, dreg, 16);
3754 #endif /* #ifndef DISABLE_JIT */
3756 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3759 emit_thunk (guint8 *code, gconstpointer target)
3763 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3764 if (thumb_supported)
3765 ARM_BX (code, ARMREG_IP);
3767 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3768 *(guint32*)code = (guint32)target;
3770 mono_arch_flush_icache (p, code - p);
3774 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3776 MonoJitInfo *ji = NULL;
3777 MonoThunkJitInfo *info;
3780 guint8 *orig_target;
3781 guint8 *target_thunk;
3784 domain = mono_domain_get ();
3788 * This can be called multiple times during JITting,
3789 * save the current position in cfg->arch to avoid
3790 * doing a O(n^2) search.
3792 if (!cfg->arch.thunks) {
3793 cfg->arch.thunks = cfg->thunks;
3794 cfg->arch.thunks_size = cfg->thunk_area;
3796 thunks = cfg->arch.thunks;
3797 thunks_size = cfg->arch.thunks_size;
3799 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3800 g_assert_not_reached ();
3803 g_assert (*(guint32*)thunks == 0);
3804 emit_thunk (thunks, target);
3805 arm_patch (code, thunks);
3807 cfg->arch.thunks += THUNK_SIZE;
3808 cfg->arch.thunks_size -= THUNK_SIZE;
3810 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3812 info = mono_jit_info_get_thunk_info (ji);
3815 thunks = (guint8*)ji->code_start + info->thunks_offset;
3816 thunks_size = info->thunks_size;
3818 orig_target = mono_arch_get_call_target (code + 4);
3820 mono_mini_arch_lock ();
3822 target_thunk = NULL;
3823 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3824 /* The call already points to a thunk, because of trampolines etc. */
3825 target_thunk = orig_target;
3827 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3828 if (((guint32*)p) [0] == 0) {
3832 } else if (((guint32*)p) [2] == (guint32)target) {
3833 /* Thunk already points to target */
3840 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3842 if (!target_thunk) {
3843 mono_mini_arch_unlock ();
3844 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3845 g_assert_not_reached ();
3848 emit_thunk (target_thunk, target);
3849 arm_patch (code, target_thunk);
3850 mono_arch_flush_icache (code, 4);
3852 mono_mini_arch_unlock ();
3857 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3859 guint32 *code32 = (void*)code;
3860 guint32 ins = *code32;
3861 guint32 prim = (ins >> 25) & 7;
3862 guint32 tval = GPOINTER_TO_UINT (target);
3864 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3865 if (prim == 5) { /* 101b */
3866 /* the diff starts 8 bytes from the branch opcode */
3867 gint diff = target - code - 8;
3869 gint tmask = 0xffffffff;
3870 if (tval & 1) { /* entering thumb mode */
3871 diff = target - 1 - code - 8;
3872 g_assert (thumb_supported);
3873 tbits = 0xf << 28; /* bl->blx bit pattern */
3874 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3875 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3879 tmask = ~(1 << 24); /* clear the link bit */
3880 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3885 if (diff <= 33554431) {
3887 ins = (ins & 0xff000000) | diff;
3889 *code32 = ins | tbits;
3893 /* diff between 0 and -33554432 */
3894 if (diff >= -33554432) {
3896 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3898 *code32 = ins | tbits;
3903 handle_thunk (cfg, domain, code, target);
3908 * The alternative call sequences looks like this:
3910 * ldr ip, [pc] // loads the address constant
3911 * b 1f // jumps around the constant
3912 * address constant embedded in the code
3917 * There are two cases for patching:
3918 * a) at the end of method emission: in this case code points to the start
3919 * of the call sequence
3920 * b) during runtime patching of the call site: in this case code points
3921 * to the mov pc, ip instruction
3923 * We have to handle also the thunk jump code sequence:
3927 * address constant // execution never reaches here
3929 if ((ins & 0x0ffffff0) == 0x12fff10) {
3930 /* Branch and exchange: the address is constructed in a reg
3931 * We can patch BX when the code sequence is the following:
3932 * ldr ip, [pc, #0] ; 0x8
3939 guint8 *emit = (guint8*)ccode;
3940 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3942 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3943 ARM_BX (emit, ARMREG_IP);
3945 /*patching from magic trampoline*/
3946 if (ins == ccode [3]) {
3947 g_assert (code32 [-4] == ccode [0]);
3948 g_assert (code32 [-3] == ccode [1]);
3949 g_assert (code32 [-1] == ccode [2]);
3950 code32 [-2] = (guint32)target;
3953 /*patching from JIT*/
3954 if (ins == ccode [0]) {
3955 g_assert (code32 [1] == ccode [1]);
3956 g_assert (code32 [3] == ccode [2]);
3957 g_assert (code32 [4] == ccode [3]);
3958 code32 [2] = (guint32)target;
3961 g_assert_not_reached ();
3962 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3970 guint8 *emit = (guint8*)ccode;
3971 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3973 ARM_BLX_REG (emit, ARMREG_IP);
3975 g_assert (code32 [-3] == ccode [0]);
3976 g_assert (code32 [-2] == ccode [1]);
3977 g_assert (code32 [0] == ccode [2]);
3979 code32 [-1] = (guint32)target;
3982 guint32 *tmp = ccode;
3983 guint8 *emit = (guint8*)tmp;
3984 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3985 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3986 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3987 ARM_BX (emit, ARMREG_IP);
3988 if (ins == ccode [2]) {
3989 g_assert_not_reached (); // should be -2 ...
3990 code32 [-1] = (guint32)target;
3993 if (ins == ccode [0]) {
3994 /* handles both thunk jump code and the far call sequence */
3995 code32 [2] = (guint32)target;
3998 g_assert_not_reached ();
4000 // g_print ("patched with 0x%08x\n", ins);
4004 arm_patch (guchar *code, const guchar *target)
4006 arm_patch_general (NULL, NULL, code, target);
4010 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
4011 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
4012 * to be used with the emit macros.
4013 * Return -1 otherwise.
4016 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
4019 for (i = 0; i < 31; i+= 2) {
4020 res = (val << (32 - i)) | (val >> i);
4023 *rot_amount = i? 32 - i: 0;
4030 * Emits in code a sequence of instructions that load the value 'val'
4031 * into the dreg register. Uses at most 4 instructions.
4034 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
4036 int imm8, rot_amount;
4038 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4039 /* skip the constant pool */
4045 if (mini_get_debug_options()->single_imm_size && v7_supported) {
4046 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4047 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4051 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4052 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4053 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4054 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4057 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4059 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4063 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4065 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4067 if (val & 0xFF0000) {
4068 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4070 if (val & 0xFF000000) {
4071 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4073 } else if (val & 0xFF00) {
4074 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4075 if (val & 0xFF0000) {
4076 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4078 if (val & 0xFF000000) {
4079 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4081 } else if (val & 0xFF0000) {
4082 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4083 if (val & 0xFF000000) {
4084 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4087 //g_assert_not_reached ();
4093 mono_arm_thumb_supported (void)
4095 return thumb_supported;
4101 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4106 call = (MonoCallInst*)ins;
4107 cinfo = call->call_info;
4109 switch (cinfo->ret.storage) {
4110 case RegTypeStructByVal:
4112 MonoInst *loc = cfg->arch.vret_addr_loc;
4115 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
4116 /* The JIT treats this as a normal call */
4120 /* Load the destination address */
4121 g_assert (loc && loc->opcode == OP_REGOFFSET);
4123 if (arm_is_imm12 (loc->inst_offset)) {
4124 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4126 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4127 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4130 if (cinfo->ret.storage == RegTypeStructByVal) {
4131 int rsize = cinfo->ret.struct_size;
4133 for (i = 0; i < cinfo->ret.nregs; ++i) {
4134 g_assert (rsize >= 0);
4139 ARM_STRB_IMM (code, i, ARMREG_LR, i * 4);
4142 ARM_STRH_IMM (code, i, ARMREG_LR, i * 4);
4145 ARM_STR_IMM (code, i, ARMREG_LR, i * 4);
4151 for (i = 0; i < cinfo->ret.nregs; ++i) {
4152 if (cinfo->ret.esize == 4)
4153 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4155 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4164 switch (ins->opcode) {
4167 case OP_FCALL_MEMBASE:
4169 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4170 if (sig_ret->type == MONO_TYPE_R4) {
4171 if (IS_HARD_FLOAT) {
4172 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4174 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4175 ARM_CVTS (code, ins->dreg, ins->dreg);
4178 if (IS_HARD_FLOAT) {
4179 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4181 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4188 case OP_RCALL_MEMBASE: {
4193 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4194 g_assert (sig_ret->type == MONO_TYPE_R4);
4195 if (IS_HARD_FLOAT) {
4196 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4198 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4199 ARM_CPYS (code, ins->dreg, ins->dreg);
4211 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4216 guint8 *code = cfg->native_code + cfg->code_len;
4217 MonoInst *last_ins = NULL;
4218 guint last_offset = 0;
4220 int imm8, rot_amount;
4222 /* we don't align basic blocks of loops on arm */
4224 if (cfg->verbose_level > 2)
4225 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4227 cpos = bb->max_offset;
4229 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4230 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4231 //g_assert (!mono_compile_aot);
4234 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4235 /* this is not thread save, but good enough */
4236 /* fixme: howto handle overflows? */
4237 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4240 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4241 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4242 (gpointer)"mono_break");
4243 code = emit_call_seq (cfg, code);
4246 MONO_BB_FOR_EACH_INS (bb, ins) {
4247 offset = code - cfg->native_code;
4249 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4251 if (offset > (cfg->code_size - max_len - 16)) {
4252 cfg->code_size *= 2;
4253 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4254 code = cfg->native_code + offset;
4256 // if (ins->cil_code)
4257 // g_print ("cil code\n");
4258 mono_debug_record_line_number (cfg, ins, offset);
4260 switch (ins->opcode) {
4261 case OP_MEMORY_BARRIER:
4263 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4264 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4268 code = mono_arm_emit_tls_get (cfg, code, ins->dreg, ins->inst_offset);
4270 case OP_TLS_GET_REG:
4271 code = mono_arm_emit_tls_get_reg (cfg, code, ins->dreg, ins->sreg1);
4274 code = mono_arm_emit_tls_set (cfg, code, ins->sreg1, ins->inst_offset);
4276 case OP_TLS_SET_REG:
4277 code = mono_arm_emit_tls_set_reg (cfg, code, ins->sreg1, ins->sreg2);
4279 case OP_ATOMIC_EXCHANGE_I4:
4280 case OP_ATOMIC_CAS_I4:
4281 case OP_ATOMIC_ADD_I4: {
4285 g_assert (v7_supported);
4288 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4290 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4292 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4296 g_assert (cfg->arch.atomic_tmp_offset != -1);
4297 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4299 switch (ins->opcode) {
4300 case OP_ATOMIC_EXCHANGE_I4:
4302 ARM_DMB (code, ARM_DMB_SY);
4303 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4304 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4305 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4307 ARM_B_COND (code, ARMCOND_NE, 0);
4308 arm_patch (buf [1], buf [0]);
4310 case OP_ATOMIC_CAS_I4:
4311 ARM_DMB (code, ARM_DMB_SY);
4313 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4314 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4316 ARM_B_COND (code, ARMCOND_NE, 0);
4317 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4318 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4320 ARM_B_COND (code, ARMCOND_NE, 0);
4321 arm_patch (buf [2], buf [0]);
4322 arm_patch (buf [1], code);
4324 case OP_ATOMIC_ADD_I4:
4326 ARM_DMB (code, ARM_DMB_SY);
4327 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4328 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4329 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4330 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4332 ARM_B_COND (code, ARMCOND_NE, 0);
4333 arm_patch (buf [1], buf [0]);
4336 g_assert_not_reached ();
4339 ARM_DMB (code, ARM_DMB_SY);
4340 if (tmpreg != ins->dreg)
4341 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4342 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4345 case OP_ATOMIC_LOAD_I1:
4346 case OP_ATOMIC_LOAD_U1:
4347 case OP_ATOMIC_LOAD_I2:
4348 case OP_ATOMIC_LOAD_U2:
4349 case OP_ATOMIC_LOAD_I4:
4350 case OP_ATOMIC_LOAD_U4:
4351 case OP_ATOMIC_LOAD_R4:
4352 case OP_ATOMIC_LOAD_R8: {
4353 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4354 ARM_DMB (code, ARM_DMB_SY);
4356 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4358 switch (ins->opcode) {
4359 case OP_ATOMIC_LOAD_I1:
4360 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4362 case OP_ATOMIC_LOAD_U1:
4363 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4365 case OP_ATOMIC_LOAD_I2:
4366 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4368 case OP_ATOMIC_LOAD_U2:
4369 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4371 case OP_ATOMIC_LOAD_I4:
4372 case OP_ATOMIC_LOAD_U4:
4373 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4375 case OP_ATOMIC_LOAD_R4:
4377 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4378 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4380 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4381 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4382 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4383 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4384 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4387 case OP_ATOMIC_LOAD_R8:
4388 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4389 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4393 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4394 ARM_DMB (code, ARM_DMB_SY);
4397 case OP_ATOMIC_STORE_I1:
4398 case OP_ATOMIC_STORE_U1:
4399 case OP_ATOMIC_STORE_I2:
4400 case OP_ATOMIC_STORE_U2:
4401 case OP_ATOMIC_STORE_I4:
4402 case OP_ATOMIC_STORE_U4:
4403 case OP_ATOMIC_STORE_R4:
4404 case OP_ATOMIC_STORE_R8: {
4405 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4406 ARM_DMB (code, ARM_DMB_SY);
4408 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4410 switch (ins->opcode) {
4411 case OP_ATOMIC_STORE_I1:
4412 case OP_ATOMIC_STORE_U1:
4413 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4415 case OP_ATOMIC_STORE_I2:
4416 case OP_ATOMIC_STORE_U2:
4417 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4419 case OP_ATOMIC_STORE_I4:
4420 case OP_ATOMIC_STORE_U4:
4421 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4423 case OP_ATOMIC_STORE_R4:
4425 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4426 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4428 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4429 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4430 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4431 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4432 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4435 case OP_ATOMIC_STORE_R8:
4436 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4437 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4441 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4442 ARM_DMB (code, ARM_DMB_SY);
4446 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4447 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
4450 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4451 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
4453 case OP_STOREI1_MEMBASE_IMM:
4454 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4455 g_assert (arm_is_imm12 (ins->inst_offset));
4456 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4458 case OP_STOREI2_MEMBASE_IMM:
4459 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4460 g_assert (arm_is_imm8 (ins->inst_offset));
4461 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4463 case OP_STORE_MEMBASE_IMM:
4464 case OP_STOREI4_MEMBASE_IMM:
4465 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4466 g_assert (arm_is_imm12 (ins->inst_offset));
4467 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4469 case OP_STOREI1_MEMBASE_REG:
4470 g_assert (arm_is_imm12 (ins->inst_offset));
4471 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4473 case OP_STOREI2_MEMBASE_REG:
4474 g_assert (arm_is_imm8 (ins->inst_offset));
4475 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4477 case OP_STORE_MEMBASE_REG:
4478 case OP_STOREI4_MEMBASE_REG:
4479 /* this case is special, since it happens for spill code after lowering has been called */
4480 if (arm_is_imm12 (ins->inst_offset)) {
4481 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4483 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4484 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4487 case OP_STOREI1_MEMINDEX:
4488 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4490 case OP_STOREI2_MEMINDEX:
4491 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4493 case OP_STORE_MEMINDEX:
4494 case OP_STOREI4_MEMINDEX:
4495 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4498 g_assert_not_reached ();
4500 case OP_LOAD_MEMINDEX:
4501 case OP_LOADI4_MEMINDEX:
4502 case OP_LOADU4_MEMINDEX:
4503 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4505 case OP_LOADI1_MEMINDEX:
4506 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4508 case OP_LOADU1_MEMINDEX:
4509 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4511 case OP_LOADI2_MEMINDEX:
4512 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4514 case OP_LOADU2_MEMINDEX:
4515 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4517 case OP_LOAD_MEMBASE:
4518 case OP_LOADI4_MEMBASE:
4519 case OP_LOADU4_MEMBASE:
4520 /* this case is special, since it happens for spill code after lowering has been called */
4521 if (arm_is_imm12 (ins->inst_offset)) {
4522 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4524 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4525 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4528 case OP_LOADI1_MEMBASE:
4529 g_assert (arm_is_imm8 (ins->inst_offset));
4530 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4532 case OP_LOADU1_MEMBASE:
4533 g_assert (arm_is_imm12 (ins->inst_offset));
4534 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4536 case OP_LOADU2_MEMBASE:
4537 g_assert (arm_is_imm8 (ins->inst_offset));
4538 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4540 case OP_LOADI2_MEMBASE:
4541 g_assert (arm_is_imm8 (ins->inst_offset));
4542 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4544 case OP_ICONV_TO_I1:
4545 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4546 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4548 case OP_ICONV_TO_I2:
4549 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4550 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4552 case OP_ICONV_TO_U1:
4553 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4555 case OP_ICONV_TO_U2:
4556 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4557 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4561 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4563 case OP_COMPARE_IMM:
4564 case OP_ICOMPARE_IMM:
4565 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4566 g_assert (imm8 >= 0);
4567 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4571 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4572 * So instead of emitting a trap, we emit a call a C function and place a
4575 //*(int*)code = 0xef9f0001;
4578 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4579 (gpointer)"mono_break");
4580 code = emit_call_seq (cfg, code);
4582 case OP_RELAXED_NOP:
4587 case OP_DUMMY_STORE:
4588 case OP_DUMMY_ICONST:
4589 case OP_DUMMY_R8CONST:
4590 case OP_NOT_REACHED:
4593 case OP_IL_SEQ_POINT:
4594 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4596 case OP_SEQ_POINT: {
4598 MonoInst *info_var = cfg->arch.seq_point_info_var;
4599 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4600 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4601 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4603 int dreg = ARMREG_LR;
4606 if (cfg->soft_breakpoints) {
4607 g_assert (!cfg->compile_aot);
4612 * For AOT, we use one got slot per method, which will point to a
4613 * SeqPointInfo structure, containing all the information required
4614 * by the code below.
4616 if (cfg->compile_aot) {
4617 g_assert (info_var);
4618 g_assert (info_var->opcode == OP_REGOFFSET);
4619 g_assert (arm_is_imm12 (info_var->inst_offset));
4622 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4624 * Read from the single stepping trigger page. This will cause a
4625 * SIGSEGV when single stepping is enabled.
4626 * We do this _before_ the breakpoint, so single stepping after
4627 * a breakpoint is hit will step to the next IL offset.
4629 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4632 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4633 if (cfg->soft_breakpoints) {
4634 /* Load the address of the sequence point method variable. */
4635 var = ss_method_var;
4637 g_assert (var->opcode == OP_REGOFFSET);
4638 g_assert (arm_is_imm12 (var->inst_offset));
4639 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4641 /* Read the value and check whether it is non-zero. */
4642 ARM_LDR_IMM (code, dreg, dreg, 0);
4643 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4644 /* Call it conditionally. */
4645 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4647 if (cfg->compile_aot) {
4648 /* Load the trigger page addr from the variable initialized in the prolog */
4649 var = ss_trigger_page_var;
4651 g_assert (var->opcode == OP_REGOFFSET);
4652 g_assert (arm_is_imm12 (var->inst_offset));
4653 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4655 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4657 *(int*)code = (int)ss_trigger_page;
4660 ARM_LDR_IMM (code, dreg, dreg, 0);
4664 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4666 if (cfg->compile_aot) {
4667 guint32 offset = code - cfg->native_code;
4670 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4671 /* Add the offset */
4672 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4673 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4674 if (arm_is_imm12 ((int)val)) {
4675 ARM_LDR_IMM (code, dreg, dreg, val);
4677 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4679 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4681 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4682 g_assert (!(val & 0xFF000000));
4684 ARM_LDR_IMM (code, dreg, dreg, 0);
4686 /* What is faster, a branch or a load ? */
4687 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4688 /* The breakpoint instruction */
4689 if (cfg->soft_breakpoints)
4690 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4692 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4693 } else if (cfg->soft_breakpoints) {
4694 /* Load the address of the breakpoint method into ip. */
4695 var = bp_method_var;
4697 g_assert (var->opcode == OP_REGOFFSET);
4698 g_assert (arm_is_imm12 (var->inst_offset));
4699 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4702 * A placeholder for a possible breakpoint inserted by
4703 * mono_arch_set_breakpoint ().
4708 * A placeholder for a possible breakpoint inserted by
4709 * mono_arch_set_breakpoint ().
4711 for (i = 0; i < 4; ++i)
4716 * Add an additional nop so skipping the bp doesn't cause the ip to point
4717 * to another IL offset.
4725 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4728 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4732 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4735 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4736 g_assert (imm8 >= 0);
4737 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4741 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4742 g_assert (imm8 >= 0);
4743 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4747 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4748 g_assert (imm8 >= 0);
4749 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4752 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4753 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4755 case OP_IADD_OVF_UN:
4756 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4757 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4760 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4761 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4763 case OP_ISUB_OVF_UN:
4764 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4765 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4767 case OP_ADD_OVF_CARRY:
4768 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4769 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4771 case OP_ADD_OVF_UN_CARRY:
4772 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4773 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4775 case OP_SUB_OVF_CARRY:
4776 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4777 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4779 case OP_SUB_OVF_UN_CARRY:
4780 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4781 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4785 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4788 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4789 g_assert (imm8 >= 0);
4790 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4793 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4797 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4801 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4802 g_assert (imm8 >= 0);
4803 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4807 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4808 g_assert (imm8 >= 0);
4809 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4811 case OP_ARM_RSBS_IMM:
4812 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4813 g_assert (imm8 >= 0);
4814 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4816 case OP_ARM_RSC_IMM:
4817 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4818 g_assert (imm8 >= 0);
4819 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4822 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4826 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4827 g_assert (imm8 >= 0);
4828 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4831 g_assert (v7s_supported || v7k_supported);
4832 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4835 g_assert (v7s_supported || v7k_supported);
4836 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4839 g_assert (v7s_supported || v7k_supported);
4840 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4841 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4844 g_assert (v7s_supported || v7k_supported);
4845 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4846 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4850 g_assert_not_reached ();
4852 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4856 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4857 g_assert (imm8 >= 0);
4858 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4861 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4865 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4866 g_assert (imm8 >= 0);
4867 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4870 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4875 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4876 else if (ins->dreg != ins->sreg1)
4877 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4880 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4885 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4886 else if (ins->dreg != ins->sreg1)
4887 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4890 case OP_ISHR_UN_IMM:
4892 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4893 else if (ins->dreg != ins->sreg1)
4894 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4897 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4900 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4903 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4906 if (ins->dreg == ins->sreg2)
4907 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4909 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4912 g_assert_not_reached ();
4915 /* FIXME: handle ovf/ sreg2 != dreg */
4916 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4917 /* FIXME: MUL doesn't set the C/O flags on ARM */
4919 case OP_IMUL_OVF_UN:
4920 /* FIXME: handle ovf/ sreg2 != dreg */
4921 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4922 /* FIXME: MUL doesn't set the C/O flags on ARM */
4925 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4928 /* Load the GOT offset */
4929 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4930 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4932 *(gpointer*)code = NULL;
4934 /* Load the value from the GOT */
4935 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4937 case OP_OBJC_GET_SELECTOR:
4938 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4939 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4941 *(gpointer*)code = NULL;
4943 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4945 case OP_ICONV_TO_I4:
4946 case OP_ICONV_TO_U4:
4948 if (ins->dreg != ins->sreg1)
4949 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4952 int saved = ins->sreg2;
4953 if (ins->sreg2 == ARM_LSW_REG) {
4954 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4957 if (ins->sreg1 != ARM_LSW_REG)
4958 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4959 if (saved != ARM_MSW_REG)
4960 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4964 if (IS_VFP && ins->dreg != ins->sreg1)
4965 ARM_CPYD (code, ins->dreg, ins->sreg1);
4968 if (IS_VFP && ins->dreg != ins->sreg1)
4969 ARM_CPYS (code, ins->dreg, ins->sreg1);
4971 case OP_MOVE_F_TO_I4:
4973 ARM_FMRS (code, ins->dreg, ins->sreg1);
4975 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4976 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4977 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4978 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4981 case OP_MOVE_I4_TO_F:
4983 ARM_FMSR (code, ins->dreg, ins->sreg1);
4985 ARM_FMSR (code, ins->dreg, ins->sreg1);
4986 ARM_CVTS (code, ins->dreg, ins->dreg);
4989 case OP_FCONV_TO_R4:
4992 ARM_CVTD (code, ins->dreg, ins->sreg1);
4994 ARM_CVTD (code, ins->dreg, ins->sreg1);
4995 ARM_CVTS (code, ins->dreg, ins->dreg);
5000 MonoCallInst *call = (MonoCallInst*)ins;
5003 * The stack looks like the following:
5004 * <caller argument area>
5007 * <callee argument area>
5008 * Need to copy the arguments from the callee argument area to
5009 * the caller argument area, and pop the frame.
5011 if (call->stack_usage) {
5012 int i, prev_sp_offset = 0;
5014 /* Compute size of saved registers restored below */
5016 prev_sp_offset = 2 * 4;
5018 prev_sp_offset = 1 * 4;
5019 for (i = 0; i < 16; ++i) {
5020 if (cfg->used_int_regs & (1 << i))
5021 prev_sp_offset += 4;
5024 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
5026 /* Copy arguments on the stack to our argument area */
5027 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
5028 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
5029 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
5034 * Keep in sync with mono_arch_emit_epilog
5036 g_assert (!cfg->method->save_lmf);
5038 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
5040 if (cfg->used_int_regs)
5041 ARM_POP (code, cfg->used_int_regs);
5042 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5044 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
5047 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
5048 if (cfg->compile_aot) {
5049 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5051 *(gpointer*)code = NULL;
5053 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5055 code = mono_arm_patchable_b (code, ARMCOND_AL);
5056 cfg->thunk_area += THUNK_SIZE;
5061 /* ensure ins->sreg1 is not NULL */
5062 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5065 g_assert (cfg->sig_cookie < 128);
5066 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5067 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5077 call = (MonoCallInst*)ins;
5080 code = emit_float_args (cfg, call, code, &max_len, &offset);
5082 if (ins->flags & MONO_INST_HAS_METHOD)
5083 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5085 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5086 code = emit_call_seq (cfg, code);
5087 ins->flags |= MONO_INST_GC_CALLSITE;
5088 ins->backend.pc_offset = code - cfg->native_code;
5089 code = emit_move_return_value (cfg, ins, code);
5096 case OP_VOIDCALL_REG:
5099 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5101 code = emit_call_reg (code, ins->sreg1);
5102 ins->flags |= MONO_INST_GC_CALLSITE;
5103 ins->backend.pc_offset = code - cfg->native_code;
5104 code = emit_move_return_value (cfg, ins, code);
5106 case OP_FCALL_MEMBASE:
5107 case OP_RCALL_MEMBASE:
5108 case OP_LCALL_MEMBASE:
5109 case OP_VCALL_MEMBASE:
5110 case OP_VCALL2_MEMBASE:
5111 case OP_VOIDCALL_MEMBASE:
5112 case OP_CALL_MEMBASE: {
5113 g_assert (ins->sreg1 != ARMREG_LR);
5114 call = (MonoCallInst*)ins;
5117 code = emit_float_args (cfg, call, code, &max_len, &offset);
5118 if (!arm_is_imm12 (ins->inst_offset)) {
5119 /* sreg1 might be IP */
5120 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5121 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5122 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_LR);
5123 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5124 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, 0);
5126 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5127 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5129 ins->flags |= MONO_INST_GC_CALLSITE;
5130 ins->backend.pc_offset = code - cfg->native_code;
5131 code = emit_move_return_value (cfg, ins, code);
5134 case OP_GENERIC_CLASS_INIT: {
5135 static int byte_offset = -1;
5136 static guint8 bitmask;
5140 if (byte_offset < 0)
5141 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5143 g_assert (arm_is_imm8 (byte_offset));
5144 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5145 imm8 = mono_arm_is_rotated_imm8 (bitmask, &rot_amount);
5146 g_assert (imm8 >= 0);
5147 ARM_AND_REG_IMM (code, ARMREG_IP, ARMREG_IP, imm8, rot_amount);
5148 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5150 ARM_B_COND (code, ARMCOND_NE, 0);
5152 /* Uninitialized case */
5153 g_assert (ins->sreg1 == ARMREG_R0);
5155 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5156 (gpointer)"mono_generic_class_init");
5157 code = emit_call_seq (cfg, code);
5159 /* Initialized case */
5160 arm_patch (jump, code);
5164 /* round the size to 8 bytes */
5165 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5166 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5167 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5168 /* memzero the area: dreg holds the size, sp is the pointer */
5169 if (ins->flags & MONO_INST_INIT) {
5170 guint8 *start_loop, *branch_to_cond;
5171 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5172 branch_to_cond = code;
5175 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5176 arm_patch (branch_to_cond, code);
5177 /* decrement by 4 and set flags */
5178 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5179 ARM_B_COND (code, ARMCOND_GE, 0);
5180 arm_patch (code - 4, start_loop);
5182 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5183 if (cfg->param_area)
5184 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5189 MonoInst *var = cfg->dyn_call_var;
5192 g_assert (var->opcode == OP_REGOFFSET);
5193 g_assert (arm_is_imm12 (var->inst_offset));
5195 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5196 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5198 ARM_MOV_REG_REG (code, ARMREG_IP, ins->sreg2);
5200 /* Save args buffer */
5201 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5203 /* Set stack slots using R0 as scratch reg */
5204 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5205 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5206 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5207 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5210 /* Set fp argument registers */
5211 if (IS_HARD_FLOAT) {
5212 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, has_fpregs));
5213 ARM_CMP_REG_IMM (code, ARMREG_R0, 0, 0);
5215 ARM_B_COND (code, ARMCOND_EQ, 0);
5216 for (i = 0; i < FP_PARAM_REGS; ++i) {
5217 int offset = MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * sizeof (double));
5218 g_assert (arm_is_fpimm8 (offset));
5219 ARM_FLDD (code, i * 2, ARMREG_LR, offset);
5221 arm_patch (buf [0], code);
5224 /* Set argument registers */
5225 for (i = 0; i < PARAM_REGS; ++i)
5226 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5229 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5230 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5233 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5234 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5235 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5237 ARM_FSTD (code, ARM_VFP_D0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, fpregs));
5241 if (ins->sreg1 != ARMREG_R0)
5242 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5243 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5244 (gpointer)"mono_arch_throw_exception");
5245 code = emit_call_seq (cfg, code);
5249 if (ins->sreg1 != ARMREG_R0)
5250 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5251 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5252 (gpointer)"mono_arch_rethrow_exception");
5253 code = emit_call_seq (cfg, code);
5256 case OP_START_HANDLER: {
5257 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5258 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5261 /* Reserve a param area, see filter-stack.exe */
5263 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5264 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5266 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5267 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5271 if (arm_is_imm12 (spvar->inst_offset)) {
5272 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5274 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5275 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5279 case OP_ENDFILTER: {
5280 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5281 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5284 /* Free the param area */
5286 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5287 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5289 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5290 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5294 if (ins->sreg1 != ARMREG_R0)
5295 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5296 if (arm_is_imm12 (spvar->inst_offset)) {
5297 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5299 g_assert (ARMREG_IP != spvar->inst_basereg);
5300 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5301 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5303 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5306 case OP_ENDFINALLY: {
5307 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5308 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5311 /* Free the param area */
5313 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5314 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5316 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5317 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5321 if (arm_is_imm12 (spvar->inst_offset)) {
5322 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5324 g_assert (ARMREG_IP != spvar->inst_basereg);
5325 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5326 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5328 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5331 case OP_CALL_HANDLER:
5332 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5333 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5334 cfg->thunk_area += THUNK_SIZE;
5335 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5338 if (ins->dreg != ARMREG_R0)
5339 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5343 ins->inst_c0 = code - cfg->native_code;
5346 /*if (ins->inst_target_bb->native_offset) {
5348 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5350 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5351 code = mono_arm_patchable_b (code, ARMCOND_AL);
5355 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5359 * In the normal case we have:
5360 * ldr pc, [pc, ins->sreg1 << 2]
5363 * ldr lr, [pc, ins->sreg1 << 2]
5365 * After follows the data.
5366 * FIXME: add aot support.
5368 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5369 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5370 if (offset + max_len > (cfg->code_size - 16)) {
5371 cfg->code_size += max_len;
5372 cfg->code_size *= 2;
5373 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5374 code = cfg->native_code + offset;
5376 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5378 code += 4 * GPOINTER_TO_INT (ins->klass);
5382 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5383 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5387 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5388 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5392 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5393 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5397 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5398 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5402 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5403 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5406 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5407 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5410 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5411 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5414 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5415 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5418 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5419 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5422 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5423 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5425 case OP_COND_EXC_EQ:
5426 case OP_COND_EXC_NE_UN:
5427 case OP_COND_EXC_LT:
5428 case OP_COND_EXC_LT_UN:
5429 case OP_COND_EXC_GT:
5430 case OP_COND_EXC_GT_UN:
5431 case OP_COND_EXC_GE:
5432 case OP_COND_EXC_GE_UN:
5433 case OP_COND_EXC_LE:
5434 case OP_COND_EXC_LE_UN:
5435 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5437 case OP_COND_EXC_IEQ:
5438 case OP_COND_EXC_INE_UN:
5439 case OP_COND_EXC_ILT:
5440 case OP_COND_EXC_ILT_UN:
5441 case OP_COND_EXC_IGT:
5442 case OP_COND_EXC_IGT_UN:
5443 case OP_COND_EXC_IGE:
5444 case OP_COND_EXC_IGE_UN:
5445 case OP_COND_EXC_ILE:
5446 case OP_COND_EXC_ILE_UN:
5447 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5450 case OP_COND_EXC_IC:
5451 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5453 case OP_COND_EXC_OV:
5454 case OP_COND_EXC_IOV:
5455 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5457 case OP_COND_EXC_NC:
5458 case OP_COND_EXC_INC:
5459 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5461 case OP_COND_EXC_NO:
5462 case OP_COND_EXC_INO:
5463 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5475 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5478 /* floating point opcodes */
5480 if (cfg->compile_aot) {
5481 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5483 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5485 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5488 /* FIXME: we can optimize the imm load by dealing with part of
5489 * the displacement in LDFD (aligning to 512).
5491 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5492 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5496 if (cfg->compile_aot) {
5497 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5499 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5502 ARM_CVTS (code, ins->dreg, ins->dreg);
5504 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5505 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5507 ARM_CVTS (code, ins->dreg, ins->dreg);
5510 case OP_STORER8_MEMBASE_REG:
5511 /* This is generated by the local regalloc pass which runs after the lowering pass */
5512 if (!arm_is_fpimm8 (ins->inst_offset)) {
5513 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5514 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5515 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5517 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5520 case OP_LOADR8_MEMBASE:
5521 /* This is generated by the local regalloc pass which runs after the lowering pass */
5522 if (!arm_is_fpimm8 (ins->inst_offset)) {
5523 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5524 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5525 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5527 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5530 case OP_STORER4_MEMBASE_REG:
5531 g_assert (arm_is_fpimm8 (ins->inst_offset));
5533 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5535 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5536 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5537 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5538 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5541 case OP_LOADR4_MEMBASE:
5543 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5545 g_assert (arm_is_fpimm8 (ins->inst_offset));
5546 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5547 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5548 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5549 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5552 case OP_ICONV_TO_R_UN: {
5553 g_assert_not_reached ();
5556 case OP_ICONV_TO_R4:
5558 ARM_FMSR (code, ins->dreg, ins->sreg1);
5559 ARM_FSITOS (code, ins->dreg, ins->dreg);
5561 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5562 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5563 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5564 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5565 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5568 case OP_ICONV_TO_R8:
5569 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5570 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5571 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5572 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5576 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5577 if (sig_ret->type == MONO_TYPE_R4) {
5579 if (IS_HARD_FLOAT) {
5580 if (ins->sreg1 != ARM_VFP_D0)
5581 ARM_CPYS (code, ARM_VFP_D0, ins->sreg1);
5583 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5586 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5589 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5593 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5595 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5599 case OP_FCONV_TO_I1:
5600 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5602 case OP_FCONV_TO_U1:
5603 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5605 case OP_FCONV_TO_I2:
5606 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5608 case OP_FCONV_TO_U2:
5609 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5611 case OP_FCONV_TO_I4:
5613 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5615 case OP_FCONV_TO_U4:
5617 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5619 case OP_FCONV_TO_I8:
5620 case OP_FCONV_TO_U8:
5621 g_assert_not_reached ();
5622 /* Implemented as helper calls */
5624 case OP_LCONV_TO_R_UN:
5625 g_assert_not_reached ();
5626 /* Implemented as helper calls */
5628 case OP_LCONV_TO_OVF_I4_2: {
5629 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5631 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5634 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5635 high_bit_not_set = code;
5636 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5638 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5639 valid_negative = code;
5640 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5641 invalid_negative = code;
5642 ARM_B_COND (code, ARMCOND_AL, 0);
5644 arm_patch (high_bit_not_set, code);
5646 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5647 valid_positive = code;
5648 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5650 arm_patch (invalid_negative, code);
5651 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5653 arm_patch (valid_negative, code);
5654 arm_patch (valid_positive, code);
5656 if (ins->dreg != ins->sreg1)
5657 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5661 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5664 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5667 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5670 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5673 ARM_NEGD (code, ins->dreg, ins->sreg1);
5677 g_assert_not_reached ();
5681 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5687 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5692 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5695 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5696 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5700 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5703 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5704 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5708 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5711 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5712 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5713 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5717 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5720 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5721 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5725 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5728 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5729 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5730 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5734 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5737 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5738 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5742 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5745 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5746 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5750 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5753 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5754 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5757 /* ARM FPA flags table:
5758 * N Less than ARMCOND_MI
5759 * Z Equal ARMCOND_EQ
5760 * C Greater Than or Equal ARMCOND_CS
5761 * V Unordered ARMCOND_VS
5764 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5767 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5770 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5773 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5774 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5780 g_assert_not_reached ();
5784 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5786 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5787 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5788 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5792 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5793 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5798 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5799 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5801 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5802 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5804 *(guint32*)code = 0xffffffff;
5806 *(guint32*)code = 0x7fefffff;
5808 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5810 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "OverflowException");
5811 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5813 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "OverflowException");
5814 ARM_CPYD (code, ins->dreg, ins->sreg1);
5816 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5817 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5822 case OP_RCONV_TO_I1:
5823 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5825 case OP_RCONV_TO_U1:
5826 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5828 case OP_RCONV_TO_I2:
5829 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5831 case OP_RCONV_TO_U2:
5832 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5834 case OP_RCONV_TO_I4:
5835 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5837 case OP_RCONV_TO_U4:
5838 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5840 case OP_RCONV_TO_R4:
5842 if (ins->dreg != ins->sreg1)
5843 ARM_CPYS (code, ins->dreg, ins->sreg1);
5845 case OP_RCONV_TO_R8:
5847 ARM_CVTS (code, ins->dreg, ins->sreg1);
5850 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5853 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5856 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5859 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5862 ARM_NEGS (code, ins->dreg, ins->sreg1);
5866 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5869 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5870 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5874 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5877 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5878 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5882 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5885 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5886 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5887 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5891 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5894 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5895 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5899 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5902 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5903 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5904 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5908 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5911 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5912 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5916 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5919 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5920 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5924 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5927 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5928 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5931 case OP_GC_LIVENESS_DEF:
5932 case OP_GC_LIVENESS_USE:
5933 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5934 ins->backend.pc_offset = code - cfg->native_code;
5936 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5937 ins->backend.pc_offset = code - cfg->native_code;
5938 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5940 case OP_GC_SAFE_POINT: {
5943 g_assert (mono_threads_is_coop_enabled ());
5945 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5946 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5948 ARM_B_COND (code, ARMCOND_EQ, 0);
5949 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
5950 code = emit_call_seq (cfg, code);
5951 arm_patch (buf [0], code);
5956 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5957 g_assert_not_reached ();
5960 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5961 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5962 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5963 g_assert_not_reached ();
5969 last_offset = offset;
5972 cfg->code_len = code - cfg->native_code;
5975 #endif /* DISABLE_JIT */
5978 mono_arch_register_lowlevel_calls (void)
5980 /* The signature doesn't matter */
5981 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5982 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5983 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
5985 #ifndef MONO_CROSS_COMPILE
5986 if (mono_arm_have_tls_get ()) {
5987 MonoTlsImplementation tls_imp = mono_arm_get_tls_implementation ();
5989 mono_register_jit_icall (tls_imp.get_tls_thunk, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
5990 mono_register_jit_icall (tls_imp.set_tls_thunk, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
5992 if (tls_imp.get_tls_thunk_end) {
5993 mono_tramp_info_register (
5994 mono_tramp_info_create (
5996 (guint8*)tls_imp.get_tls_thunk,
5997 (guint8*)tls_imp.get_tls_thunk_end - (guint8*)tls_imp.get_tls_thunk,
5999 mono_arch_get_cie_program ()
6003 mono_tramp_info_register (
6004 mono_tramp_info_create (
6006 (guint8*)tls_imp.set_tls_thunk,
6007 (guint8*)tls_imp.set_tls_thunk_end - (guint8*)tls_imp.set_tls_thunk,
6009 mono_arch_get_cie_program ()
6018 #define patch_lis_ori(ip,val) do {\
6019 guint16 *__lis_ori = (guint16*)(ip); \
6020 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
6021 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
6025 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6027 unsigned char *ip = ji->ip.i + code;
6029 if (ji->type == MONO_PATCH_INFO_SWITCH) {
6033 case MONO_PATCH_INFO_SWITCH: {
6034 gpointer *jt = (gpointer*)(ip + 8);
6036 /* jt is the inlined jump table, 2 instructions after ip
6037 * In the normal case we store the absolute addresses,
6038 * otherwise the displacements.
6040 for (i = 0; i < ji->data.table->table_size; i++)
6041 jt [i] = code + (int)ji->data.table->table [i];
6044 case MONO_PATCH_INFO_IP:
6045 g_assert_not_reached ();
6046 patch_lis_ori (ip, ip);
6048 case MONO_PATCH_INFO_METHOD_REL:
6049 g_assert_not_reached ();
6050 *((gpointer *)(ip)) = target;
6052 case MONO_PATCH_INFO_METHODCONST:
6053 case MONO_PATCH_INFO_CLASS:
6054 case MONO_PATCH_INFO_IMAGE:
6055 case MONO_PATCH_INFO_FIELD:
6056 case MONO_PATCH_INFO_VTABLE:
6057 case MONO_PATCH_INFO_IID:
6058 case MONO_PATCH_INFO_SFLDA:
6059 case MONO_PATCH_INFO_LDSTR:
6060 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
6061 case MONO_PATCH_INFO_LDTOKEN:
6062 g_assert_not_reached ();
6063 /* from OP_AOTCONST : lis + ori */
6064 patch_lis_ori (ip, target);
6066 case MONO_PATCH_INFO_R4:
6067 case MONO_PATCH_INFO_R8:
6068 g_assert_not_reached ();
6069 *((gconstpointer *)(ip + 2)) = target;
6071 case MONO_PATCH_INFO_EXC_NAME:
6072 g_assert_not_reached ();
6073 *((gconstpointer *)(ip + 1)) = target;
6075 case MONO_PATCH_INFO_NONE:
6076 case MONO_PATCH_INFO_BB_OVF:
6077 case MONO_PATCH_INFO_EXC_OVF:
6078 /* everything is dealt with at epilog output time */
6081 arm_patch_general (cfg, domain, ip, target);
6087 mono_arm_unaligned_stack (MonoMethod *method)
6089 g_assert_not_reached ();
6095 * Stack frame layout:
6097 * ------------------- fp
6098 * MonoLMF structure or saved registers
6099 * -------------------
6101 * -------------------
6103 * -------------------
6104 * optional 8 bytes for tracing
6105 * -------------------
6106 * param area size is cfg->param_area
6107 * ------------------- sp
6110 mono_arch_emit_prolog (MonoCompile *cfg)
6112 MonoMethod *method = cfg->method;
6114 MonoMethodSignature *sig;
6116 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6121 int prev_sp_offset, reg_offset;
6123 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6126 sig = mono_method_signature (method);
6127 cfg->code_size = 256 + sig->param_count * 64;
6128 code = cfg->native_code = g_malloc (cfg->code_size);
6130 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6132 alloc_size = cfg->stack_offset;
6138 * The iphone uses R7 as the frame pointer, and it points at the saved
6143 * We can't use r7 as a frame pointer since it points into the middle of
6144 * the frame, so we keep using our own frame pointer.
6145 * FIXME: Optimize this.
6147 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6148 prev_sp_offset += 8; /* r7 and lr */
6149 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6150 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6151 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6154 if (!method->save_lmf) {
6156 /* No need to push LR again */
6157 if (cfg->used_int_regs)
6158 ARM_PUSH (code, cfg->used_int_regs);
6160 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6161 prev_sp_offset += 4;
6163 for (i = 0; i < 16; ++i) {
6164 if (cfg->used_int_regs & (1 << i))
6165 prev_sp_offset += 4;
6167 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6169 for (i = 0; i < 16; ++i) {
6170 if ((cfg->used_int_regs & (1 << i))) {
6171 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6172 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6176 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6177 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6179 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6180 ARM_PUSH (code, 0x5ff0);
6181 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6182 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6184 for (i = 0; i < 16; ++i) {
6185 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6186 /* The original r7 is saved at the start */
6187 if (!(iphone_abi && i == ARMREG_R7))
6188 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6192 g_assert (reg_offset == 4 * 10);
6193 pos += sizeof (MonoLMF) - (4 * 10);
6197 orig_alloc_size = alloc_size;
6198 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6199 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6200 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6201 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6204 /* the stack used in the pushed regs */
6205 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6206 cfg->stack_usage = alloc_size;
6208 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6209 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6211 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6212 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6214 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6216 if (cfg->frame_reg != ARMREG_SP) {
6217 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6218 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6220 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6221 prev_sp_offset += alloc_size;
6223 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6224 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6226 /* compute max_offset in order to use short forward jumps
6227 * we could skip do it on arm because the immediate displacement
6228 * for jumps is large enough, it may be useful later for constant pools
6231 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6232 MonoInst *ins = bb->code;
6233 bb->max_offset = max_offset;
6235 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6238 MONO_BB_FOR_EACH_INS (bb, ins)
6239 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6242 /* stack alignment check */
6246 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6247 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6248 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6249 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6251 ARM_B_COND (code, ARMCOND_EQ, 0);
6252 if (cfg->compile_aot)
6253 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6255 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6256 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6257 code = emit_call_seq (cfg, code);
6258 arm_patch (buf [0], code);
6262 /* store runtime generic context */
6263 if (cfg->rgctx_var) {
6264 MonoInst *ins = cfg->rgctx_var;
6266 g_assert (ins->opcode == OP_REGOFFSET);
6268 if (arm_is_imm12 (ins->inst_offset)) {
6269 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6271 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6272 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6276 /* load arguments allocated to register from the stack */
6279 cinfo = get_call_info (NULL, sig);
6281 if (cinfo->ret.storage == RegTypeStructByAddr) {
6282 ArgInfo *ainfo = &cinfo->ret;
6283 inst = cfg->vret_addr;
6284 g_assert (arm_is_imm12 (inst->inst_offset));
6285 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6288 if (sig->call_convention == MONO_CALL_VARARG) {
6289 ArgInfo *cookie = &cinfo->sig_cookie;
6291 /* Save the sig cookie address */
6292 g_assert (cookie->storage == RegTypeBase);
6294 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6295 g_assert (arm_is_imm12 (cfg->sig_cookie));
6296 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6297 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6300 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6301 ArgInfo *ainfo = cinfo->args + i;
6302 inst = cfg->args [pos];
6304 if (cfg->verbose_level > 2)
6305 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6307 if (inst->opcode == OP_REGVAR) {
6308 if (ainfo->storage == RegTypeGeneral)
6309 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6310 else if (ainfo->storage == RegTypeFP) {
6311 g_assert_not_reached ();
6312 } else if (ainfo->storage == RegTypeBase) {
6313 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6314 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6316 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6317 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6320 g_assert_not_reached ();
6322 if (cfg->verbose_level > 2)
6323 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6325 switch (ainfo->storage) {
6327 for (part = 0; part < ainfo->nregs; part ++) {
6328 if (ainfo->esize == 4)
6329 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6331 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6334 case RegTypeGeneral:
6335 case RegTypeIRegPair:
6336 case RegTypeGSharedVtInReg:
6337 case RegTypeStructByAddr:
6338 switch (ainfo->size) {
6340 if (arm_is_imm12 (inst->inst_offset))
6341 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6343 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6344 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6348 if (arm_is_imm8 (inst->inst_offset)) {
6349 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6351 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6352 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6356 if (arm_is_imm12 (inst->inst_offset)) {
6357 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6359 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6360 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6362 if (arm_is_imm12 (inst->inst_offset + 4)) {
6363 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6365 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6366 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6370 if (arm_is_imm12 (inst->inst_offset)) {
6371 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6373 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6374 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6379 case RegTypeBaseGen:
6380 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6381 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6383 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6384 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6386 if (arm_is_imm12 (inst->inst_offset + 4)) {
6387 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6388 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6390 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6391 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6392 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6393 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6397 case RegTypeGSharedVtOnStack:
6398 case RegTypeStructByAddrOnStack:
6399 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6400 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6402 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6403 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6406 switch (ainfo->size) {
6408 if (arm_is_imm8 (inst->inst_offset)) {
6409 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6411 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6412 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6416 if (arm_is_imm8 (inst->inst_offset)) {
6417 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6419 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6420 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6424 if (arm_is_imm12 (inst->inst_offset)) {
6425 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6427 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6428 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6430 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6431 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6433 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6434 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6436 if (arm_is_imm12 (inst->inst_offset + 4)) {
6437 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6439 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6440 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6444 if (arm_is_imm12 (inst->inst_offset)) {
6445 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6447 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6448 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6454 int imm8, rot_amount;
6456 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6457 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6458 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6460 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6462 if (ainfo->size == 8)
6463 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6465 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6468 case RegTypeStructByVal: {
6469 int doffset = inst->inst_offset;
6473 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6474 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6475 if (arm_is_imm12 (doffset)) {
6476 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6478 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6479 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6481 soffset += sizeof (gpointer);
6482 doffset += sizeof (gpointer);
6484 if (ainfo->vtsize) {
6485 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6486 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6487 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6492 g_assert_not_reached ();
6499 if (method->save_lmf)
6500 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6503 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6505 if (cfg->arch.seq_point_info_var) {
6506 MonoInst *ins = cfg->arch.seq_point_info_var;
6508 /* Initialize the variable from a GOT slot */
6509 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6510 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6512 *(gpointer*)code = NULL;
6514 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6516 g_assert (ins->opcode == OP_REGOFFSET);
6518 if (arm_is_imm12 (ins->inst_offset)) {
6519 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6521 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6522 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6526 /* Initialize ss_trigger_page_var */
6527 if (!cfg->soft_breakpoints) {
6528 MonoInst *info_var = cfg->arch.seq_point_info_var;
6529 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6530 int dreg = ARMREG_LR;
6533 g_assert (info_var->opcode == OP_REGOFFSET);
6534 g_assert (arm_is_imm12 (info_var->inst_offset));
6536 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6537 /* Load the trigger page addr */
6538 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6539 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6543 if (cfg->arch.seq_point_ss_method_var) {
6544 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6545 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6546 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6547 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6548 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6549 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6551 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6553 *(gpointer*)code = &single_step_tramp;
6555 *(gpointer*)code = breakpoint_tramp;
6558 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6559 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6560 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6561 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6564 cfg->code_len = code - cfg->native_code;
6565 g_assert (cfg->code_len < cfg->code_size);
6572 mono_arch_emit_epilog (MonoCompile *cfg)
6574 MonoMethod *method = cfg->method;
6575 int pos, i, rot_amount;
6576 int max_epilog_size = 16 + 20*4;
6580 if (cfg->method->save_lmf)
6581 max_epilog_size += 128;
6583 if (mono_jit_trace_calls != NULL)
6584 max_epilog_size += 50;
6586 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6587 max_epilog_size += 50;
6589 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6590 cfg->code_size *= 2;
6591 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6592 cfg->stat_code_reallocs++;
6596 * Keep in sync with OP_JMP
6598 code = cfg->native_code + cfg->code_len;
6600 /* Save the uwind state which is needed by the out-of-line code */
6601 mono_emit_unwind_op_remember_state (cfg, code);
6603 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6604 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6608 /* Load returned vtypes into registers if needed */
6609 cinfo = cfg->arch.cinfo;
6610 switch (cinfo->ret.storage) {
6611 case RegTypeStructByVal: {
6612 MonoInst *ins = cfg->ret;
6614 if (cinfo->ret.nregs == 1) {
6615 if (arm_is_imm12 (ins->inst_offset)) {
6616 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6618 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6619 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6622 for (i = 0; i < cinfo->ret.nregs; ++i) {
6623 int offset = ins->inst_offset + (i * 4);
6624 if (arm_is_imm12 (offset)) {
6625 ARM_LDR_IMM (code, i, ins->inst_basereg, offset);
6627 code = mono_arm_emit_load_imm (code, ARMREG_LR, offset);
6628 ARM_LDR_REG_REG (code, i, ins->inst_basereg, ARMREG_LR);
6635 MonoInst *ins = cfg->ret;
6637 for (i = 0; i < cinfo->ret.nregs; ++i) {
6638 if (cinfo->ret.esize == 4)
6639 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6641 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6649 if (method->save_lmf) {
6650 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6651 /* all but r0-r3, sp and pc */
6652 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6655 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6657 /* This points to r4 inside MonoLMF->iregs */
6658 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6660 regmask = 0x9ff0; /* restore lr to pc */
6661 /* Skip caller saved registers not used by the method */
6662 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6663 regmask &= ~(1 << reg);
6668 /* Restored later */
6669 regmask &= ~(1 << ARMREG_PC);
6670 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6671 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6672 for (i = 0; i < 16; i++) {
6673 if (regmask & (1 << i))
6676 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6678 ARM_POP (code, regmask);
6680 for (i = 0; i < 16; i++) {
6681 if (regmask & (1 << i))
6682 mono_emit_unwind_op_same_value (cfg, code, i);
6684 /* Restore saved r7, restore LR to PC */
6685 /* Skip lr from the lmf */
6686 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6687 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6688 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6689 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6692 int i, nused_int_regs = 0;
6694 for (i = 0; i < 16; i++) {
6695 if (cfg->used_int_regs & (1 << i))
6699 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6700 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6702 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6703 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6706 if (cfg->frame_reg != ARMREG_SP) {
6707 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6711 /* Restore saved gregs */
6712 if (cfg->used_int_regs) {
6713 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6714 ARM_POP (code, cfg->used_int_regs);
6715 for (i = 0; i < 16; i++) {
6716 if (cfg->used_int_regs & (1 << i))
6717 mono_emit_unwind_op_same_value (cfg, code, i);
6720 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6721 /* Restore saved r7, restore LR to PC */
6722 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6724 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6725 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6729 /* Restore the unwind state to be the same as before the epilog */
6730 mono_emit_unwind_op_restore_state (cfg, code);
6732 cfg->code_len = code - cfg->native_code;
6734 g_assert (cfg->code_len < cfg->code_size);
6739 mono_arch_emit_exceptions (MonoCompile *cfg)
6741 MonoJumpInfo *patch_info;
6744 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6745 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6746 int max_epilog_size = 50;
6748 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6749 exc_throw_pos [i] = NULL;
6750 exc_throw_found [i] = 0;
6753 /* count the number of exception infos */
6756 * make sure we have enough space for exceptions
6758 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6759 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6760 i = mini_exception_id_by_name (patch_info->data.target);
6761 if (!exc_throw_found [i]) {
6762 max_epilog_size += 32;
6763 exc_throw_found [i] = TRUE;
6768 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6769 cfg->code_size *= 2;
6770 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6771 cfg->stat_code_reallocs++;
6774 code = cfg->native_code + cfg->code_len;
6776 /* add code to raise exceptions */
6777 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6778 switch (patch_info->type) {
6779 case MONO_PATCH_INFO_EXC: {
6780 MonoClass *exc_class;
6781 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6783 i = mini_exception_id_by_name (patch_info->data.target);
6784 if (exc_throw_pos [i]) {
6785 arm_patch (ip, exc_throw_pos [i]);
6786 patch_info->type = MONO_PATCH_INFO_NONE;
6789 exc_throw_pos [i] = code;
6791 arm_patch (ip, code);
6793 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6795 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6796 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6797 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6798 patch_info->data.name = "mono_arch_throw_corlib_exception";
6799 patch_info->ip.i = code - cfg->native_code;
6801 cfg->thunk_area += THUNK_SIZE;
6802 *(guint32*)(gpointer)code = exc_class->type_token - MONO_TOKEN_TYPE_DEF;
6812 cfg->code_len = code - cfg->native_code;
6814 g_assert (cfg->code_len < cfg->code_size);
6818 #endif /* #ifndef DISABLE_JIT */
6821 mono_arch_finish_init (void)
6826 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6831 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6838 mono_arch_print_tree (MonoInst *tree, int arity)
6848 mono_arch_get_patch_offset (guint8 *code)
6855 mono_arch_flush_register_windows (void)
6860 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6862 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6866 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6868 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6872 mono_arch_get_cie_program (void)
6876 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6881 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6882 #define BASE_SIZE (6 * 4)
6883 #define BSEARCH_ENTRY_SIZE (4 * 4)
6884 #define CMP_SIZE (3 * 4)
6885 #define BRANCH_SIZE (1 * 4)
6886 #define CALL_SIZE (2 * 4)
6887 #define WMC_SIZE (8 * 4)
6888 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6891 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6893 guint32 delta = DISTANCE (target, code);
6895 g_assert (delta >= 0 && delta <= 0xFFF);
6896 *target = *target | delta;
6901 #ifdef ENABLE_WRONG_METHOD_CHECK
6903 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6905 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6911 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6912 gpointer fail_tramp)
6915 arminstr_t *code, *start;
6916 gboolean large_offsets = FALSE;
6917 guint32 **constant_pool_starts;
6918 arminstr_t *vtable_target = NULL;
6919 int extra_space = 0;
6920 #ifdef ENABLE_WRONG_METHOD_CHECK
6926 constant_pool_starts = g_new0 (guint32*, count);
6928 for (i = 0; i < count; ++i) {
6929 MonoIMTCheckItem *item = imt_entries [i];
6930 if (item->is_equals) {
6931 gboolean fail_case = !item->check_target_idx && fail_tramp;
6933 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6934 item->chunk_size += 32;
6935 large_offsets = TRUE;
6938 if (item->check_target_idx || fail_case) {
6939 if (!item->compare_done || fail_case)
6940 item->chunk_size += CMP_SIZE;
6941 item->chunk_size += BRANCH_SIZE;
6943 #ifdef ENABLE_WRONG_METHOD_CHECK
6944 item->chunk_size += WMC_SIZE;
6948 item->chunk_size += 16;
6949 large_offsets = TRUE;
6951 item->chunk_size += CALL_SIZE;
6953 item->chunk_size += BSEARCH_ENTRY_SIZE;
6954 imt_entries [item->check_target_idx]->compare_done = TRUE;
6956 size += item->chunk_size;
6960 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6963 code = mono_method_alloc_generic_virtual_thunk (domain, size);
6965 code = mono_domain_code_reserve (domain, size);
6968 unwind_ops = mono_arch_get_cie_program ();
6971 g_print ("Building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6972 for (i = 0; i < count; ++i) {
6973 MonoIMTCheckItem *item = imt_entries [i];
6974 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
6978 if (large_offsets) {
6979 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6980 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
6982 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
6983 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6985 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
6986 vtable_target = code;
6987 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
6988 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
6990 for (i = 0; i < count; ++i) {
6991 MonoIMTCheckItem *item = imt_entries [i];
6992 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
6993 gint32 vtable_offset;
6995 item->code_target = (guint8*)code;
6997 if (item->is_equals) {
6998 gboolean fail_case = !item->check_target_idx && fail_tramp;
7000 if (item->check_target_idx || fail_case) {
7001 if (!item->compare_done || fail_case) {
7003 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7004 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7006 item->jmp_code = (guint8*)code;
7007 ARM_B_COND (code, ARMCOND_NE, 0);
7009 /*Enable the commented code to assert on wrong method*/
7010 #ifdef ENABLE_WRONG_METHOD_CHECK
7012 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7013 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7015 ARM_B_COND (code, ARMCOND_EQ, 0);
7017 /* Define this if your system is so bad that gdb is failing. */
7018 #ifdef BROKEN_DEV_ENV
7019 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
7021 arm_patch (code - 1, mini_dump_bad_imt);
7025 arm_patch (cond, code);
7029 if (item->has_target_code) {
7030 /* Load target address */
7031 target_code_ins = code;
7032 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7033 /* Save it to the fourth slot */
7034 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7035 /* Restore registers and branch */
7036 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7038 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
7040 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
7041 if (!arm_is_imm12 (vtable_offset)) {
7043 * We need to branch to a computed address but we don't have
7044 * a free register to store it, since IP must contain the
7045 * vtable address. So we push the two values to the stack, and
7046 * load them both using LDM.
7048 /* Compute target address */
7049 vtable_offset_ins = code;
7050 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7051 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
7052 /* Save it to the fourth slot */
7053 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7054 /* Restore registers and branch */
7055 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7057 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
7059 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
7060 if (large_offsets) {
7061 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7062 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
7064 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7065 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
7070 arm_patch (item->jmp_code, (guchar*)code);
7072 target_code_ins = code;
7073 /* Load target address */
7074 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7075 /* Save it to the fourth slot */
7076 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7077 /* Restore registers and branch */
7078 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7080 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7081 item->jmp_code = NULL;
7085 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7087 /*must emit after unconditional branch*/
7088 if (vtable_target) {
7089 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7090 item->chunk_size += 4;
7091 vtable_target = NULL;
7094 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7095 constant_pool_starts [i] = code;
7097 code += extra_space;
7101 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7102 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7104 item->jmp_code = (guint8*)code;
7105 ARM_B_COND (code, ARMCOND_HS, 0);
7110 for (i = 0; i < count; ++i) {
7111 MonoIMTCheckItem *item = imt_entries [i];
7112 if (item->jmp_code) {
7113 if (item->check_target_idx)
7114 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7116 if (i > 0 && item->is_equals) {
7118 arminstr_t *space_start = constant_pool_starts [i];
7119 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7120 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7127 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7128 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7133 g_free (constant_pool_starts);
7135 mono_arch_flush_icache ((guint8*)start, size);
7136 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7137 mono_stats.imt_thunks_size += code - start;
7139 g_assert (DISTANCE (start, code) <= size);
7141 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7147 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7149 return ctx->regs [reg];
7153 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7155 ctx->regs [reg] = val;
7159 * mono_arch_get_trampolines:
7161 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7165 mono_arch_get_trampolines (gboolean aot)
7167 return mono_arm_get_exception_trampolines (aot);
7171 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7178 bp = MONO_CONTEXT_GET_BP (ctx);
7179 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7181 old_value = *lr_loc;
7182 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7185 *lr_loc = new_value;
7190 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7192 * mono_arch_set_breakpoint:
7194 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7195 * The location should contain code emitted by OP_SEQ_POINT.
7198 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7201 guint32 native_offset = ip - (guint8*)ji->code_start;
7202 MonoDebugOptions *opt = mini_get_debug_options ();
7205 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7207 if (!breakpoint_tramp)
7208 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7210 g_assert (native_offset % 4 == 0);
7211 g_assert (info->bp_addrs [native_offset / 4] == 0);
7212 info->bp_addrs [native_offset / 4] = opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page;
7213 } else if (opt->soft_breakpoints) {
7215 ARM_BLX_REG (code, ARMREG_LR);
7216 mono_arch_flush_icache (code - 4, 4);
7218 int dreg = ARMREG_LR;
7220 /* Read from another trigger page */
7221 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7223 *(int*)code = (int)bp_trigger_page;
7225 ARM_LDR_IMM (code, dreg, dreg, 0);
7227 mono_arch_flush_icache (code - 16, 16);
7230 /* This is currently implemented by emitting an SWI instruction, which
7231 * qemu/linux seems to convert to a SIGILL.
7233 *(int*)code = (0xef << 24) | 8;
7235 mono_arch_flush_icache (code - 4, 4);
7241 * mono_arch_clear_breakpoint:
7243 * Clear the breakpoint at IP.
7246 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7248 MonoDebugOptions *opt = mini_get_debug_options ();
7253 guint32 native_offset = ip - (guint8*)ji->code_start;
7254 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7256 if (!breakpoint_tramp)
7257 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7259 g_assert (native_offset % 4 == 0);
7260 g_assert (info->bp_addrs [native_offset / 4] == (opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page));
7261 info->bp_addrs [native_offset / 4] = 0;
7262 } else if (opt->soft_breakpoints) {
7265 mono_arch_flush_icache (code - 4, 4);
7267 for (i = 0; i < 4; ++i)
7270 mono_arch_flush_icache (ip, code - ip);
7275 * mono_arch_start_single_stepping:
7277 * Start single stepping.
7280 mono_arch_start_single_stepping (void)
7282 if (ss_trigger_page)
7283 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7285 single_step_tramp = mini_get_single_step_trampoline ();
7289 * mono_arch_stop_single_stepping:
7291 * Stop single stepping.
7294 mono_arch_stop_single_stepping (void)
7296 if (ss_trigger_page)
7297 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7299 single_step_tramp = NULL;
7303 #define DBG_SIGNAL SIGBUS
7305 #define DBG_SIGNAL SIGSEGV
7309 * mono_arch_is_single_step_event:
7311 * Return whenever the machine state in SIGCTX corresponds to a single
7315 mono_arch_is_single_step_event (void *info, void *sigctx)
7317 siginfo_t *sinfo = info;
7319 if (!ss_trigger_page)
7322 /* Sometimes the address is off by 4 */
7323 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7330 * mono_arch_is_breakpoint_event:
7332 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7335 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7337 siginfo_t *sinfo = info;
7339 if (!ss_trigger_page)
7342 if (sinfo->si_signo == DBG_SIGNAL) {
7343 /* Sometimes the address is off by 4 */
7344 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7354 * mono_arch_skip_breakpoint:
7356 * See mini-amd64.c for docs.
7359 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7361 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7365 * mono_arch_skip_single_step:
7367 * See mini-amd64.c for docs.
7370 mono_arch_skip_single_step (MonoContext *ctx)
7372 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7375 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7378 * mono_arch_get_seq_point_info:
7380 * See mini-amd64.c for docs.
7383 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7388 // FIXME: Add a free function
7390 mono_domain_lock (domain);
7391 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7393 mono_domain_unlock (domain);
7396 ji = mono_jit_info_table_find (domain, (char*)code);
7399 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7401 info->ss_trigger_page = ss_trigger_page;
7402 info->bp_trigger_page = bp_trigger_page;
7404 mono_domain_lock (domain);
7405 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7407 mono_domain_unlock (domain);
7414 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7416 ext->lmf.previous_lmf = prev_lmf;
7417 /* Mark that this is a MonoLMFExt */
7418 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7419 ext->lmf.sp = (gssize)ext;
7423 * mono_arch_set_target:
7425 * Set the target architecture the JIT backend should generate code for, in the form
7426 * of a GNU target triplet. Only used in AOT mode.
7429 mono_arch_set_target (char *mtriple)
7431 /* The GNU target triple format is not very well documented */
7432 if (strstr (mtriple, "armv7")) {
7433 v5_supported = TRUE;
7434 v6_supported = TRUE;
7435 v7_supported = TRUE;
7437 if (strstr (mtriple, "armv6")) {
7438 v5_supported = TRUE;
7439 v6_supported = TRUE;
7441 if (strstr (mtriple, "armv7s")) {
7442 v7s_supported = TRUE;
7444 if (strstr (mtriple, "armv7k")) {
7445 v7k_supported = TRUE;
7447 if (strstr (mtriple, "thumbv7s")) {
7448 v5_supported = TRUE;
7449 v6_supported = TRUE;
7450 v7_supported = TRUE;
7451 v7s_supported = TRUE;
7452 thumb_supported = TRUE;
7453 thumb2_supported = TRUE;
7455 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7456 v5_supported = TRUE;
7457 v6_supported = TRUE;
7458 thumb_supported = TRUE;
7461 if (strstr (mtriple, "gnueabi"))
7462 eabi_supported = TRUE;
7466 mono_arch_opcode_supported (int opcode)
7469 case OP_ATOMIC_ADD_I4:
7470 case OP_ATOMIC_EXCHANGE_I4:
7471 case OP_ATOMIC_CAS_I4:
7472 case OP_ATOMIC_LOAD_I1:
7473 case OP_ATOMIC_LOAD_I2:
7474 case OP_ATOMIC_LOAD_I4:
7475 case OP_ATOMIC_LOAD_U1:
7476 case OP_ATOMIC_LOAD_U2:
7477 case OP_ATOMIC_LOAD_U4:
7478 case OP_ATOMIC_STORE_I1:
7479 case OP_ATOMIC_STORE_I2:
7480 case OP_ATOMIC_STORE_I4:
7481 case OP_ATOMIC_STORE_U1:
7482 case OP_ATOMIC_STORE_U2:
7483 case OP_ATOMIC_STORE_U4:
7484 return v7_supported;
7485 case OP_ATOMIC_LOAD_R4:
7486 case OP_ATOMIC_LOAD_R8:
7487 case OP_ATOMIC_STORE_R4:
7488 case OP_ATOMIC_STORE_R8:
7489 return v7_supported && IS_VFP;
7496 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
7498 return get_call_info (mp, sig);