2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
11 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
16 #include <mono/metadata/abi-details.h>
17 #include <mono/metadata/appdomain.h>
18 #include <mono/metadata/profiler-private.h>
19 #include <mono/metadata/debug-helpers.h>
20 #include <mono/utils/mono-mmap.h>
21 #include <mono/utils/mono-hwcap-arm.h>
22 #include <mono/utils/mono-memory-model.h>
23 #include <mono/utils/mono-threads-coop.h>
26 #include "mini-arm-tls.h"
30 #include "debugger-agent.h"
32 #include "mono/arch/arm/arm-vfp-codegen.h"
34 #if (defined(HAVE_KW_THREAD) && defined(__linux__) && defined(__ARM_EABI__)) \
35 || defined(TARGET_ANDROID) \
36 || (defined(TARGET_IOS) && !defined(TARGET_WATCHOS))
40 /* Sanity check: This makes no sense */
41 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
42 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
46 * IS_SOFT_FLOAT: Is full software floating point used?
47 * IS_HARD_FLOAT: Is full hardware floating point used?
48 * IS_VFP: Is hardware floating point with software ABI used?
50 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
51 * IS_VFP may delegate to mono_arch_is_soft_float ().
54 #if defined(ARM_FPU_VFP_HARD)
55 #define IS_SOFT_FLOAT (FALSE)
56 #define IS_HARD_FLOAT (TRUE)
58 #elif defined(ARM_FPU_NONE)
59 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
60 #define IS_HARD_FLOAT (FALSE)
61 #define IS_VFP (!mono_arch_is_soft_float ())
63 #define IS_SOFT_FLOAT (FALSE)
64 #define IS_HARD_FLOAT (FALSE)
68 #define THUNK_SIZE (3 * 4)
70 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
73 void sys_icache_invalidate (void *start, size_t len);
76 /* This mutex protects architecture specific caches */
77 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
78 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
79 static mono_mutex_t mini_arch_mutex;
81 static gboolean v5_supported = FALSE;
82 static gboolean v6_supported = FALSE;
83 static gboolean v7_supported = FALSE;
84 static gboolean v7s_supported = FALSE;
85 static gboolean v7k_supported = FALSE;
86 static gboolean thumb_supported = FALSE;
87 static gboolean thumb2_supported = FALSE;
89 * Whenever to use the ARM EABI
91 static gboolean eabi_supported = FALSE;
94 * Whenever to use the iphone ABI extensions:
95 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
96 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
97 * This is required for debugging/profiling tools to work, but it has some overhead so it should
98 * only be turned on in debug builds.
100 static gboolean iphone_abi = FALSE;
103 * The FPU we are generating code for. This is NOT runtime configurable right now,
104 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
106 static MonoArmFPU arm_fpu;
108 #if defined(ARM_FPU_VFP_HARD)
110 * On armhf, d0-d7 are used for argument passing and d8-d15
111 * must be preserved across calls, which leaves us no room
112 * for scratch registers. So we use d14-d15 but back up their
113 * previous contents to a stack slot before using them - see
114 * mono_arm_emit_vfp_scratch_save/_restore ().
116 static int vfp_scratch1 = ARM_VFP_D14;
117 static int vfp_scratch2 = ARM_VFP_D15;
120 * On armel, d0-d7 do not need to be preserved, so we can
121 * freely make use of them as scratch registers.
123 static int vfp_scratch1 = ARM_VFP_D0;
124 static int vfp_scratch2 = ARM_VFP_D1;
129 static gpointer single_step_tramp, breakpoint_tramp;
132 * The code generated for sequence points reads from this location, which is
133 * made read-only when single stepping is enabled.
135 static gpointer ss_trigger_page;
137 /* Enabled breakpoints read from this trigger page */
138 static gpointer bp_trigger_page;
142 * floating point support: on ARM it is a mess, there are at least 3
143 * different setups, each of which binary incompat with the other.
144 * 1) FPA: old and ugly, but unfortunately what current distros use
145 * the double binary format has the two words swapped. 8 double registers.
146 * Implemented usually by kernel emulation.
147 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
148 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
149 * 3) VFP: the new and actually sensible and useful FP support. Implemented
150 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
152 * We do not care about FPA. We will support soft float and VFP.
154 int mono_exc_esp_offset = 0;
156 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
157 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
158 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
160 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
161 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
162 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
164 //#define DEBUG_IMT 0
167 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
171 mono_arch_regname (int reg)
173 static const char * rnames[] = {
174 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
175 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
176 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
179 if (reg >= 0 && reg < 16)
185 mono_arch_fregname (int reg)
187 static const char * rnames[] = {
188 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
189 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
190 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
191 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
192 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
193 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
196 if (reg >= 0 && reg < 32)
204 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
206 int imm8, rot_amount;
207 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
208 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
212 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
213 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
215 code = mono_arm_emit_load_imm (code, dreg, imm);
216 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
221 /* If dreg == sreg, this clobbers IP */
223 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
225 int imm8, rot_amount;
226 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
227 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
231 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
232 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
234 code = mono_arm_emit_load_imm (code, dreg, imm);
235 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
241 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
243 /* we can use r0-r3, since this is called only for incoming args on the stack */
244 if (size > sizeof (gpointer) * 4) {
246 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
247 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
248 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
249 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
250 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
251 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
252 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
253 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
254 ARM_B_COND (code, ARMCOND_NE, 0);
255 arm_patch (code - 4, start_loop);
258 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
259 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
261 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
262 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
268 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
269 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
270 doffset = soffset = 0;
272 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
273 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
279 g_assert (size == 0);
284 emit_call_reg (guint8 *code, int reg)
287 ARM_BLX_REG (code, reg);
289 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
293 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
299 emit_call_seq (MonoCompile *cfg, guint8 *code)
301 if (cfg->method->dynamic) {
302 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
304 *(gpointer*)code = NULL;
306 code = emit_call_reg (code, ARMREG_IP);
310 cfg->thunk_area += THUNK_SIZE;
315 mono_arm_patchable_b (guint8 *code, int cond)
317 ARM_B_COND (code, cond, 0);
322 mono_arm_patchable_bl (guint8 *code, int cond)
324 ARM_BL_COND (code, cond, 0);
329 mono_arm_emit_tls_get (MonoCompile *cfg, guint8* code, int dreg, int tls_offset)
332 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
333 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
335 code = emit_call_seq (cfg, code);
336 if (dreg != ARMREG_R0)
337 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
339 g_assert_not_reached ();
345 mono_arm_emit_tls_get_reg (MonoCompile *cfg, guint8* code, int dreg, int tls_offset_reg)
348 if (tls_offset_reg != ARMREG_R0)
349 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
350 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
352 code = emit_call_seq (cfg, code);
353 if (dreg != ARMREG_R0)
354 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
356 g_assert_not_reached ();
362 mono_arm_emit_tls_set (MonoCompile *cfg, guint8* code, int sreg, int tls_offset)
365 if (sreg != ARMREG_R1)
366 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
367 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
368 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
370 code = emit_call_seq (cfg, code);
372 g_assert_not_reached ();
378 mono_arm_emit_tls_set_reg (MonoCompile *cfg, guint8* code, int sreg, int tls_offset_reg)
381 /* Get sreg in R1 and tls_offset_reg in R0 */
382 if (tls_offset_reg == ARMREG_R1) {
383 if (sreg == ARMREG_R0) {
384 /* swap sreg and tls_offset_reg */
385 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
386 ARM_EOR_REG_REG (code, tls_offset_reg, sreg, tls_offset_reg);
387 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
389 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
390 if (sreg != ARMREG_R1)
391 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
394 if (sreg != ARMREG_R1)
395 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
396 if (tls_offset_reg != ARMREG_R0)
397 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
399 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
401 code = emit_call_seq (cfg, code);
403 g_assert_not_reached ();
411 * Emit code to push an LMF structure on the LMF stack.
412 * On arm, this is intermixed with the initialization of other fields of the structure.
415 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
417 gboolean get_lmf_fast = FALSE;
420 if (mono_arm_have_tls_get ()) {
422 if (cfg->compile_aot) {
424 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_TLS_OFFSET, (gpointer)TLS_KEY_LMF_ADDR);
425 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
427 *(gpointer*)code = NULL;
429 /* Load the value from the GOT */
430 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_PC, ARMREG_R1);
431 code = mono_arm_emit_tls_get_reg (cfg, code, ARMREG_R0, ARMREG_R1);
433 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
434 g_assert (lmf_addr_tls_offset != -1);
435 code = mono_arm_emit_tls_get (cfg, code, ARMREG_R0, lmf_addr_tls_offset);
440 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
441 (gpointer)"mono_get_lmf_addr");
442 code = emit_call_seq (cfg, code);
444 /* we build the MonoLMF structure on the stack - see mini-arm.h */
445 /* lmf_offset is the offset from the previous stack pointer,
446 * alloc_size is the total stack space allocated, so the offset
447 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
448 * The pointer to the struct is put in r1 (new_lmf).
449 * ip is used as scratch
450 * The callee-saved registers are already in the MonoLMF structure
452 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
453 /* r0 is the result from mono_get_lmf_addr () */
454 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
455 /* new_lmf->previous_lmf = *lmf_addr */
456 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
457 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
458 /* *(lmf_addr) = r1 */
459 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
460 /* Skip method (only needed for trampoline LMF frames) */
461 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
462 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
463 /* save the current IP */
464 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
465 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
467 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
468 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
479 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
483 for (list = inst->float_args; list; list = list->next) {
484 FloatArgData *fad = list->data;
485 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
486 gboolean imm = arm_is_fpimm8 (var->inst_offset);
488 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
494 if (*offset + *max_len > cfg->code_size) {
495 cfg->code_size += *max_len;
496 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
498 code = cfg->native_code + *offset;
502 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
503 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
505 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
507 *offset = code - cfg->native_code;
514 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
518 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
520 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
523 if (!arm_is_fpimm8 (inst->inst_offset)) {
524 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
525 ARM_FSTD (code, reg, ARMREG_LR, 0);
527 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
534 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
538 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
540 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
543 if (!arm_is_fpimm8 (inst->inst_offset)) {
544 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
545 ARM_FLDD (code, reg, ARMREG_LR, 0);
547 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
556 * Emit code to pop an LMF structure from the LMF stack.
559 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
563 if (lmf_offset < 32) {
564 basereg = cfg->frame_reg;
569 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
572 /* ip = previous_lmf */
573 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
575 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
576 /* *(lmf_addr) = previous_lmf */
577 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
582 #endif /* #ifndef DISABLE_JIT */
585 * mono_arm_have_tls_get:
587 * Returns whether we have tls access implemented on the current
591 mono_arm_have_tls_get (void)
601 * mono_arch_get_argument_info:
602 * @csig: a method signature
603 * @param_count: the number of parameters to consider
604 * @arg_info: an array to store the result infos
606 * Gathers information on parameters such as size, alignment and
607 * padding. arg_info should be large enought to hold param_count + 1 entries.
609 * Returns the size of the activation frame.
612 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
614 int k, frame_size = 0;
615 guint32 size, align, pad;
619 t = mini_get_underlying_type (csig->ret);
620 if (MONO_TYPE_ISSTRUCT (t)) {
621 frame_size += sizeof (gpointer);
625 arg_info [0].offset = offset;
628 frame_size += sizeof (gpointer);
632 arg_info [0].size = frame_size;
634 for (k = 0; k < param_count; k++) {
635 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
637 /* ignore alignment for now */
640 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
641 arg_info [k].pad = pad;
643 arg_info [k + 1].pad = 0;
644 arg_info [k + 1].size = size;
646 arg_info [k + 1].offset = offset;
650 align = MONO_ARCH_FRAME_ALIGNMENT;
651 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
652 arg_info [k].pad = pad;
657 #define MAX_ARCH_DELEGATE_PARAMS 3
660 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
662 guint8 *code, *start;
663 GSList *unwind_ops = mono_arch_get_cie_program ();
666 start = code = mono_global_codeman_reserve (12);
668 /* Replace the this argument with the target */
669 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
670 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
671 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
673 g_assert ((code - start) <= 12);
675 mono_arch_flush_icache (start, 12);
679 size = 8 + param_count * 4;
680 start = code = mono_global_codeman_reserve (size);
682 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
683 /* slide down the arguments */
684 for (i = 0; i < param_count; ++i) {
685 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
687 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
689 g_assert ((code - start) <= size);
691 mono_arch_flush_icache (start, size);
695 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
697 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
698 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
702 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
708 * mono_arch_get_delegate_invoke_impls:
710 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
714 mono_arch_get_delegate_invoke_impls (void)
720 get_delegate_invoke_impl (&info, TRUE, 0);
721 res = g_slist_prepend (res, info);
723 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
724 get_delegate_invoke_impl (&info, FALSE, i);
725 res = g_slist_prepend (res, info);
732 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
734 guint8 *code, *start;
737 /* FIXME: Support more cases */
738 sig_ret = mini_get_underlying_type (sig->ret);
739 if (MONO_TYPE_ISSTRUCT (sig_ret))
743 static guint8* cached = NULL;
744 mono_mini_arch_lock ();
746 mono_mini_arch_unlock ();
751 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
754 start = get_delegate_invoke_impl (&info, TRUE, 0);
755 mono_tramp_info_register (info, NULL);
758 mono_mini_arch_unlock ();
761 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
764 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
766 for (i = 0; i < sig->param_count; ++i)
767 if (!mono_is_regsize_var (sig->params [i]))
770 mono_mini_arch_lock ();
771 code = cache [sig->param_count];
773 mono_mini_arch_unlock ();
778 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
779 start = mono_aot_get_trampoline (name);
783 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
784 mono_tramp_info_register (info, NULL);
786 cache [sig->param_count] = start;
787 mono_mini_arch_unlock ();
795 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
801 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
803 return (gpointer)regs [ARMREG_R0];
807 * Initialize the cpu to execute managed code.
810 mono_arch_cpu_init (void)
812 i8_align = MONO_ABI_ALIGNOF (gint64);
813 #ifdef MONO_CROSS_COMPILE
814 /* Need to set the alignment of i8 since it can different on the target */
815 #ifdef TARGET_ANDROID
817 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
823 * Initialize architecture specific code.
826 mono_arch_init (void)
828 const char *cpu_arch;
830 #ifdef TARGET_WATCHOS
831 mini_get_debug_options ()->soft_breakpoints = TRUE;
834 mono_os_mutex_init_recursive (&mini_arch_mutex);
835 if (mini_get_debug_options ()->soft_breakpoints) {
836 breakpoint_tramp = mini_get_breakpoint_trampoline ();
838 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
839 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
840 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
843 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
844 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
845 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
846 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
847 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
849 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
851 #if defined(__ARM_EABI__)
852 eabi_supported = TRUE;
855 #if defined(ARM_FPU_VFP_HARD)
856 arm_fpu = MONO_ARM_FPU_VFP_HARD;
858 arm_fpu = MONO_ARM_FPU_VFP;
860 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
862 * If we're compiling with a soft float fallback and it
863 * turns out that no VFP unit is available, we need to
864 * switch to soft float. We don't do this for iOS, since
865 * iOS devices always have a VFP unit.
867 if (!mono_hwcap_arm_has_vfp)
868 arm_fpu = MONO_ARM_FPU_NONE;
871 * This environment variable can be useful in testing
872 * environments to make sure the soft float fallback
873 * works. Most ARM devices have VFP units these days, so
874 * normally soft float code would not be exercised much.
876 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
878 if (soft && !strncmp (soft, "1", 1))
879 arm_fpu = MONO_ARM_FPU_NONE;
883 v5_supported = mono_hwcap_arm_is_v5;
884 v6_supported = mono_hwcap_arm_is_v6;
885 v7_supported = mono_hwcap_arm_is_v7;
888 * On weird devices, the hwcap code may fail to detect
889 * the ARM version. In that case, we can at least safely
890 * assume the version the runtime was compiled for.
902 #if defined(__APPLE__)
903 /* iOS is special-cased here because we don't yet
904 have a way to properly detect CPU features on it. */
905 thumb_supported = TRUE;
908 thumb_supported = mono_hwcap_arm_has_thumb;
909 thumb2_supported = mono_hwcap_arm_has_thumb2;
912 /* Format: armv(5|6|7[s])[-thumb[2]] */
913 cpu_arch = g_getenv ("MONO_CPU_ARCH");
915 /* Do this here so it overrides any detection. */
917 if (strncmp (cpu_arch, "armv", 4) == 0) {
918 v5_supported = cpu_arch [4] >= '5';
919 v6_supported = cpu_arch [4] >= '6';
920 v7_supported = cpu_arch [4] >= '7';
921 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
922 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
925 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
926 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
931 * Cleanup architecture specific code.
934 mono_arch_cleanup (void)
939 * This function returns the optimizations supported on this cpu.
942 mono_arch_cpu_optimizations (guint32 *exclude_mask)
944 /* no arm-specific optimizations yet */
950 * This function test for all SIMD functions supported.
952 * Returns a bitmask corresponding to all supported versions.
956 mono_arch_cpu_enumerate_simd_versions (void)
958 /* SIMD is currently unimplemented */
963 mono_arm_is_hard_float (void)
965 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
971 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
973 if (v7s_supported || v7k_supported) {
987 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
989 mono_arch_is_soft_float (void)
991 return arm_fpu == MONO_ARM_FPU_NONE;
996 is_regsize_var (MonoType *t)
1000 t = mini_get_underlying_type (t);
1007 case MONO_TYPE_FNPTR:
1009 case MONO_TYPE_OBJECT:
1010 case MONO_TYPE_STRING:
1011 case MONO_TYPE_CLASS:
1012 case MONO_TYPE_SZARRAY:
1013 case MONO_TYPE_ARRAY:
1015 case MONO_TYPE_GENERICINST:
1016 if (!mono_type_generic_inst_is_valuetype (t))
1019 case MONO_TYPE_VALUETYPE:
1026 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1031 for (i = 0; i < cfg->num_varinfo; i++) {
1032 MonoInst *ins = cfg->varinfo [i];
1033 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1036 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1039 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1042 /* we can only allocate 32 bit values */
1043 if (is_regsize_var (ins->inst_vtype)) {
1044 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1045 g_assert (i == vmv->idx);
1046 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1054 mono_arch_get_global_int_regs (MonoCompile *cfg)
1058 mono_arch_compute_omit_fp (cfg);
1061 * FIXME: Interface calls might go through a static rgctx trampoline which
1062 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1065 if (cfg->flags & MONO_CFG_HAS_CALLS)
1066 cfg->uses_rgctx_reg = TRUE;
1068 if (cfg->arch.omit_fp)
1069 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1070 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1071 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1072 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1074 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1075 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1077 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1078 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1079 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1080 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1081 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1082 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1088 * mono_arch_regalloc_cost:
1090 * Return the cost, in number of memory references, of the action of
1091 * allocating the variable VMV into a register during global register
1095 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1101 #endif /* #ifndef DISABLE_JIT */
1104 mono_arch_flush_icache (guint8 *code, gint size)
1106 #if defined(MONO_CROSS_COMPILE)
1108 sys_icache_invalidate (code, size);
1110 __builtin___clear_cache (code, code + size);
1117 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1120 if (*gr > ARMREG_R3) {
1122 ainfo->offset = *stack_size;
1123 ainfo->reg = ARMREG_SP; /* in the caller */
1124 ainfo->storage = RegTypeBase;
1127 ainfo->storage = RegTypeGeneral;
1134 split = i8_align == 4;
1139 if (*gr == ARMREG_R3 && split) {
1140 /* first word in r3 and the second on the stack */
1141 ainfo->offset = *stack_size;
1142 ainfo->reg = ARMREG_SP; /* in the caller */
1143 ainfo->storage = RegTypeBaseGen;
1145 } else if (*gr >= ARMREG_R3) {
1146 if (eabi_supported) {
1147 /* darwin aligns longs to 4 byte only */
1148 if (i8_align == 8) {
1153 ainfo->offset = *stack_size;
1154 ainfo->reg = ARMREG_SP; /* in the caller */
1155 ainfo->storage = RegTypeBase;
1158 if (eabi_supported) {
1159 if (i8_align == 8 && ((*gr) & 1))
1162 ainfo->storage = RegTypeIRegPair;
1171 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1174 * If we're calling a function like this:
1176 * void foo(float a, double b, float c)
1178 * We pass a in s0 and b in d1. That leaves us
1179 * with s1 being unused. The armhf ABI recognizes
1180 * this and requires register assignment to then
1181 * use that for the next single-precision arg,
1182 * i.e. c in this example. So float_spare either
1183 * tells us which reg to use for the next single-
1184 * precision arg, or it's -1, meaning use *fpr.
1186 * Note that even though most of the JIT speaks
1187 * double-precision, fpr represents single-
1188 * precision registers.
1190 * See parts 5.5 and 6.1.2 of the AAPCS for how
1194 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1195 ainfo->storage = RegTypeFP;
1199 * If we're passing a double-precision value
1200 * and *fpr is odd (e.g. it's s1, s3, ...)
1201 * we need to use the next even register. So
1202 * we mark the current *fpr as a spare that
1203 * can be used for the next single-precision
1207 *float_spare = *fpr;
1212 * At this point, we have an even register
1213 * so we assign that and move along.
1217 } else if (*float_spare >= 0) {
1219 * We're passing a single-precision value
1220 * and it looks like a spare single-
1221 * precision register is available. Let's
1225 ainfo->reg = *float_spare;
1229 * If we hit this branch, we're passing a
1230 * single-precision value and we can simply
1231 * use the next available register.
1239 * We've exhausted available floating point
1240 * regs, so pass the rest on the stack.
1248 ainfo->offset = *stack_size;
1249 ainfo->reg = ARMREG_SP;
1250 ainfo->storage = RegTypeBase;
1257 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1261 MonoClassField *field;
1262 MonoType *ftype, *prev_ftype = NULL;
1265 klass = mono_class_from_mono_type (t);
1267 while ((field = mono_class_get_fields (klass, &iter))) {
1268 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1270 ftype = mono_field_get_type (field);
1271 ftype = mini_get_underlying_type (ftype);
1273 if (MONO_TYPE_ISSTRUCT (ftype)) {
1274 int nested_nfields, nested_esize;
1276 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1278 if (nested_esize == 4)
1279 ftype = &mono_defaults.single_class->byval_arg;
1281 ftype = &mono_defaults.double_class->byval_arg;
1282 if (prev_ftype && prev_ftype->type != ftype->type)
1285 nfields += nested_nfields;
1287 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1289 if (prev_ftype && prev_ftype->type != ftype->type)
1295 if (nfields == 0 || nfields > 4)
1297 *out_nfields = nfields;
1298 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1303 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1305 guint i, gr, fpr, pstart;
1307 int n = sig->hasthis + sig->param_count;
1311 guint32 stack_size = 0;
1313 gboolean is_pinvoke = sig->pinvoke;
1314 gboolean vtype_retaddr = FALSE;
1317 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1319 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1326 t = mini_get_underlying_type (sig->ret);
1337 case MONO_TYPE_FNPTR:
1338 case MONO_TYPE_CLASS:
1339 case MONO_TYPE_OBJECT:
1340 case MONO_TYPE_SZARRAY:
1341 case MONO_TYPE_ARRAY:
1342 case MONO_TYPE_STRING:
1343 cinfo->ret.storage = RegTypeGeneral;
1344 cinfo->ret.reg = ARMREG_R0;
1348 cinfo->ret.storage = RegTypeIRegPair;
1349 cinfo->ret.reg = ARMREG_R0;
1353 cinfo->ret.storage = RegTypeFP;
1355 if (t->type == MONO_TYPE_R4)
1356 cinfo->ret.size = 4;
1358 cinfo->ret.size = 8;
1360 if (IS_HARD_FLOAT) {
1361 cinfo->ret.reg = ARM_VFP_F0;
1363 cinfo->ret.reg = ARMREG_R0;
1366 case MONO_TYPE_GENERICINST:
1367 if (!mono_type_generic_inst_is_valuetype (t)) {
1368 cinfo->ret.storage = RegTypeGeneral;
1369 cinfo->ret.reg = ARMREG_R0;
1372 if (mini_is_gsharedvt_variable_type (t)) {
1373 cinfo->ret.storage = RegTypeStructByAddr;
1377 case MONO_TYPE_VALUETYPE:
1378 case MONO_TYPE_TYPEDBYREF:
1379 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1380 cinfo->ret.storage = RegTypeHFA;
1382 cinfo->ret.nregs = nfields;
1383 cinfo->ret.esize = esize;
1386 int native_size = mono_class_native_size (mono_class_from_mono_type (t), &align);
1389 #ifdef TARGET_WATCHOS
1394 if (native_size <= max_size) {
1395 cinfo->ret.storage = RegTypeStructByVal;
1396 cinfo->ret.struct_size = native_size;
1397 cinfo->ret.nregs = ALIGN_TO (native_size, 4) / 4;
1399 cinfo->ret.storage = RegTypeStructByAddr;
1402 cinfo->ret.storage = RegTypeStructByAddr;
1407 case MONO_TYPE_MVAR:
1408 g_assert (mini_is_gsharedvt_type (t));
1409 cinfo->ret.storage = RegTypeStructByAddr;
1411 case MONO_TYPE_VOID:
1414 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1417 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1422 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1423 * the first argument, allowing 'this' to be always passed in the first arg reg.
1424 * Also do this if the first argument is a reference type, since virtual calls
1425 * are sometimes made using calli without sig->hasthis set, like in the delegate
1428 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1430 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1432 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1436 cinfo->ret.reg = gr;
1438 cinfo->vret_arg_index = 1;
1442 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1445 if (vtype_retaddr) {
1446 cinfo->ret.reg = gr;
1451 DEBUG(g_print("params: %d\n", sig->param_count));
1452 for (i = pstart; i < sig->param_count; ++i) {
1453 ArgInfo *ainfo = &cinfo->args [n];
1455 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1456 /* Prevent implicit arguments and sig_cookie from
1457 being passed in registers */
1460 /* Emit the signature cookie just before the implicit arguments */
1461 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1463 DEBUG(g_print("param %d: ", i));
1464 if (sig->params [i]->byref) {
1465 DEBUG(g_print("byref\n"));
1466 add_general (&gr, &stack_size, ainfo, TRUE);
1470 t = mini_get_underlying_type (sig->params [i]);
1474 cinfo->args [n].size = 1;
1475 add_general (&gr, &stack_size, ainfo, TRUE);
1479 cinfo->args [n].size = 2;
1480 add_general (&gr, &stack_size, ainfo, TRUE);
1484 cinfo->args [n].size = 4;
1485 add_general (&gr, &stack_size, ainfo, TRUE);
1490 case MONO_TYPE_FNPTR:
1491 case MONO_TYPE_CLASS:
1492 case MONO_TYPE_OBJECT:
1493 case MONO_TYPE_STRING:
1494 case MONO_TYPE_SZARRAY:
1495 case MONO_TYPE_ARRAY:
1496 cinfo->args [n].size = sizeof (gpointer);
1497 add_general (&gr, &stack_size, ainfo, TRUE);
1499 case MONO_TYPE_GENERICINST:
1500 if (!mono_type_generic_inst_is_valuetype (t)) {
1501 cinfo->args [n].size = sizeof (gpointer);
1502 add_general (&gr, &stack_size, ainfo, TRUE);
1505 if (mini_is_gsharedvt_variable_type (t)) {
1506 /* gsharedvt arguments are passed by ref */
1507 g_assert (mini_is_gsharedvt_type (t));
1508 add_general (&gr, &stack_size, ainfo, TRUE);
1509 switch (ainfo->storage) {
1510 case RegTypeGeneral:
1511 ainfo->storage = RegTypeGSharedVtInReg;
1514 ainfo->storage = RegTypeGSharedVtOnStack;
1517 g_assert_not_reached ();
1522 case MONO_TYPE_TYPEDBYREF:
1523 case MONO_TYPE_VALUETYPE: {
1526 int nwords, nfields, esize;
1529 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1530 if (fpr + nfields < ARM_VFP_F16) {
1531 ainfo->storage = RegTypeHFA;
1533 ainfo->nregs = nfields;
1534 ainfo->esize = esize;
1545 if (t->type == MONO_TYPE_TYPEDBYREF) {
1546 size = sizeof (MonoTypedRef);
1547 align = sizeof (gpointer);
1549 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1551 size = mono_class_native_size (klass, &align);
1553 size = mini_type_stack_size_full (t, &align, FALSE);
1555 DEBUG(g_print ("load %d bytes struct\n", size));
1557 #ifdef TARGET_WATCHOS
1558 /* Watchos pass large structures by ref */
1559 /* We only do this for pinvoke to make gsharedvt/dyncall simpler */
1560 if (sig->pinvoke && size > 16) {
1561 add_general (&gr, &stack_size, ainfo, TRUE);
1562 switch (ainfo->storage) {
1563 case RegTypeGeneral:
1564 ainfo->storage = RegTypeStructByAddr;
1567 ainfo->storage = RegTypeStructByAddrOnStack;
1570 g_assert_not_reached ();
1579 align_size += (sizeof (gpointer) - 1);
1580 align_size &= ~(sizeof (gpointer) - 1);
1581 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1582 ainfo->storage = RegTypeStructByVal;
1583 ainfo->struct_size = size;
1584 /* FIXME: align stack_size if needed */
1585 if (eabi_supported) {
1586 if (align >= 8 && (gr & 1))
1589 if (gr > ARMREG_R3) {
1591 ainfo->vtsize = nwords;
1593 int rest = ARMREG_R3 - gr + 1;
1594 int n_in_regs = rest >= nwords? nwords: rest;
1596 ainfo->size = n_in_regs;
1597 ainfo->vtsize = nwords - n_in_regs;
1600 nwords -= n_in_regs;
1602 if (sig->call_convention == MONO_CALL_VARARG)
1603 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1604 stack_size = ALIGN_TO (stack_size, align);
1605 ainfo->offset = stack_size;
1606 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1607 stack_size += nwords * sizeof (gpointer);
1613 add_general (&gr, &stack_size, ainfo, FALSE);
1619 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1621 add_general (&gr, &stack_size, ainfo, TRUE);
1627 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1629 add_general (&gr, &stack_size, ainfo, FALSE);
1632 case MONO_TYPE_MVAR:
1633 /* gsharedvt arguments are passed by ref */
1634 g_assert (mini_is_gsharedvt_type (t));
1635 add_general (&gr, &stack_size, ainfo, TRUE);
1636 switch (ainfo->storage) {
1637 case RegTypeGeneral:
1638 ainfo->storage = RegTypeGSharedVtInReg;
1641 ainfo->storage = RegTypeGSharedVtOnStack;
1644 g_assert_not_reached ();
1648 g_error ("Can't handle 0x%x", sig->params [i]->type);
1653 /* Handle the case where there are no implicit arguments */
1654 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1655 /* Prevent implicit arguments and sig_cookie from
1656 being passed in registers */
1659 /* Emit the signature cookie just before the implicit arguments */
1660 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1663 /* align stack size to 8 */
1664 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1665 stack_size = (stack_size + 7) & ~7;
1667 cinfo->stack_usage = stack_size;
1673 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1675 MonoType *callee_ret;
1679 c1 = get_call_info (NULL, caller_sig);
1680 c2 = get_call_info (NULL, callee_sig);
1683 * Tail calls with more callee stack usage than the caller cannot be supported, since
1684 * the extra stack space would be left on the stack after the tail call.
1686 res = c1->stack_usage >= c2->stack_usage;
1687 callee_ret = mini_get_underlying_type (callee_sig->ret);
1688 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1689 /* An address on the callee's stack is passed as the first argument */
1692 if (c2->stack_usage > 16 * 4)
1704 debug_omit_fp (void)
1707 return mono_debug_count ();
1714 * mono_arch_compute_omit_fp:
1716 * Determine whenever the frame pointer can be eliminated.
1719 mono_arch_compute_omit_fp (MonoCompile *cfg)
1721 MonoMethodSignature *sig;
1722 MonoMethodHeader *header;
1726 if (cfg->arch.omit_fp_computed)
1729 header = cfg->header;
1731 sig = mono_method_signature (cfg->method);
1733 if (!cfg->arch.cinfo)
1734 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1735 cinfo = cfg->arch.cinfo;
1738 * FIXME: Remove some of the restrictions.
1740 cfg->arch.omit_fp = TRUE;
1741 cfg->arch.omit_fp_computed = TRUE;
1743 if (cfg->disable_omit_fp)
1744 cfg->arch.omit_fp = FALSE;
1745 if (!debug_omit_fp ())
1746 cfg->arch.omit_fp = FALSE;
1748 if (cfg->method->save_lmf)
1749 cfg->arch.omit_fp = FALSE;
1751 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1752 cfg->arch.omit_fp = FALSE;
1753 if (header->num_clauses)
1754 cfg->arch.omit_fp = FALSE;
1755 if (cfg->param_area)
1756 cfg->arch.omit_fp = FALSE;
1757 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1758 cfg->arch.omit_fp = FALSE;
1759 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1760 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1761 cfg->arch.omit_fp = FALSE;
1762 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1763 ArgInfo *ainfo = &cinfo->args [i];
1765 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1767 * The stack offset can only be determined when the frame
1770 cfg->arch.omit_fp = FALSE;
1775 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1776 MonoInst *ins = cfg->varinfo [i];
1779 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1784 * Set var information according to the calling convention. arm version.
1785 * The locals var stuff should most likely be split in another method.
1788 mono_arch_allocate_vars (MonoCompile *cfg)
1790 MonoMethodSignature *sig;
1791 MonoMethodHeader *header;
1794 int i, offset, size, align, curinst;
1799 sig = mono_method_signature (cfg->method);
1801 if (!cfg->arch.cinfo)
1802 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1803 cinfo = cfg->arch.cinfo;
1804 sig_ret = mini_get_underlying_type (sig->ret);
1806 mono_arch_compute_omit_fp (cfg);
1808 if (cfg->arch.omit_fp)
1809 cfg->frame_reg = ARMREG_SP;
1811 cfg->frame_reg = ARMREG_FP;
1813 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1815 /* allow room for the vararg method args: void* and long/double */
1816 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1817 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1819 header = cfg->header;
1821 /* See mono_arch_get_global_int_regs () */
1822 if (cfg->flags & MONO_CFG_HAS_CALLS)
1823 cfg->uses_rgctx_reg = TRUE;
1825 if (cfg->frame_reg != ARMREG_SP)
1826 cfg->used_int_regs |= 1 << cfg->frame_reg;
1828 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1829 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1830 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1834 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1835 if (sig_ret->type != MONO_TYPE_VOID) {
1836 cfg->ret->opcode = OP_REGVAR;
1837 cfg->ret->inst_c0 = ARMREG_R0;
1840 /* local vars are at a positive offset from the stack pointer */
1842 * also note that if the function uses alloca, we use FP
1843 * to point at the local variables.
1845 offset = 0; /* linkage area */
1846 /* align the offset to 16 bytes: not sure this is needed here */
1848 //offset &= ~(8 - 1);
1850 /* add parameter area size for called functions */
1851 offset += cfg->param_area;
1854 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1857 /* allow room to save the return value */
1858 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1861 switch (cinfo->ret.storage) {
1862 case RegTypeStructByVal:
1864 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1865 offset = ALIGN_TO (offset, 8);
1866 cfg->ret->opcode = OP_REGOFFSET;
1867 cfg->ret->inst_basereg = cfg->frame_reg;
1868 cfg->ret->inst_offset = offset;
1869 if (cinfo->ret.storage == RegTypeStructByVal)
1870 offset += cinfo->ret.nregs * sizeof (gpointer);
1874 case RegTypeStructByAddr:
1875 ins = cfg->vret_addr;
1876 offset += sizeof(gpointer) - 1;
1877 offset &= ~(sizeof(gpointer) - 1);
1878 ins->inst_offset = offset;
1879 ins->opcode = OP_REGOFFSET;
1880 ins->inst_basereg = cfg->frame_reg;
1881 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1882 g_print ("vret_addr =");
1883 mono_print_ins (cfg->vret_addr);
1885 offset += sizeof(gpointer);
1891 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1892 if (cfg->arch.seq_point_info_var) {
1895 ins = cfg->arch.seq_point_info_var;
1899 offset += align - 1;
1900 offset &= ~(align - 1);
1901 ins->opcode = OP_REGOFFSET;
1902 ins->inst_basereg = cfg->frame_reg;
1903 ins->inst_offset = offset;
1906 if (cfg->arch.ss_trigger_page_var) {
1909 ins = cfg->arch.ss_trigger_page_var;
1912 offset += align - 1;
1913 offset &= ~(align - 1);
1914 ins->opcode = OP_REGOFFSET;
1915 ins->inst_basereg = cfg->frame_reg;
1916 ins->inst_offset = offset;
1920 if (cfg->arch.seq_point_ss_method_var) {
1923 ins = cfg->arch.seq_point_ss_method_var;
1926 offset += align - 1;
1927 offset &= ~(align - 1);
1928 ins->opcode = OP_REGOFFSET;
1929 ins->inst_basereg = cfg->frame_reg;
1930 ins->inst_offset = offset;
1933 if (cfg->arch.seq_point_bp_method_var) {
1936 ins = cfg->arch.seq_point_bp_method_var;
1939 offset += align - 1;
1940 offset &= ~(align - 1);
1941 ins->opcode = OP_REGOFFSET;
1942 ins->inst_basereg = cfg->frame_reg;
1943 ins->inst_offset = offset;
1947 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
1948 /* Allocate a temporary used by the atomic ops */
1952 /* Allocate a local slot to hold the sig cookie address */
1953 offset += align - 1;
1954 offset &= ~(align - 1);
1955 cfg->arch.atomic_tmp_offset = offset;
1958 cfg->arch.atomic_tmp_offset = -1;
1961 cfg->locals_min_stack_offset = offset;
1963 curinst = cfg->locals_start;
1964 for (i = curinst; i < cfg->num_varinfo; ++i) {
1967 ins = cfg->varinfo [i];
1968 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1971 t = ins->inst_vtype;
1972 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
1975 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1976 * pinvoke wrappers when they call functions returning structure */
1977 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
1978 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
1982 size = mono_type_size (t, &align);
1984 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1985 * since it loads/stores misaligned words, which don't do the right thing.
1987 if (align < 4 && size >= 4)
1989 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1990 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1991 offset += align - 1;
1992 offset &= ~(align - 1);
1993 ins->opcode = OP_REGOFFSET;
1994 ins->inst_offset = offset;
1995 ins->inst_basereg = cfg->frame_reg;
1997 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
2000 cfg->locals_max_stack_offset = offset;
2004 ins = cfg->args [curinst];
2005 if (ins->opcode != OP_REGVAR) {
2006 ins->opcode = OP_REGOFFSET;
2007 ins->inst_basereg = cfg->frame_reg;
2008 offset += sizeof (gpointer) - 1;
2009 offset &= ~(sizeof (gpointer) - 1);
2010 ins->inst_offset = offset;
2011 offset += sizeof (gpointer);
2016 if (sig->call_convention == MONO_CALL_VARARG) {
2020 /* Allocate a local slot to hold the sig cookie address */
2021 offset += align - 1;
2022 offset &= ~(align - 1);
2023 cfg->sig_cookie = offset;
2027 for (i = 0; i < sig->param_count; ++i) {
2028 ainfo = cinfo->args + i;
2030 ins = cfg->args [curinst];
2032 switch (ainfo->storage) {
2034 offset = ALIGN_TO (offset, 8);
2035 ins->opcode = OP_REGOFFSET;
2036 ins->inst_basereg = cfg->frame_reg;
2037 /* These arguments are saved to the stack in the prolog */
2038 ins->inst_offset = offset;
2039 if (cfg->verbose_level >= 2)
2040 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2048 if (ins->opcode != OP_REGVAR) {
2049 ins->opcode = OP_REGOFFSET;
2050 ins->inst_basereg = cfg->frame_reg;
2051 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
2053 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2054 * since it loads/stores misaligned words, which don't do the right thing.
2056 if (align < 4 && size >= 4)
2058 /* The code in the prolog () stores words when storing vtypes received in a register */
2059 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2061 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2062 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2063 offset += align - 1;
2064 offset &= ~(align - 1);
2065 ins->inst_offset = offset;
2071 /* align the offset to 8 bytes */
2072 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2073 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2078 cfg->stack_offset = offset;
2082 mono_arch_create_vars (MonoCompile *cfg)
2084 MonoMethodSignature *sig;
2088 sig = mono_method_signature (cfg->method);
2090 if (!cfg->arch.cinfo)
2091 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2092 cinfo = cfg->arch.cinfo;
2094 if (IS_HARD_FLOAT) {
2095 for (i = 0; i < 2; i++) {
2096 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2097 inst->flags |= MONO_INST_VOLATILE;
2099 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2103 if (cinfo->ret.storage == RegTypeStructByVal)
2104 cfg->ret_var_is_local = TRUE;
2106 if (cinfo->ret.storage == RegTypeStructByAddr) {
2107 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2108 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2109 g_print ("vret_addr = ");
2110 mono_print_ins (cfg->vret_addr);
2114 if (cfg->gen_sdb_seq_points) {
2115 if (cfg->compile_aot) {
2116 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2117 ins->flags |= MONO_INST_VOLATILE;
2118 cfg->arch.seq_point_info_var = ins;
2120 if (!cfg->soft_breakpoints) {
2121 /* Allocate a separate variable for this to save 1 load per seq point */
2122 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2123 ins->flags |= MONO_INST_VOLATILE;
2124 cfg->arch.ss_trigger_page_var = ins;
2127 if (cfg->soft_breakpoints) {
2130 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2131 ins->flags |= MONO_INST_VOLATILE;
2132 cfg->arch.seq_point_ss_method_var = ins;
2134 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2135 ins->flags |= MONO_INST_VOLATILE;
2136 cfg->arch.seq_point_bp_method_var = ins;
2142 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2144 MonoMethodSignature *tmp_sig;
2147 if (call->tail_call)
2150 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2153 * mono_ArgIterator_Setup assumes the signature cookie is
2154 * passed first and all the arguments which were before it are
2155 * passed on the stack after the signature. So compensate by
2156 * passing a different signature.
2158 tmp_sig = mono_metadata_signature_dup (call->signature);
2159 tmp_sig->param_count -= call->signature->sentinelpos;
2160 tmp_sig->sentinelpos = 0;
2161 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2163 sig_reg = mono_alloc_ireg (cfg);
2164 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2166 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2171 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2176 LLVMCallInfo *linfo;
2178 n = sig->param_count + sig->hasthis;
2180 cinfo = get_call_info (cfg->mempool, sig);
2182 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2185 * LLVM always uses the native ABI while we use our own ABI, the
2186 * only difference is the handling of vtypes:
2187 * - we only pass/receive them in registers in some cases, and only
2188 * in 1 or 2 integer registers.
2190 switch (cinfo->ret.storage) {
2191 case RegTypeGeneral:
2194 case RegTypeIRegPair:
2196 case RegTypeStructByAddr:
2197 /* Vtype returned using a hidden argument */
2198 linfo->ret.storage = LLVMArgVtypeRetAddr;
2199 linfo->vret_arg_index = cinfo->vret_arg_index;
2202 case RegTypeStructByVal:
2203 /* LLVM models this by returning an int array */
2204 linfo->ret.storage = LLVMArgAsIArgs;
2205 linfo->ret.nslots = cinfo->ret.nregs;
2209 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2210 cfg->disable_llvm = TRUE;
2214 for (i = 0; i < n; ++i) {
2215 LLVMArgInfo *lainfo = &linfo->args [i];
2216 ainfo = cinfo->args + i;
2218 lainfo->storage = LLVMArgNone;
2220 switch (ainfo->storage) {
2221 case RegTypeGeneral:
2222 case RegTypeIRegPair:
2224 case RegTypeBaseGen:
2226 lainfo->storage = LLVMArgNormal;
2228 case RegTypeStructByVal:
2229 lainfo->storage = LLVMArgAsIArgs;
2230 lainfo->nslots = ainfo->struct_size / sizeof (gpointer);
2232 case RegTypeStructByAddr:
2233 case RegTypeStructByAddrOnStack:
2234 lainfo->storage = LLVMArgVtypeByRef;
2237 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2238 cfg->disable_llvm = TRUE;
2248 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2251 MonoMethodSignature *sig;
2255 sig = call->signature;
2256 n = sig->param_count + sig->hasthis;
2258 cinfo = get_call_info (cfg->mempool, sig);
2260 switch (cinfo->ret.storage) {
2261 case RegTypeStructByVal:
2263 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
2264 /* The JIT will transform this into a normal call */
2265 call->vret_in_reg = TRUE;
2268 if (call->inst.opcode == OP_TAILCALL)
2271 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2272 * the location pointed to by it after call in emit_move_return_value ().
2274 if (!cfg->arch.vret_addr_loc) {
2275 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2276 /* Prevent it from being register allocated or optimized away */
2277 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2280 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2282 case RegTypeStructByAddr: {
2284 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2285 vtarg->sreg1 = call->vret_var->dreg;
2286 vtarg->dreg = mono_alloc_preg (cfg);
2287 MONO_ADD_INS (cfg->cbb, vtarg);
2289 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2296 for (i = 0; i < n; ++i) {
2297 ArgInfo *ainfo = cinfo->args + i;
2300 if (i >= sig->hasthis)
2301 t = sig->params [i - sig->hasthis];
2303 t = &mono_defaults.int_class->byval_arg;
2304 t = mini_get_underlying_type (t);
2306 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2307 /* Emit the signature cookie just before the implicit arguments */
2308 emit_sig_cookie (cfg, call, cinfo);
2311 in = call->args [i];
2313 switch (ainfo->storage) {
2314 case RegTypeGeneral:
2315 case RegTypeIRegPair:
2316 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2317 MONO_INST_NEW (cfg, ins, OP_MOVE);
2318 ins->dreg = mono_alloc_ireg (cfg);
2319 ins->sreg1 = MONO_LVREG_LS (in->dreg);
2320 MONO_ADD_INS (cfg->cbb, ins);
2321 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2323 MONO_INST_NEW (cfg, ins, OP_MOVE);
2324 ins->dreg = mono_alloc_ireg (cfg);
2325 ins->sreg1 = MONO_LVREG_MS (in->dreg);
2326 MONO_ADD_INS (cfg->cbb, ins);
2327 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2328 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2329 if (ainfo->size == 4) {
2330 if (IS_SOFT_FLOAT) {
2331 /* mono_emit_call_args () have already done the r8->r4 conversion */
2332 /* The converted value is in an int vreg */
2333 MONO_INST_NEW (cfg, ins, OP_MOVE);
2334 ins->dreg = mono_alloc_ireg (cfg);
2335 ins->sreg1 = in->dreg;
2336 MONO_ADD_INS (cfg->cbb, ins);
2337 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2341 cfg->param_area = MAX (cfg->param_area, 8);
2342 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2343 creg = mono_alloc_ireg (cfg);
2344 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2345 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2348 if (IS_SOFT_FLOAT) {
2349 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2350 ins->dreg = mono_alloc_ireg (cfg);
2351 ins->sreg1 = in->dreg;
2352 MONO_ADD_INS (cfg->cbb, ins);
2353 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2355 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2356 ins->dreg = mono_alloc_ireg (cfg);
2357 ins->sreg1 = in->dreg;
2358 MONO_ADD_INS (cfg->cbb, ins);
2359 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2363 cfg->param_area = MAX (cfg->param_area, 8);
2364 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2365 creg = mono_alloc_ireg (cfg);
2366 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2367 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2368 creg = mono_alloc_ireg (cfg);
2369 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2370 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2373 cfg->flags |= MONO_CFG_HAS_FPOUT;
2375 MONO_INST_NEW (cfg, ins, OP_MOVE);
2376 ins->dreg = mono_alloc_ireg (cfg);
2377 ins->sreg1 = in->dreg;
2378 MONO_ADD_INS (cfg->cbb, ins);
2380 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2383 case RegTypeStructByVal:
2384 case RegTypeGSharedVtInReg:
2385 case RegTypeGSharedVtOnStack:
2387 case RegTypeStructByAddr:
2388 case RegTypeStructByAddrOnStack:
2389 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2390 ins->opcode = OP_OUTARG_VT;
2391 ins->sreg1 = in->dreg;
2392 ins->klass = in->klass;
2393 ins->inst_p0 = call;
2394 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2395 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2396 mono_call_inst_add_outarg_vt (cfg, call, ins);
2397 MONO_ADD_INS (cfg->cbb, ins);
2400 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2401 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2402 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2403 if (t->type == MONO_TYPE_R8) {
2404 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2407 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2409 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2412 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2415 case RegTypeBaseGen:
2416 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2417 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? MONO_LVREG_LS (in->dreg) : MONO_LVREG_MS (in->dreg));
2418 MONO_INST_NEW (cfg, ins, OP_MOVE);
2419 ins->dreg = mono_alloc_ireg (cfg);
2420 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? MONO_LVREG_MS (in->dreg) : MONO_LVREG_LS (in->dreg);
2421 MONO_ADD_INS (cfg->cbb, ins);
2422 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2423 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2426 /* This should work for soft-float as well */
2428 cfg->param_area = MAX (cfg->param_area, 8);
2429 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2430 creg = mono_alloc_ireg (cfg);
2431 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2432 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2433 creg = mono_alloc_ireg (cfg);
2434 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2435 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2436 cfg->flags |= MONO_CFG_HAS_FPOUT;
2438 g_assert_not_reached ();
2442 int fdreg = mono_alloc_freg (cfg);
2444 if (ainfo->size == 8) {
2445 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2446 ins->sreg1 = in->dreg;
2448 MONO_ADD_INS (cfg->cbb, ins);
2450 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2455 * Mono's register allocator doesn't speak single-precision registers that
2456 * overlap double-precision registers (i.e. armhf). So we have to work around
2457 * the register allocator and load the value from memory manually.
2459 * So we create a variable for the float argument and an instruction to store
2460 * the argument into the variable. We then store the list of these arguments
2461 * in call->float_args. This list is then used by emit_float_args later to
2462 * pass the arguments in the various call opcodes.
2464 * This is not very nice, and we should really try to fix the allocator.
2467 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2469 /* Make sure the instruction isn't seen as pointless and removed.
2471 float_arg->flags |= MONO_INST_VOLATILE;
2473 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2475 /* We use the dreg to look up the instruction later. The hreg is used to
2476 * emit the instruction that loads the value into the FP reg.
2478 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2479 fad->vreg = float_arg->dreg;
2480 fad->hreg = ainfo->reg;
2482 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2485 call->used_iregs |= 1 << ainfo->reg;
2486 cfg->flags |= MONO_CFG_HAS_FPOUT;
2490 g_assert_not_reached ();
2494 /* Handle the case where there are no implicit arguments */
2495 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2496 emit_sig_cookie (cfg, call, cinfo);
2498 call->call_info = cinfo;
2499 call->stack_usage = cinfo->stack_usage;
2503 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2509 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2510 ins->dreg = mono_alloc_freg (cfg);
2511 ins->sreg1 = arg->dreg;
2512 MONO_ADD_INS (cfg->cbb, ins);
2513 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2516 g_assert_not_reached ();
2522 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2524 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2526 ArgInfo *ainfo = ins->inst_p1;
2527 int ovf_size = ainfo->vtsize;
2528 int doffset = ainfo->offset;
2529 int struct_size = ainfo->struct_size;
2530 int i, soffset, dreg, tmpreg;
2532 switch (ainfo->storage) {
2533 case RegTypeGSharedVtInReg:
2534 case RegTypeStructByAddr:
2536 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2538 case RegTypeGSharedVtOnStack:
2539 case RegTypeStructByAddrOnStack:
2540 /* Pass by addr on stack */
2541 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2544 for (i = 0; i < ainfo->nregs; ++i) {
2545 if (ainfo->esize == 4)
2546 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2548 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2549 load->dreg = mono_alloc_freg (cfg);
2550 load->inst_basereg = src->dreg;
2551 load->inst_offset = i * ainfo->esize;
2552 MONO_ADD_INS (cfg->cbb, load);
2554 if (ainfo->esize == 4) {
2557 /* See RegTypeFP in mono_arch_emit_call () */
2558 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2559 float_arg->flags |= MONO_INST_VOLATILE;
2560 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2562 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2563 fad->vreg = float_arg->dreg;
2564 fad->hreg = ainfo->reg + i;
2566 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2568 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2574 for (i = 0; i < ainfo->size; ++i) {
2575 dreg = mono_alloc_ireg (cfg);
2576 switch (struct_size) {
2578 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2581 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2584 tmpreg = mono_alloc_ireg (cfg);
2585 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2586 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2587 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2588 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2589 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2590 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2591 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2594 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2597 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2598 soffset += sizeof (gpointer);
2599 struct_size -= sizeof (gpointer);
2601 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2603 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2609 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2611 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2614 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2617 if (COMPILE_LLVM (cfg)) {
2618 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2620 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2621 ins->sreg1 = MONO_LVREG_LS (val->dreg);
2622 ins->sreg2 = MONO_LVREG_MS (val->dreg);
2623 MONO_ADD_INS (cfg->cbb, ins);
2628 case MONO_ARM_FPU_NONE:
2629 if (ret->type == MONO_TYPE_R8) {
2632 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2633 ins->dreg = cfg->ret->dreg;
2634 ins->sreg1 = val->dreg;
2635 MONO_ADD_INS (cfg->cbb, ins);
2638 if (ret->type == MONO_TYPE_R4) {
2639 /* Already converted to an int in method_to_ir () */
2640 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2644 case MONO_ARM_FPU_VFP:
2645 case MONO_ARM_FPU_VFP_HARD:
2646 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2649 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2650 ins->dreg = cfg->ret->dreg;
2651 ins->sreg1 = val->dreg;
2652 MONO_ADD_INS (cfg->cbb, ins);
2657 g_assert_not_reached ();
2661 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2664 #endif /* #ifndef DISABLE_JIT */
2667 mono_arch_is_inst_imm (gint64 imm)
2673 MonoMethodSignature *sig;
2676 MonoType **param_types;
2680 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2684 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2687 switch (cinfo->ret.storage) {
2689 case RegTypeGeneral:
2690 case RegTypeIRegPair:
2691 case RegTypeStructByAddr:
2702 for (i = 0; i < cinfo->nargs; ++i) {
2703 ArgInfo *ainfo = &cinfo->args [i];
2706 switch (ainfo->storage) {
2707 case RegTypeGeneral:
2708 case RegTypeIRegPair:
2709 case RegTypeBaseGen:
2713 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2716 case RegTypeStructByVal:
2717 if (ainfo->size == 0)
2718 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2720 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2721 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2729 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2730 for (i = 0; i < sig->param_count; ++i) {
2731 MonoType *t = sig->params [i];
2736 t = mini_get_underlying_type (t);
2759 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2761 ArchDynCallInfo *info;
2765 cinfo = get_call_info (NULL, sig);
2767 if (!dyn_call_supported (cinfo, sig)) {
2772 info = g_new0 (ArchDynCallInfo, 1);
2773 // FIXME: Preprocess the info to speed up start_dyn_call ()
2775 info->cinfo = cinfo;
2776 info->rtype = mini_get_underlying_type (sig->ret);
2777 info->param_types = g_new0 (MonoType*, sig->param_count);
2778 for (i = 0; i < sig->param_count; ++i)
2779 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2781 return (MonoDynCallInfo*)info;
2785 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2787 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2789 g_free (ainfo->cinfo);
2794 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2796 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2797 DynCallArgs *p = (DynCallArgs*)buf;
2798 int arg_index, greg, i, j, pindex;
2799 MonoMethodSignature *sig = dinfo->sig;
2801 g_assert (buf_len >= sizeof (DynCallArgs));
2811 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2812 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2817 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2818 p->regs [greg ++] = (mgreg_t)ret;
2820 for (i = pindex; i < sig->param_count; i++) {
2821 MonoType *t = dinfo->param_types [i];
2822 gpointer *arg = args [arg_index ++];
2823 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2826 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2828 } else if (ainfo->storage == RegTypeFP) {
2829 } else if (ainfo->storage == RegTypeBase) {
2830 slot = PARAM_REGS + (ainfo->offset / 4);
2831 } else if (ainfo->storage == RegTypeBaseGen) {
2832 /* slot + 1 is the first stack slot, so the code below will work */
2835 g_assert_not_reached ();
2839 p->regs [slot] = (mgreg_t)*arg;
2844 case MONO_TYPE_STRING:
2845 case MONO_TYPE_CLASS:
2846 case MONO_TYPE_ARRAY:
2847 case MONO_TYPE_SZARRAY:
2848 case MONO_TYPE_OBJECT:
2852 p->regs [slot] = (mgreg_t)*arg;
2855 p->regs [slot] = *(guint8*)arg;
2858 p->regs [slot] = *(gint8*)arg;
2861 p->regs [slot] = *(gint16*)arg;
2864 p->regs [slot] = *(guint16*)arg;
2867 p->regs [slot] = *(gint32*)arg;
2870 p->regs [slot] = *(guint32*)arg;
2874 p->regs [slot ++] = (mgreg_t)arg [0];
2875 p->regs [slot] = (mgreg_t)arg [1];
2878 if (ainfo->storage == RegTypeFP) {
2879 float f = *(float*)arg;
2880 p->fpregs [ainfo->reg / 2] = *(double*)&f;
2883 p->regs [slot] = *(mgreg_t*)arg;
2887 if (ainfo->storage == RegTypeFP) {
2888 p->fpregs [ainfo->reg / 2] = *(double*)arg;
2891 p->regs [slot ++] = (mgreg_t)arg [0];
2892 p->regs [slot] = (mgreg_t)arg [1];
2895 case MONO_TYPE_GENERICINST:
2896 if (MONO_TYPE_IS_REFERENCE (t)) {
2897 p->regs [slot] = (mgreg_t)*arg;
2900 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2901 MonoClass *klass = mono_class_from_mono_type (t);
2902 guint8 *nullable_buf;
2905 size = mono_class_value_size (klass, NULL);
2906 nullable_buf = g_alloca (size);
2907 g_assert (nullable_buf);
2909 /* The argument pointed to by arg is either a boxed vtype or null */
2910 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2912 arg = (gpointer*)nullable_buf;
2918 case MONO_TYPE_VALUETYPE:
2919 g_assert (ainfo->storage == RegTypeStructByVal);
2921 if (ainfo->size == 0)
2922 slot = PARAM_REGS + (ainfo->offset / 4);
2926 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2927 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2930 g_assert_not_reached ();
2936 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2938 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2939 DynCallArgs *p = (DynCallArgs*)buf;
2940 MonoType *ptype = ainfo->rtype;
2941 guint8 *ret = p->ret;
2942 mgreg_t res = p->res;
2943 mgreg_t res2 = p->res2;
2945 switch (ptype->type) {
2946 case MONO_TYPE_VOID:
2947 *(gpointer*)ret = NULL;
2949 case MONO_TYPE_STRING:
2950 case MONO_TYPE_CLASS:
2951 case MONO_TYPE_ARRAY:
2952 case MONO_TYPE_SZARRAY:
2953 case MONO_TYPE_OBJECT:
2957 *(gpointer*)ret = (gpointer)res;
2963 *(guint8*)ret = res;
2966 *(gint16*)ret = res;
2969 *(guint16*)ret = res;
2972 *(gint32*)ret = res;
2975 *(guint32*)ret = res;
2979 /* This handles endianness as well */
2980 ((gint32*)ret) [0] = res;
2981 ((gint32*)ret) [1] = res2;
2983 case MONO_TYPE_GENERICINST:
2984 if (MONO_TYPE_IS_REFERENCE (ptype)) {
2985 *(gpointer*)ret = (gpointer)res;
2990 case MONO_TYPE_VALUETYPE:
2991 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
2997 *(float*)ret = *(float*)&p->fpregs [0];
2999 *(float*)ret = *(float*)&res;
3001 case MONO_TYPE_R8: {
3005 if (IS_HARD_FLOAT) {
3006 *(double*)ret = p->fpregs [0];
3011 *(double*)ret = *(double*)®s;
3016 g_assert_not_reached ();
3023 * Allow tracing to work with this interface (with an optional argument)
3027 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
3031 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3032 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
3033 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
3034 code = emit_call_reg (code, ARMREG_R2);
3048 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3051 int save_mode = SAVE_NONE;
3053 MonoMethod *method = cfg->method;
3054 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
3055 int rtype = ret_type->type;
3056 int save_offset = cfg->param_area;
3060 offset = code - cfg->native_code;
3061 /* we need about 16 instructions */
3062 if (offset > (cfg->code_size - 16 * 4)) {
3063 cfg->code_size *= 2;
3064 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3065 code = cfg->native_code + offset;
3068 case MONO_TYPE_VOID:
3069 /* special case string .ctor icall */
3070 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3071 save_mode = SAVE_ONE;
3073 save_mode = SAVE_NONE;
3077 save_mode = SAVE_TWO;
3081 save_mode = SAVE_ONE_FP;
3083 save_mode = SAVE_ONE;
3087 save_mode = SAVE_TWO_FP;
3089 save_mode = SAVE_TWO;
3091 case MONO_TYPE_GENERICINST:
3092 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3093 save_mode = SAVE_ONE;
3097 case MONO_TYPE_VALUETYPE:
3098 save_mode = SAVE_STRUCT;
3101 save_mode = SAVE_ONE;
3105 switch (save_mode) {
3107 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3108 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3109 if (enable_arguments) {
3110 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3111 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3115 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3116 if (enable_arguments) {
3117 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3121 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3122 if (enable_arguments) {
3123 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3127 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3128 if (enable_arguments) {
3129 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3133 if (enable_arguments) {
3134 /* FIXME: get the actual address */
3135 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3143 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3144 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3145 code = emit_call_reg (code, ARMREG_IP);
3147 switch (save_mode) {
3149 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3150 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3153 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3156 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3159 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3170 * The immediate field for cond branches is big enough for all reasonable methods
3172 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3173 if (0 && ins->inst_true_bb->native_offset) { \
3174 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3176 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3177 ARM_B_COND (code, (condcode), 0); \
3180 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3182 /* emit an exception if condition is fail
3184 * We assign the extra code used to throw the implicit exceptions
3185 * to cfg->bb_exit as far as the big branch handling is concerned
3187 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3189 mono_add_patch_info (cfg, code - cfg->native_code, \
3190 MONO_PATCH_INFO_EXC, exc_name); \
3191 ARM_BL_COND (code, (condcode), 0); \
3194 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3197 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3202 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3206 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3207 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3209 switch (ins->opcode) {
3212 /* Already done by an arch-independent pass */
3214 case OP_LOAD_MEMBASE:
3215 case OP_LOADI4_MEMBASE:
3217 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3218 * OP_LOAD_MEMBASE offset(basereg), reg
3220 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3221 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3222 ins->inst_basereg == last_ins->inst_destbasereg &&
3223 ins->inst_offset == last_ins->inst_offset) {
3224 if (ins->dreg == last_ins->sreg1) {
3225 MONO_DELETE_INS (bb, ins);
3228 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3229 ins->opcode = OP_MOVE;
3230 ins->sreg1 = last_ins->sreg1;
3234 * Note: reg1 must be different from the basereg in the second load
3235 * OP_LOAD_MEMBASE offset(basereg), reg1
3236 * OP_LOAD_MEMBASE offset(basereg), reg2
3238 * OP_LOAD_MEMBASE offset(basereg), reg1
3239 * OP_MOVE reg1, reg2
3241 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3242 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3243 ins->inst_basereg != last_ins->dreg &&
3244 ins->inst_basereg == last_ins->inst_basereg &&
3245 ins->inst_offset == last_ins->inst_offset) {
3247 if (ins->dreg == last_ins->dreg) {
3248 MONO_DELETE_INS (bb, ins);
3251 ins->opcode = OP_MOVE;
3252 ins->sreg1 = last_ins->dreg;
3255 //g_assert_not_reached ();
3259 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3260 * OP_LOAD_MEMBASE offset(basereg), reg
3262 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3263 * OP_ICONST reg, imm
3265 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3266 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3267 ins->inst_basereg == last_ins->inst_destbasereg &&
3268 ins->inst_offset == last_ins->inst_offset) {
3269 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3270 ins->opcode = OP_ICONST;
3271 ins->inst_c0 = last_ins->inst_imm;
3272 g_assert_not_reached (); // check this rule
3276 case OP_LOADU1_MEMBASE:
3277 case OP_LOADI1_MEMBASE:
3278 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3279 ins->inst_basereg == last_ins->inst_destbasereg &&
3280 ins->inst_offset == last_ins->inst_offset) {
3281 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3282 ins->sreg1 = last_ins->sreg1;
3285 case OP_LOADU2_MEMBASE:
3286 case OP_LOADI2_MEMBASE:
3287 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3288 ins->inst_basereg == last_ins->inst_destbasereg &&
3289 ins->inst_offset == last_ins->inst_offset) {
3290 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3291 ins->sreg1 = last_ins->sreg1;
3295 ins->opcode = OP_MOVE;
3299 if (ins->dreg == ins->sreg1) {
3300 MONO_DELETE_INS (bb, ins);
3304 * OP_MOVE sreg, dreg
3305 * OP_MOVE dreg, sreg
3307 if (last_ins && last_ins->opcode == OP_MOVE &&
3308 ins->sreg1 == last_ins->dreg &&
3309 ins->dreg == last_ins->sreg1) {
3310 MONO_DELETE_INS (bb, ins);
3319 * the branch_cc_table should maintain the order of these
3333 branch_cc_table [] = {
3347 #define ADD_NEW_INS(cfg,dest,op) do { \
3348 MONO_INST_NEW ((cfg), (dest), (op)); \
3349 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3353 map_to_reg_reg_op (int op)
3362 case OP_COMPARE_IMM:
3364 case OP_ICOMPARE_IMM:
3378 case OP_LOAD_MEMBASE:
3379 return OP_LOAD_MEMINDEX;
3380 case OP_LOADI4_MEMBASE:
3381 return OP_LOADI4_MEMINDEX;
3382 case OP_LOADU4_MEMBASE:
3383 return OP_LOADU4_MEMINDEX;
3384 case OP_LOADU1_MEMBASE:
3385 return OP_LOADU1_MEMINDEX;
3386 case OP_LOADI2_MEMBASE:
3387 return OP_LOADI2_MEMINDEX;
3388 case OP_LOADU2_MEMBASE:
3389 return OP_LOADU2_MEMINDEX;
3390 case OP_LOADI1_MEMBASE:
3391 return OP_LOADI1_MEMINDEX;
3392 case OP_STOREI1_MEMBASE_REG:
3393 return OP_STOREI1_MEMINDEX;
3394 case OP_STOREI2_MEMBASE_REG:
3395 return OP_STOREI2_MEMINDEX;
3396 case OP_STOREI4_MEMBASE_REG:
3397 return OP_STOREI4_MEMINDEX;
3398 case OP_STORE_MEMBASE_REG:
3399 return OP_STORE_MEMINDEX;
3400 case OP_STORER4_MEMBASE_REG:
3401 return OP_STORER4_MEMINDEX;
3402 case OP_STORER8_MEMBASE_REG:
3403 return OP_STORER8_MEMINDEX;
3404 case OP_STORE_MEMBASE_IMM:
3405 return OP_STORE_MEMBASE_REG;
3406 case OP_STOREI1_MEMBASE_IMM:
3407 return OP_STOREI1_MEMBASE_REG;
3408 case OP_STOREI2_MEMBASE_IMM:
3409 return OP_STOREI2_MEMBASE_REG;
3410 case OP_STOREI4_MEMBASE_IMM:
3411 return OP_STOREI4_MEMBASE_REG;
3413 g_assert_not_reached ();
3417 * Remove from the instruction list the instructions that can't be
3418 * represented with very simple instructions with no register
3422 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3424 MonoInst *ins, *temp, *last_ins = NULL;
3425 int rot_amount, imm8, low_imm;
3427 MONO_BB_FOR_EACH_INS (bb, ins) {
3429 switch (ins->opcode) {
3433 case OP_COMPARE_IMM:
3434 case OP_ICOMPARE_IMM:
3448 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3449 int opcode2 = mono_op_imm_to_op (ins->opcode);
3450 ADD_NEW_INS (cfg, temp, OP_ICONST);
3451 temp->inst_c0 = ins->inst_imm;
3452 temp->dreg = mono_alloc_ireg (cfg);
3453 ins->sreg2 = temp->dreg;
3455 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3456 ins->opcode = opcode2;
3458 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3464 if (ins->inst_imm == 1) {
3465 ins->opcode = OP_MOVE;
3468 if (ins->inst_imm == 0) {
3469 ins->opcode = OP_ICONST;
3473 imm8 = mono_is_power_of_two (ins->inst_imm);
3475 ins->opcode = OP_SHL_IMM;
3476 ins->inst_imm = imm8;
3479 ADD_NEW_INS (cfg, temp, OP_ICONST);
3480 temp->inst_c0 = ins->inst_imm;
3481 temp->dreg = mono_alloc_ireg (cfg);
3482 ins->sreg2 = temp->dreg;
3483 ins->opcode = OP_IMUL;
3489 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3490 /* ARM sets the C flag to 1 if there was _no_ overflow */
3491 ins->next->opcode = OP_COND_EXC_NC;
3494 case OP_IDIV_UN_IMM:
3496 case OP_IREM_UN_IMM: {
3497 int opcode2 = mono_op_imm_to_op (ins->opcode);
3498 ADD_NEW_INS (cfg, temp, OP_ICONST);
3499 temp->inst_c0 = ins->inst_imm;
3500 temp->dreg = mono_alloc_ireg (cfg);
3501 ins->sreg2 = temp->dreg;
3503 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3504 ins->opcode = opcode2;
3507 case OP_LOCALLOC_IMM:
3508 ADD_NEW_INS (cfg, temp, OP_ICONST);
3509 temp->inst_c0 = ins->inst_imm;
3510 temp->dreg = mono_alloc_ireg (cfg);
3511 ins->sreg1 = temp->dreg;
3512 ins->opcode = OP_LOCALLOC;
3514 case OP_LOAD_MEMBASE:
3515 case OP_LOADI4_MEMBASE:
3516 case OP_LOADU4_MEMBASE:
3517 case OP_LOADU1_MEMBASE:
3518 /* we can do two things: load the immed in a register
3519 * and use an indexed load, or see if the immed can be
3520 * represented as an ad_imm + a load with a smaller offset
3521 * that fits. We just do the first for now, optimize later.
3523 if (arm_is_imm12 (ins->inst_offset))
3525 ADD_NEW_INS (cfg, temp, OP_ICONST);
3526 temp->inst_c0 = ins->inst_offset;
3527 temp->dreg = mono_alloc_ireg (cfg);
3528 ins->sreg2 = temp->dreg;
3529 ins->opcode = map_to_reg_reg_op (ins->opcode);
3531 case OP_LOADI2_MEMBASE:
3532 case OP_LOADU2_MEMBASE:
3533 case OP_LOADI1_MEMBASE:
3534 if (arm_is_imm8 (ins->inst_offset))
3536 ADD_NEW_INS (cfg, temp, OP_ICONST);
3537 temp->inst_c0 = ins->inst_offset;
3538 temp->dreg = mono_alloc_ireg (cfg);
3539 ins->sreg2 = temp->dreg;
3540 ins->opcode = map_to_reg_reg_op (ins->opcode);
3542 case OP_LOADR4_MEMBASE:
3543 case OP_LOADR8_MEMBASE:
3544 if (arm_is_fpimm8 (ins->inst_offset))
3546 low_imm = ins->inst_offset & 0x1ff;
3547 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3548 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3549 temp->inst_imm = ins->inst_offset & ~0x1ff;
3550 temp->sreg1 = ins->inst_basereg;
3551 temp->dreg = mono_alloc_ireg (cfg);
3552 ins->inst_basereg = temp->dreg;
3553 ins->inst_offset = low_imm;
3557 ADD_NEW_INS (cfg, temp, OP_ICONST);
3558 temp->inst_c0 = ins->inst_offset;
3559 temp->dreg = mono_alloc_ireg (cfg);
3561 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3562 add_ins->sreg1 = ins->inst_basereg;
3563 add_ins->sreg2 = temp->dreg;
3564 add_ins->dreg = mono_alloc_ireg (cfg);
3566 ins->inst_basereg = add_ins->dreg;
3567 ins->inst_offset = 0;
3570 case OP_STORE_MEMBASE_REG:
3571 case OP_STOREI4_MEMBASE_REG:
3572 case OP_STOREI1_MEMBASE_REG:
3573 if (arm_is_imm12 (ins->inst_offset))
3575 ADD_NEW_INS (cfg, temp, OP_ICONST);
3576 temp->inst_c0 = ins->inst_offset;
3577 temp->dreg = mono_alloc_ireg (cfg);
3578 ins->sreg2 = temp->dreg;
3579 ins->opcode = map_to_reg_reg_op (ins->opcode);
3581 case OP_STOREI2_MEMBASE_REG:
3582 if (arm_is_imm8 (ins->inst_offset))
3584 ADD_NEW_INS (cfg, temp, OP_ICONST);
3585 temp->inst_c0 = ins->inst_offset;
3586 temp->dreg = mono_alloc_ireg (cfg);
3587 ins->sreg2 = temp->dreg;
3588 ins->opcode = map_to_reg_reg_op (ins->opcode);
3590 case OP_STORER4_MEMBASE_REG:
3591 case OP_STORER8_MEMBASE_REG:
3592 if (arm_is_fpimm8 (ins->inst_offset))
3594 low_imm = ins->inst_offset & 0x1ff;
3595 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3596 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3597 temp->inst_imm = ins->inst_offset & ~0x1ff;
3598 temp->sreg1 = ins->inst_destbasereg;
3599 temp->dreg = mono_alloc_ireg (cfg);
3600 ins->inst_destbasereg = temp->dreg;
3601 ins->inst_offset = low_imm;
3605 ADD_NEW_INS (cfg, temp, OP_ICONST);
3606 temp->inst_c0 = ins->inst_offset;
3607 temp->dreg = mono_alloc_ireg (cfg);
3609 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3610 add_ins->sreg1 = ins->inst_destbasereg;
3611 add_ins->sreg2 = temp->dreg;
3612 add_ins->dreg = mono_alloc_ireg (cfg);
3614 ins->inst_destbasereg = add_ins->dreg;
3615 ins->inst_offset = 0;
3618 case OP_STORE_MEMBASE_IMM:
3619 case OP_STOREI1_MEMBASE_IMM:
3620 case OP_STOREI2_MEMBASE_IMM:
3621 case OP_STOREI4_MEMBASE_IMM:
3622 ADD_NEW_INS (cfg, temp, OP_ICONST);
3623 temp->inst_c0 = ins->inst_imm;
3624 temp->dreg = mono_alloc_ireg (cfg);
3625 ins->sreg1 = temp->dreg;
3626 ins->opcode = map_to_reg_reg_op (ins->opcode);
3628 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3631 gboolean swap = FALSE;
3635 /* Optimized away */
3640 /* Some fp compares require swapped operands */
3641 switch (ins->next->opcode) {
3643 ins->next->opcode = OP_FBLT;
3647 ins->next->opcode = OP_FBLT_UN;
3651 ins->next->opcode = OP_FBGE;
3655 ins->next->opcode = OP_FBGE_UN;
3663 ins->sreg1 = ins->sreg2;
3672 bb->last_ins = last_ins;
3673 bb->max_vreg = cfg->next_vreg;
3677 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3681 if (long_ins->opcode == OP_LNEG) {
3683 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), 0);
3684 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
3690 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3692 /* sreg is a float, dreg is an integer reg */
3694 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3696 ARM_TOSIZD (code, vfp_scratch1, sreg);
3698 ARM_TOUIZD (code, vfp_scratch1, sreg);
3699 ARM_FMRS (code, dreg, vfp_scratch1);
3700 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3704 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3705 else if (size == 2) {
3706 ARM_SHL_IMM (code, dreg, dreg, 16);
3707 ARM_SHR_IMM (code, dreg, dreg, 16);
3711 ARM_SHL_IMM (code, dreg, dreg, 24);
3712 ARM_SAR_IMM (code, dreg, dreg, 24);
3713 } else if (size == 2) {
3714 ARM_SHL_IMM (code, dreg, dreg, 16);
3715 ARM_SAR_IMM (code, dreg, dreg, 16);
3722 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3724 /* sreg is a float, dreg is an integer reg */
3726 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3728 ARM_TOSIZS (code, vfp_scratch1, sreg);
3730 ARM_TOUIZS (code, vfp_scratch1, sreg);
3731 ARM_FMRS (code, dreg, vfp_scratch1);
3732 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3736 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3737 else if (size == 2) {
3738 ARM_SHL_IMM (code, dreg, dreg, 16);
3739 ARM_SHR_IMM (code, dreg, dreg, 16);
3743 ARM_SHL_IMM (code, dreg, dreg, 24);
3744 ARM_SAR_IMM (code, dreg, dreg, 24);
3745 } else if (size == 2) {
3746 ARM_SHL_IMM (code, dreg, dreg, 16);
3747 ARM_SAR_IMM (code, dreg, dreg, 16);
3753 #endif /* #ifndef DISABLE_JIT */
3755 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3758 emit_thunk (guint8 *code, gconstpointer target)
3762 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3763 if (thumb_supported)
3764 ARM_BX (code, ARMREG_IP);
3766 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3767 *(guint32*)code = (guint32)target;
3769 mono_arch_flush_icache (p, code - p);
3773 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3775 MonoJitInfo *ji = NULL;
3776 MonoThunkJitInfo *info;
3779 guint8 *orig_target;
3780 guint8 *target_thunk;
3783 domain = mono_domain_get ();
3787 * This can be called multiple times during JITting,
3788 * save the current position in cfg->arch to avoid
3789 * doing a O(n^2) search.
3791 if (!cfg->arch.thunks) {
3792 cfg->arch.thunks = cfg->thunks;
3793 cfg->arch.thunks_size = cfg->thunk_area;
3795 thunks = cfg->arch.thunks;
3796 thunks_size = cfg->arch.thunks_size;
3798 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3799 g_assert_not_reached ();
3802 g_assert (*(guint32*)thunks == 0);
3803 emit_thunk (thunks, target);
3804 arm_patch (code, thunks);
3806 cfg->arch.thunks += THUNK_SIZE;
3807 cfg->arch.thunks_size -= THUNK_SIZE;
3809 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3811 info = mono_jit_info_get_thunk_info (ji);
3814 thunks = (guint8*)ji->code_start + info->thunks_offset;
3815 thunks_size = info->thunks_size;
3817 orig_target = mono_arch_get_call_target (code + 4);
3819 mono_mini_arch_lock ();
3821 target_thunk = NULL;
3822 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3823 /* The call already points to a thunk, because of trampolines etc. */
3824 target_thunk = orig_target;
3826 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3827 if (((guint32*)p) [0] == 0) {
3831 } else if (((guint32*)p) [2] == (guint32)target) {
3832 /* Thunk already points to target */
3839 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3841 if (!target_thunk) {
3842 mono_mini_arch_unlock ();
3843 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3844 g_assert_not_reached ();
3847 emit_thunk (target_thunk, target);
3848 arm_patch (code, target_thunk);
3849 mono_arch_flush_icache (code, 4);
3851 mono_mini_arch_unlock ();
3856 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3858 guint32 *code32 = (void*)code;
3859 guint32 ins = *code32;
3860 guint32 prim = (ins >> 25) & 7;
3861 guint32 tval = GPOINTER_TO_UINT (target);
3863 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3864 if (prim == 5) { /* 101b */
3865 /* the diff starts 8 bytes from the branch opcode */
3866 gint diff = target - code - 8;
3868 gint tmask = 0xffffffff;
3869 if (tval & 1) { /* entering thumb mode */
3870 diff = target - 1 - code - 8;
3871 g_assert (thumb_supported);
3872 tbits = 0xf << 28; /* bl->blx bit pattern */
3873 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3874 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3878 tmask = ~(1 << 24); /* clear the link bit */
3879 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3884 if (diff <= 33554431) {
3886 ins = (ins & 0xff000000) | diff;
3888 *code32 = ins | tbits;
3892 /* diff between 0 and -33554432 */
3893 if (diff >= -33554432) {
3895 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3897 *code32 = ins | tbits;
3902 handle_thunk (cfg, domain, code, target);
3907 * The alternative call sequences looks like this:
3909 * ldr ip, [pc] // loads the address constant
3910 * b 1f // jumps around the constant
3911 * address constant embedded in the code
3916 * There are two cases for patching:
3917 * a) at the end of method emission: in this case code points to the start
3918 * of the call sequence
3919 * b) during runtime patching of the call site: in this case code points
3920 * to the mov pc, ip instruction
3922 * We have to handle also the thunk jump code sequence:
3926 * address constant // execution never reaches here
3928 if ((ins & 0x0ffffff0) == 0x12fff10) {
3929 /* Branch and exchange: the address is constructed in a reg
3930 * We can patch BX when the code sequence is the following:
3931 * ldr ip, [pc, #0] ; 0x8
3938 guint8 *emit = (guint8*)ccode;
3939 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3941 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3942 ARM_BX (emit, ARMREG_IP);
3944 /*patching from magic trampoline*/
3945 if (ins == ccode [3]) {
3946 g_assert (code32 [-4] == ccode [0]);
3947 g_assert (code32 [-3] == ccode [1]);
3948 g_assert (code32 [-1] == ccode [2]);
3949 code32 [-2] = (guint32)target;
3952 /*patching from JIT*/
3953 if (ins == ccode [0]) {
3954 g_assert (code32 [1] == ccode [1]);
3955 g_assert (code32 [3] == ccode [2]);
3956 g_assert (code32 [4] == ccode [3]);
3957 code32 [2] = (guint32)target;
3960 g_assert_not_reached ();
3961 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3969 guint8 *emit = (guint8*)ccode;
3970 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3972 ARM_BLX_REG (emit, ARMREG_IP);
3974 g_assert (code32 [-3] == ccode [0]);
3975 g_assert (code32 [-2] == ccode [1]);
3976 g_assert (code32 [0] == ccode [2]);
3978 code32 [-1] = (guint32)target;
3981 guint32 *tmp = ccode;
3982 guint8 *emit = (guint8*)tmp;
3983 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3984 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3985 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3986 ARM_BX (emit, ARMREG_IP);
3987 if (ins == ccode [2]) {
3988 g_assert_not_reached (); // should be -2 ...
3989 code32 [-1] = (guint32)target;
3992 if (ins == ccode [0]) {
3993 /* handles both thunk jump code and the far call sequence */
3994 code32 [2] = (guint32)target;
3997 g_assert_not_reached ();
3999 // g_print ("patched with 0x%08x\n", ins);
4003 arm_patch (guchar *code, const guchar *target)
4005 arm_patch_general (NULL, NULL, code, target);
4009 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
4010 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
4011 * to be used with the emit macros.
4012 * Return -1 otherwise.
4015 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
4018 for (i = 0; i < 31; i+= 2) {
4019 res = (val << (32 - i)) | (val >> i);
4022 *rot_amount = i? 32 - i: 0;
4029 * Emits in code a sequence of instructions that load the value 'val'
4030 * into the dreg register. Uses at most 4 instructions.
4033 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
4035 int imm8, rot_amount;
4037 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4038 /* skip the constant pool */
4044 if (mini_get_debug_options()->single_imm_size && v7_supported) {
4045 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4046 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4050 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4051 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4052 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4053 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4056 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4058 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4062 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4064 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4066 if (val & 0xFF0000) {
4067 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4069 if (val & 0xFF000000) {
4070 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4072 } else if (val & 0xFF00) {
4073 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4074 if (val & 0xFF0000) {
4075 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4077 if (val & 0xFF000000) {
4078 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4080 } else if (val & 0xFF0000) {
4081 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4082 if (val & 0xFF000000) {
4083 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4086 //g_assert_not_reached ();
4092 mono_arm_thumb_supported (void)
4094 return thumb_supported;
4100 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4105 call = (MonoCallInst*)ins;
4106 cinfo = call->call_info;
4108 switch (cinfo->ret.storage) {
4109 case RegTypeStructByVal:
4111 MonoInst *loc = cfg->arch.vret_addr_loc;
4114 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
4115 /* The JIT treats this as a normal call */
4119 /* Load the destination address */
4120 g_assert (loc && loc->opcode == OP_REGOFFSET);
4122 if (arm_is_imm12 (loc->inst_offset)) {
4123 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4125 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4126 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4129 if (cinfo->ret.storage == RegTypeStructByVal) {
4130 int rsize = cinfo->ret.struct_size;
4132 for (i = 0; i < cinfo->ret.nregs; ++i) {
4133 g_assert (rsize >= 0);
4138 ARM_STRB_IMM (code, i, ARMREG_LR, i * 4);
4141 ARM_STRH_IMM (code, i, ARMREG_LR, i * 4);
4144 ARM_STR_IMM (code, i, ARMREG_LR, i * 4);
4150 for (i = 0; i < cinfo->ret.nregs; ++i) {
4151 if (cinfo->ret.esize == 4)
4152 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4154 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4163 switch (ins->opcode) {
4166 case OP_FCALL_MEMBASE:
4168 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4169 if (sig_ret->type == MONO_TYPE_R4) {
4170 if (IS_HARD_FLOAT) {
4171 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4173 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4174 ARM_CVTS (code, ins->dreg, ins->dreg);
4177 if (IS_HARD_FLOAT) {
4178 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4180 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4187 case OP_RCALL_MEMBASE: {
4192 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4193 g_assert (sig_ret->type == MONO_TYPE_R4);
4194 if (IS_HARD_FLOAT) {
4195 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4197 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4198 ARM_CPYS (code, ins->dreg, ins->dreg);
4210 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4215 guint8 *code = cfg->native_code + cfg->code_len;
4216 MonoInst *last_ins = NULL;
4217 guint last_offset = 0;
4219 int imm8, rot_amount;
4221 /* we don't align basic blocks of loops on arm */
4223 if (cfg->verbose_level > 2)
4224 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4226 cpos = bb->max_offset;
4228 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4229 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4230 //g_assert (!mono_compile_aot);
4233 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4234 /* this is not thread save, but good enough */
4235 /* fixme: howto handle overflows? */
4236 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4239 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4240 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4241 (gpointer)"mono_break");
4242 code = emit_call_seq (cfg, code);
4245 MONO_BB_FOR_EACH_INS (bb, ins) {
4246 offset = code - cfg->native_code;
4248 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4250 if (offset > (cfg->code_size - max_len - 16)) {
4251 cfg->code_size *= 2;
4252 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4253 code = cfg->native_code + offset;
4255 // if (ins->cil_code)
4256 // g_print ("cil code\n");
4257 mono_debug_record_line_number (cfg, ins, offset);
4259 switch (ins->opcode) {
4260 case OP_MEMORY_BARRIER:
4262 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4263 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4267 code = mono_arm_emit_tls_get (cfg, code, ins->dreg, ins->inst_offset);
4269 case OP_TLS_GET_REG:
4270 code = mono_arm_emit_tls_get_reg (cfg, code, ins->dreg, ins->sreg1);
4273 code = mono_arm_emit_tls_set (cfg, code, ins->sreg1, ins->inst_offset);
4275 case OP_TLS_SET_REG:
4276 code = mono_arm_emit_tls_set_reg (cfg, code, ins->sreg1, ins->sreg2);
4278 case OP_ATOMIC_EXCHANGE_I4:
4279 case OP_ATOMIC_CAS_I4:
4280 case OP_ATOMIC_ADD_I4: {
4284 g_assert (v7_supported);
4287 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4289 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4291 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4295 g_assert (cfg->arch.atomic_tmp_offset != -1);
4296 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4298 switch (ins->opcode) {
4299 case OP_ATOMIC_EXCHANGE_I4:
4301 ARM_DMB (code, ARM_DMB_SY);
4302 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4303 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4304 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4306 ARM_B_COND (code, ARMCOND_NE, 0);
4307 arm_patch (buf [1], buf [0]);
4309 case OP_ATOMIC_CAS_I4:
4310 ARM_DMB (code, ARM_DMB_SY);
4312 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4313 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4315 ARM_B_COND (code, ARMCOND_NE, 0);
4316 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4317 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4319 ARM_B_COND (code, ARMCOND_NE, 0);
4320 arm_patch (buf [2], buf [0]);
4321 arm_patch (buf [1], code);
4323 case OP_ATOMIC_ADD_I4:
4325 ARM_DMB (code, ARM_DMB_SY);
4326 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4327 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4328 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4329 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4331 ARM_B_COND (code, ARMCOND_NE, 0);
4332 arm_patch (buf [1], buf [0]);
4335 g_assert_not_reached ();
4338 ARM_DMB (code, ARM_DMB_SY);
4339 if (tmpreg != ins->dreg)
4340 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4341 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4344 case OP_ATOMIC_LOAD_I1:
4345 case OP_ATOMIC_LOAD_U1:
4346 case OP_ATOMIC_LOAD_I2:
4347 case OP_ATOMIC_LOAD_U2:
4348 case OP_ATOMIC_LOAD_I4:
4349 case OP_ATOMIC_LOAD_U4:
4350 case OP_ATOMIC_LOAD_R4:
4351 case OP_ATOMIC_LOAD_R8: {
4352 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4353 ARM_DMB (code, ARM_DMB_SY);
4355 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4357 switch (ins->opcode) {
4358 case OP_ATOMIC_LOAD_I1:
4359 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4361 case OP_ATOMIC_LOAD_U1:
4362 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4364 case OP_ATOMIC_LOAD_I2:
4365 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4367 case OP_ATOMIC_LOAD_U2:
4368 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4370 case OP_ATOMIC_LOAD_I4:
4371 case OP_ATOMIC_LOAD_U4:
4372 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4374 case OP_ATOMIC_LOAD_R4:
4376 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4377 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4379 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4380 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4381 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4382 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4383 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4386 case OP_ATOMIC_LOAD_R8:
4387 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4388 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4392 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4393 ARM_DMB (code, ARM_DMB_SY);
4396 case OP_ATOMIC_STORE_I1:
4397 case OP_ATOMIC_STORE_U1:
4398 case OP_ATOMIC_STORE_I2:
4399 case OP_ATOMIC_STORE_U2:
4400 case OP_ATOMIC_STORE_I4:
4401 case OP_ATOMIC_STORE_U4:
4402 case OP_ATOMIC_STORE_R4:
4403 case OP_ATOMIC_STORE_R8: {
4404 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4405 ARM_DMB (code, ARM_DMB_SY);
4407 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4409 switch (ins->opcode) {
4410 case OP_ATOMIC_STORE_I1:
4411 case OP_ATOMIC_STORE_U1:
4412 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4414 case OP_ATOMIC_STORE_I2:
4415 case OP_ATOMIC_STORE_U2:
4416 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4418 case OP_ATOMIC_STORE_I4:
4419 case OP_ATOMIC_STORE_U4:
4420 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4422 case OP_ATOMIC_STORE_R4:
4424 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4425 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4427 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4428 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4429 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4430 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4431 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4434 case OP_ATOMIC_STORE_R8:
4435 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4436 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4440 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4441 ARM_DMB (code, ARM_DMB_SY);
4445 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4446 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
4449 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4450 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
4452 case OP_STOREI1_MEMBASE_IMM:
4453 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4454 g_assert (arm_is_imm12 (ins->inst_offset));
4455 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4457 case OP_STOREI2_MEMBASE_IMM:
4458 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4459 g_assert (arm_is_imm8 (ins->inst_offset));
4460 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4462 case OP_STORE_MEMBASE_IMM:
4463 case OP_STOREI4_MEMBASE_IMM:
4464 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4465 g_assert (arm_is_imm12 (ins->inst_offset));
4466 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4468 case OP_STOREI1_MEMBASE_REG:
4469 g_assert (arm_is_imm12 (ins->inst_offset));
4470 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4472 case OP_STOREI2_MEMBASE_REG:
4473 g_assert (arm_is_imm8 (ins->inst_offset));
4474 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4476 case OP_STORE_MEMBASE_REG:
4477 case OP_STOREI4_MEMBASE_REG:
4478 /* this case is special, since it happens for spill code after lowering has been called */
4479 if (arm_is_imm12 (ins->inst_offset)) {
4480 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4482 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4483 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4486 case OP_STOREI1_MEMINDEX:
4487 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4489 case OP_STOREI2_MEMINDEX:
4490 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4492 case OP_STORE_MEMINDEX:
4493 case OP_STOREI4_MEMINDEX:
4494 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4497 g_assert_not_reached ();
4499 case OP_LOAD_MEMINDEX:
4500 case OP_LOADI4_MEMINDEX:
4501 case OP_LOADU4_MEMINDEX:
4502 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4504 case OP_LOADI1_MEMINDEX:
4505 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4507 case OP_LOADU1_MEMINDEX:
4508 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4510 case OP_LOADI2_MEMINDEX:
4511 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4513 case OP_LOADU2_MEMINDEX:
4514 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4516 case OP_LOAD_MEMBASE:
4517 case OP_LOADI4_MEMBASE:
4518 case OP_LOADU4_MEMBASE:
4519 /* this case is special, since it happens for spill code after lowering has been called */
4520 if (arm_is_imm12 (ins->inst_offset)) {
4521 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4523 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4524 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4527 case OP_LOADI1_MEMBASE:
4528 g_assert (arm_is_imm8 (ins->inst_offset));
4529 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4531 case OP_LOADU1_MEMBASE:
4532 g_assert (arm_is_imm12 (ins->inst_offset));
4533 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4535 case OP_LOADU2_MEMBASE:
4536 g_assert (arm_is_imm8 (ins->inst_offset));
4537 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4539 case OP_LOADI2_MEMBASE:
4540 g_assert (arm_is_imm8 (ins->inst_offset));
4541 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4543 case OP_ICONV_TO_I1:
4544 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4545 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4547 case OP_ICONV_TO_I2:
4548 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4549 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4551 case OP_ICONV_TO_U1:
4552 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4554 case OP_ICONV_TO_U2:
4555 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4556 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4560 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4562 case OP_COMPARE_IMM:
4563 case OP_ICOMPARE_IMM:
4564 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4565 g_assert (imm8 >= 0);
4566 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4570 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4571 * So instead of emitting a trap, we emit a call a C function and place a
4574 //*(int*)code = 0xef9f0001;
4577 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4578 (gpointer)"mono_break");
4579 code = emit_call_seq (cfg, code);
4581 case OP_RELAXED_NOP:
4586 case OP_DUMMY_STORE:
4587 case OP_DUMMY_ICONST:
4588 case OP_DUMMY_R8CONST:
4589 case OP_NOT_REACHED:
4592 case OP_IL_SEQ_POINT:
4593 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4595 case OP_SEQ_POINT: {
4597 MonoInst *info_var = cfg->arch.seq_point_info_var;
4598 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4599 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4600 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4602 int dreg = ARMREG_LR;
4605 if (cfg->soft_breakpoints) {
4606 g_assert (!cfg->compile_aot);
4611 * For AOT, we use one got slot per method, which will point to a
4612 * SeqPointInfo structure, containing all the information required
4613 * by the code below.
4615 if (cfg->compile_aot) {
4616 g_assert (info_var);
4617 g_assert (info_var->opcode == OP_REGOFFSET);
4618 g_assert (arm_is_imm12 (info_var->inst_offset));
4621 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4623 * Read from the single stepping trigger page. This will cause a
4624 * SIGSEGV when single stepping is enabled.
4625 * We do this _before_ the breakpoint, so single stepping after
4626 * a breakpoint is hit will step to the next IL offset.
4628 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4631 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4632 if (cfg->soft_breakpoints) {
4633 /* Load the address of the sequence point method variable. */
4634 var = ss_method_var;
4636 g_assert (var->opcode == OP_REGOFFSET);
4637 g_assert (arm_is_imm12 (var->inst_offset));
4638 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4640 /* Read the value and check whether it is non-zero. */
4641 ARM_LDR_IMM (code, dreg, dreg, 0);
4642 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4643 /* Call it conditionally. */
4644 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4646 if (cfg->compile_aot) {
4647 /* Load the trigger page addr from the variable initialized in the prolog */
4648 var = ss_trigger_page_var;
4650 g_assert (var->opcode == OP_REGOFFSET);
4651 g_assert (arm_is_imm12 (var->inst_offset));
4652 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4654 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4656 *(int*)code = (int)ss_trigger_page;
4659 ARM_LDR_IMM (code, dreg, dreg, 0);
4663 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4665 if (cfg->compile_aot) {
4666 guint32 offset = code - cfg->native_code;
4669 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4670 /* Add the offset */
4671 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4672 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4673 if (arm_is_imm12 ((int)val)) {
4674 ARM_LDR_IMM (code, dreg, dreg, val);
4676 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4678 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4680 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4681 g_assert (!(val & 0xFF000000));
4683 ARM_LDR_IMM (code, dreg, dreg, 0);
4685 /* What is faster, a branch or a load ? */
4686 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4687 /* The breakpoint instruction */
4688 if (cfg->soft_breakpoints)
4689 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4691 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4692 } else if (cfg->soft_breakpoints) {
4693 /* Load the address of the breakpoint method into ip. */
4694 var = bp_method_var;
4696 g_assert (var->opcode == OP_REGOFFSET);
4697 g_assert (arm_is_imm12 (var->inst_offset));
4698 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4701 * A placeholder for a possible breakpoint inserted by
4702 * mono_arch_set_breakpoint ().
4707 * A placeholder for a possible breakpoint inserted by
4708 * mono_arch_set_breakpoint ().
4710 for (i = 0; i < 4; ++i)
4715 * Add an additional nop so skipping the bp doesn't cause the ip to point
4716 * to another IL offset.
4724 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4727 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4731 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4734 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4735 g_assert (imm8 >= 0);
4736 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4740 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4741 g_assert (imm8 >= 0);
4742 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4746 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4747 g_assert (imm8 >= 0);
4748 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4751 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4752 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4754 case OP_IADD_OVF_UN:
4755 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4756 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4759 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4760 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4762 case OP_ISUB_OVF_UN:
4763 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4764 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4766 case OP_ADD_OVF_CARRY:
4767 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4768 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4770 case OP_ADD_OVF_UN_CARRY:
4771 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4772 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4774 case OP_SUB_OVF_CARRY:
4775 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4776 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4778 case OP_SUB_OVF_UN_CARRY:
4779 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4780 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4784 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4787 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4788 g_assert (imm8 >= 0);
4789 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4792 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4796 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4800 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4801 g_assert (imm8 >= 0);
4802 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4806 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4807 g_assert (imm8 >= 0);
4808 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4810 case OP_ARM_RSBS_IMM:
4811 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4812 g_assert (imm8 >= 0);
4813 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4815 case OP_ARM_RSC_IMM:
4816 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4817 g_assert (imm8 >= 0);
4818 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4821 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4825 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4826 g_assert (imm8 >= 0);
4827 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4830 g_assert (v7s_supported || v7k_supported);
4831 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4834 g_assert (v7s_supported || v7k_supported);
4835 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4838 g_assert (v7s_supported || v7k_supported);
4839 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4840 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4843 g_assert (v7s_supported || v7k_supported);
4844 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4845 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4849 g_assert_not_reached ();
4851 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4855 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4856 g_assert (imm8 >= 0);
4857 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4860 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4864 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4865 g_assert (imm8 >= 0);
4866 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4869 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4874 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4875 else if (ins->dreg != ins->sreg1)
4876 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4879 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4884 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4885 else if (ins->dreg != ins->sreg1)
4886 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4889 case OP_ISHR_UN_IMM:
4891 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4892 else if (ins->dreg != ins->sreg1)
4893 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4896 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4899 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4902 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4905 if (ins->dreg == ins->sreg2)
4906 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4908 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4911 g_assert_not_reached ();
4914 /* FIXME: handle ovf/ sreg2 != dreg */
4915 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4916 /* FIXME: MUL doesn't set the C/O flags on ARM */
4918 case OP_IMUL_OVF_UN:
4919 /* FIXME: handle ovf/ sreg2 != dreg */
4920 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4921 /* FIXME: MUL doesn't set the C/O flags on ARM */
4924 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4927 /* Load the GOT offset */
4928 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4929 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4931 *(gpointer*)code = NULL;
4933 /* Load the value from the GOT */
4934 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4936 case OP_OBJC_GET_SELECTOR:
4937 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4938 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4940 *(gpointer*)code = NULL;
4942 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4944 case OP_ICONV_TO_I4:
4945 case OP_ICONV_TO_U4:
4947 if (ins->dreg != ins->sreg1)
4948 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4951 int saved = ins->sreg2;
4952 if (ins->sreg2 == ARM_LSW_REG) {
4953 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4956 if (ins->sreg1 != ARM_LSW_REG)
4957 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4958 if (saved != ARM_MSW_REG)
4959 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4963 if (IS_VFP && ins->dreg != ins->sreg1)
4964 ARM_CPYD (code, ins->dreg, ins->sreg1);
4967 if (IS_VFP && ins->dreg != ins->sreg1)
4968 ARM_CPYS (code, ins->dreg, ins->sreg1);
4970 case OP_MOVE_F_TO_I4:
4972 ARM_FMRS (code, ins->dreg, ins->sreg1);
4974 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4975 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4976 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4977 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4980 case OP_MOVE_I4_TO_F:
4982 ARM_FMSR (code, ins->dreg, ins->sreg1);
4984 ARM_FMSR (code, ins->dreg, ins->sreg1);
4985 ARM_CVTS (code, ins->dreg, ins->dreg);
4988 case OP_FCONV_TO_R4:
4991 ARM_CVTD (code, ins->dreg, ins->sreg1);
4993 ARM_CVTD (code, ins->dreg, ins->sreg1);
4994 ARM_CVTS (code, ins->dreg, ins->dreg);
4999 MonoCallInst *call = (MonoCallInst*)ins;
5002 * The stack looks like the following:
5003 * <caller argument area>
5006 * <callee argument area>
5007 * Need to copy the arguments from the callee argument area to
5008 * the caller argument area, and pop the frame.
5010 if (call->stack_usage) {
5011 int i, prev_sp_offset = 0;
5013 /* Compute size of saved registers restored below */
5015 prev_sp_offset = 2 * 4;
5017 prev_sp_offset = 1 * 4;
5018 for (i = 0; i < 16; ++i) {
5019 if (cfg->used_int_regs & (1 << i))
5020 prev_sp_offset += 4;
5023 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
5025 /* Copy arguments on the stack to our argument area */
5026 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
5027 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
5028 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
5033 * Keep in sync with mono_arch_emit_epilog
5035 g_assert (!cfg->method->save_lmf);
5037 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
5039 if (cfg->used_int_regs)
5040 ARM_POP (code, cfg->used_int_regs);
5041 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5043 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
5046 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
5047 if (cfg->compile_aot) {
5048 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5050 *(gpointer*)code = NULL;
5052 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5054 code = mono_arm_patchable_b (code, ARMCOND_AL);
5055 cfg->thunk_area += THUNK_SIZE;
5060 /* ensure ins->sreg1 is not NULL */
5061 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5064 g_assert (cfg->sig_cookie < 128);
5065 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5066 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5076 call = (MonoCallInst*)ins;
5079 code = emit_float_args (cfg, call, code, &max_len, &offset);
5081 if (ins->flags & MONO_INST_HAS_METHOD)
5082 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5084 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5085 code = emit_call_seq (cfg, code);
5086 ins->flags |= MONO_INST_GC_CALLSITE;
5087 ins->backend.pc_offset = code - cfg->native_code;
5088 code = emit_move_return_value (cfg, ins, code);
5095 case OP_VOIDCALL_REG:
5098 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5100 code = emit_call_reg (code, ins->sreg1);
5101 ins->flags |= MONO_INST_GC_CALLSITE;
5102 ins->backend.pc_offset = code - cfg->native_code;
5103 code = emit_move_return_value (cfg, ins, code);
5105 case OP_FCALL_MEMBASE:
5106 case OP_RCALL_MEMBASE:
5107 case OP_LCALL_MEMBASE:
5108 case OP_VCALL_MEMBASE:
5109 case OP_VCALL2_MEMBASE:
5110 case OP_VOIDCALL_MEMBASE:
5111 case OP_CALL_MEMBASE: {
5112 g_assert (ins->sreg1 != ARMREG_LR);
5113 call = (MonoCallInst*)ins;
5116 code = emit_float_args (cfg, call, code, &max_len, &offset);
5117 if (!arm_is_imm12 (ins->inst_offset)) {
5118 /* sreg1 might be IP */
5119 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5120 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5121 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_LR);
5122 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5123 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, 0);
5125 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5126 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5128 ins->flags |= MONO_INST_GC_CALLSITE;
5129 ins->backend.pc_offset = code - cfg->native_code;
5130 code = emit_move_return_value (cfg, ins, code);
5133 case OP_GENERIC_CLASS_INIT: {
5134 static int byte_offset = -1;
5135 static guint8 bitmask;
5139 if (byte_offset < 0)
5140 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5142 g_assert (arm_is_imm8 (byte_offset));
5143 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5144 imm8 = mono_arm_is_rotated_imm8 (bitmask, &rot_amount);
5145 g_assert (imm8 >= 0);
5146 ARM_AND_REG_IMM (code, ARMREG_IP, ARMREG_IP, imm8, rot_amount);
5147 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5149 ARM_B_COND (code, ARMCOND_NE, 0);
5151 /* Uninitialized case */
5152 g_assert (ins->sreg1 == ARMREG_R0);
5154 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5155 (gpointer)"mono_generic_class_init");
5156 code = emit_call_seq (cfg, code);
5158 /* Initialized case */
5159 arm_patch (jump, code);
5163 /* round the size to 8 bytes */
5164 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5165 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5166 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5167 /* memzero the area: dreg holds the size, sp is the pointer */
5168 if (ins->flags & MONO_INST_INIT) {
5169 guint8 *start_loop, *branch_to_cond;
5170 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5171 branch_to_cond = code;
5174 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5175 arm_patch (branch_to_cond, code);
5176 /* decrement by 4 and set flags */
5177 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5178 ARM_B_COND (code, ARMCOND_GE, 0);
5179 arm_patch (code - 4, start_loop);
5181 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5182 if (cfg->param_area)
5183 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5188 MonoInst *var = cfg->dyn_call_var;
5191 g_assert (var->opcode == OP_REGOFFSET);
5192 g_assert (arm_is_imm12 (var->inst_offset));
5194 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5195 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5197 ARM_MOV_REG_REG (code, ARMREG_IP, ins->sreg2);
5199 /* Save args buffer */
5200 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5202 /* Set stack slots using R0 as scratch reg */
5203 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5204 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5205 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5206 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5209 /* Set fp argument registers */
5210 if (IS_HARD_FLOAT) {
5211 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, has_fpregs));
5212 ARM_CMP_REG_IMM (code, ARMREG_R0, 0, 0);
5214 ARM_B_COND (code, ARMCOND_EQ, 0);
5215 for (i = 0; i < FP_PARAM_REGS; ++i) {
5216 int offset = MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * sizeof (double));
5217 g_assert (arm_is_fpimm8 (offset));
5218 ARM_FLDD (code, i * 2, ARMREG_LR, offset);
5220 arm_patch (buf [0], code);
5223 /* Set argument registers */
5224 for (i = 0; i < PARAM_REGS; ++i)
5225 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5228 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5229 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5232 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5233 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5234 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5236 ARM_FSTD (code, ARM_VFP_D0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, fpregs));
5240 if (ins->sreg1 != ARMREG_R0)
5241 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5242 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5243 (gpointer)"mono_arch_throw_exception");
5244 code = emit_call_seq (cfg, code);
5248 if (ins->sreg1 != ARMREG_R0)
5249 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5250 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5251 (gpointer)"mono_arch_rethrow_exception");
5252 code = emit_call_seq (cfg, code);
5255 case OP_START_HANDLER: {
5256 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5257 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5260 /* Reserve a param area, see filter-stack.exe */
5262 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5263 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5265 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5266 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5270 if (arm_is_imm12 (spvar->inst_offset)) {
5271 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5273 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5274 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5278 case OP_ENDFILTER: {
5279 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5280 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5283 /* Free the param area */
5285 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5286 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5288 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5289 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5293 if (ins->sreg1 != ARMREG_R0)
5294 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5295 if (arm_is_imm12 (spvar->inst_offset)) {
5296 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5298 g_assert (ARMREG_IP != spvar->inst_basereg);
5299 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5300 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5302 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5305 case OP_ENDFINALLY: {
5306 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5307 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5310 /* Free the param area */
5312 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5313 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5315 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5316 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5320 if (arm_is_imm12 (spvar->inst_offset)) {
5321 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5323 g_assert (ARMREG_IP != spvar->inst_basereg);
5324 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5325 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5327 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5330 case OP_CALL_HANDLER:
5331 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5332 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5333 cfg->thunk_area += THUNK_SIZE;
5334 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5337 if (ins->dreg != ARMREG_R0)
5338 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5342 ins->inst_c0 = code - cfg->native_code;
5345 /*if (ins->inst_target_bb->native_offset) {
5347 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5349 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5350 code = mono_arm_patchable_b (code, ARMCOND_AL);
5354 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5358 * In the normal case we have:
5359 * ldr pc, [pc, ins->sreg1 << 2]
5362 * ldr lr, [pc, ins->sreg1 << 2]
5364 * After follows the data.
5365 * FIXME: add aot support.
5367 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5368 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5369 if (offset + max_len > (cfg->code_size - 16)) {
5370 cfg->code_size += max_len;
5371 cfg->code_size *= 2;
5372 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5373 code = cfg->native_code + offset;
5375 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5377 code += 4 * GPOINTER_TO_INT (ins->klass);
5381 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5382 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5386 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5387 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5391 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5392 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5396 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5397 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5401 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5402 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5405 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5406 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5409 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5410 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5413 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5414 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5417 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5418 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5421 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5422 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5424 case OP_COND_EXC_EQ:
5425 case OP_COND_EXC_NE_UN:
5426 case OP_COND_EXC_LT:
5427 case OP_COND_EXC_LT_UN:
5428 case OP_COND_EXC_GT:
5429 case OP_COND_EXC_GT_UN:
5430 case OP_COND_EXC_GE:
5431 case OP_COND_EXC_GE_UN:
5432 case OP_COND_EXC_LE:
5433 case OP_COND_EXC_LE_UN:
5434 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5436 case OP_COND_EXC_IEQ:
5437 case OP_COND_EXC_INE_UN:
5438 case OP_COND_EXC_ILT:
5439 case OP_COND_EXC_ILT_UN:
5440 case OP_COND_EXC_IGT:
5441 case OP_COND_EXC_IGT_UN:
5442 case OP_COND_EXC_IGE:
5443 case OP_COND_EXC_IGE_UN:
5444 case OP_COND_EXC_ILE:
5445 case OP_COND_EXC_ILE_UN:
5446 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5449 case OP_COND_EXC_IC:
5450 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5452 case OP_COND_EXC_OV:
5453 case OP_COND_EXC_IOV:
5454 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5456 case OP_COND_EXC_NC:
5457 case OP_COND_EXC_INC:
5458 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5460 case OP_COND_EXC_NO:
5461 case OP_COND_EXC_INO:
5462 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5474 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5477 /* floating point opcodes */
5479 if (cfg->compile_aot) {
5480 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5482 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5484 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5487 /* FIXME: we can optimize the imm load by dealing with part of
5488 * the displacement in LDFD (aligning to 512).
5490 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5491 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5495 if (cfg->compile_aot) {
5496 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5498 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5501 ARM_CVTS (code, ins->dreg, ins->dreg);
5503 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5504 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5506 ARM_CVTS (code, ins->dreg, ins->dreg);
5509 case OP_STORER8_MEMBASE_REG:
5510 /* This is generated by the local regalloc pass which runs after the lowering pass */
5511 if (!arm_is_fpimm8 (ins->inst_offset)) {
5512 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5513 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5514 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5516 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5519 case OP_LOADR8_MEMBASE:
5520 /* This is generated by the local regalloc pass which runs after the lowering pass */
5521 if (!arm_is_fpimm8 (ins->inst_offset)) {
5522 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5523 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5524 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5526 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5529 case OP_STORER4_MEMBASE_REG:
5530 g_assert (arm_is_fpimm8 (ins->inst_offset));
5532 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5534 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5535 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5536 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5537 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5540 case OP_LOADR4_MEMBASE:
5542 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5544 g_assert (arm_is_fpimm8 (ins->inst_offset));
5545 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5546 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5547 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5548 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5551 case OP_ICONV_TO_R_UN: {
5552 g_assert_not_reached ();
5555 case OP_ICONV_TO_R4:
5557 ARM_FMSR (code, ins->dreg, ins->sreg1);
5558 ARM_FSITOS (code, ins->dreg, ins->dreg);
5560 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5561 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5562 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5563 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5564 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5567 case OP_ICONV_TO_R8:
5568 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5569 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5570 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5571 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5575 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5576 if (sig_ret->type == MONO_TYPE_R4) {
5578 if (IS_HARD_FLOAT) {
5579 if (ins->sreg1 != ARM_VFP_D0)
5580 ARM_CPYS (code, ARM_VFP_D0, ins->sreg1);
5582 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5585 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5588 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5592 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5594 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5598 case OP_FCONV_TO_I1:
5599 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5601 case OP_FCONV_TO_U1:
5602 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5604 case OP_FCONV_TO_I2:
5605 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5607 case OP_FCONV_TO_U2:
5608 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5610 case OP_FCONV_TO_I4:
5612 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5614 case OP_FCONV_TO_U4:
5616 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5618 case OP_FCONV_TO_I8:
5619 case OP_FCONV_TO_U8:
5620 g_assert_not_reached ();
5621 /* Implemented as helper calls */
5623 case OP_LCONV_TO_R_UN:
5624 g_assert_not_reached ();
5625 /* Implemented as helper calls */
5627 case OP_LCONV_TO_OVF_I4_2: {
5628 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5630 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5633 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5634 high_bit_not_set = code;
5635 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5637 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5638 valid_negative = code;
5639 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5640 invalid_negative = code;
5641 ARM_B_COND (code, ARMCOND_AL, 0);
5643 arm_patch (high_bit_not_set, code);
5645 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5646 valid_positive = code;
5647 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5649 arm_patch (invalid_negative, code);
5650 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5652 arm_patch (valid_negative, code);
5653 arm_patch (valid_positive, code);
5655 if (ins->dreg != ins->sreg1)
5656 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5660 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5663 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5666 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5669 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5672 ARM_NEGD (code, ins->dreg, ins->sreg1);
5676 g_assert_not_reached ();
5680 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5686 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5691 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5694 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5695 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5699 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5702 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5703 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5707 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5710 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5711 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5712 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5716 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5719 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5720 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5724 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5727 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5728 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5729 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5733 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5736 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5737 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5741 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5744 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5745 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5749 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5752 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5753 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5756 /* ARM FPA flags table:
5757 * N Less than ARMCOND_MI
5758 * Z Equal ARMCOND_EQ
5759 * C Greater Than or Equal ARMCOND_CS
5760 * V Unordered ARMCOND_VS
5763 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5766 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5769 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5772 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5773 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5779 g_assert_not_reached ();
5783 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5785 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5786 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5787 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5791 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5792 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5797 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5798 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5800 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5801 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5803 *(guint32*)code = 0xffffffff;
5805 *(guint32*)code = 0x7fefffff;
5807 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5809 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "OverflowException");
5810 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5812 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "OverflowException");
5813 ARM_CPYD (code, ins->dreg, ins->sreg1);
5815 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5816 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5821 case OP_RCONV_TO_I1:
5822 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5824 case OP_RCONV_TO_U1:
5825 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5827 case OP_RCONV_TO_I2:
5828 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5830 case OP_RCONV_TO_U2:
5831 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5833 case OP_RCONV_TO_I4:
5834 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5836 case OP_RCONV_TO_U4:
5837 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5839 case OP_RCONV_TO_R4:
5841 if (ins->dreg != ins->sreg1)
5842 ARM_CPYS (code, ins->dreg, ins->sreg1);
5844 case OP_RCONV_TO_R8:
5846 ARM_CVTS (code, ins->dreg, ins->sreg1);
5849 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5852 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5855 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5858 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5861 ARM_NEGS (code, ins->dreg, ins->sreg1);
5865 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5868 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5869 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5873 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5876 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5877 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5881 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5884 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5885 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5886 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5890 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5893 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5894 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5898 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5901 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5902 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5903 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5907 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5910 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5911 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5915 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5918 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5919 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5923 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5926 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5927 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5930 case OP_GC_LIVENESS_DEF:
5931 case OP_GC_LIVENESS_USE:
5932 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5933 ins->backend.pc_offset = code - cfg->native_code;
5935 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5936 ins->backend.pc_offset = code - cfg->native_code;
5937 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5939 case OP_GC_SAFE_POINT: {
5942 g_assert (mono_threads_is_coop_enabled ());
5944 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5945 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5947 ARM_B_COND (code, ARMCOND_EQ, 0);
5948 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
5949 code = emit_call_seq (cfg, code);
5950 arm_patch (buf [0], code);
5955 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5956 g_assert_not_reached ();
5959 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5960 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5961 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5962 g_assert_not_reached ();
5968 last_offset = offset;
5971 cfg->code_len = code - cfg->native_code;
5974 #endif /* DISABLE_JIT */
5977 mono_arch_register_lowlevel_calls (void)
5979 /* The signature doesn't matter */
5980 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5981 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5982 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
5984 #ifndef MONO_CROSS_COMPILE
5985 if (mono_arm_have_tls_get ()) {
5986 MonoTlsImplementation tls_imp = mono_arm_get_tls_implementation ();
5988 mono_register_jit_icall (tls_imp.get_tls_thunk, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
5989 mono_register_jit_icall (tls_imp.set_tls_thunk, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
5991 if (tls_imp.get_tls_thunk_end) {
5992 mono_tramp_info_register (
5993 mono_tramp_info_create (
5995 (guint8*)tls_imp.get_tls_thunk,
5996 (guint8*)tls_imp.get_tls_thunk_end - (guint8*)tls_imp.get_tls_thunk,
5998 mono_arch_get_cie_program ()
6002 mono_tramp_info_register (
6003 mono_tramp_info_create (
6005 (guint8*)tls_imp.set_tls_thunk,
6006 (guint8*)tls_imp.set_tls_thunk_end - (guint8*)tls_imp.set_tls_thunk,
6008 mono_arch_get_cie_program ()
6017 #define patch_lis_ori(ip,val) do {\
6018 guint16 *__lis_ori = (guint16*)(ip); \
6019 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
6020 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
6024 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6026 unsigned char *ip = ji->ip.i + code;
6028 if (ji->type == MONO_PATCH_INFO_SWITCH) {
6032 case MONO_PATCH_INFO_SWITCH: {
6033 gpointer *jt = (gpointer*)(ip + 8);
6035 /* jt is the inlined jump table, 2 instructions after ip
6036 * In the normal case we store the absolute addresses,
6037 * otherwise the displacements.
6039 for (i = 0; i < ji->data.table->table_size; i++)
6040 jt [i] = code + (int)ji->data.table->table [i];
6043 case MONO_PATCH_INFO_IP:
6044 g_assert_not_reached ();
6045 patch_lis_ori (ip, ip);
6047 case MONO_PATCH_INFO_METHOD_REL:
6048 g_assert_not_reached ();
6049 *((gpointer *)(ip)) = target;
6051 case MONO_PATCH_INFO_METHODCONST:
6052 case MONO_PATCH_INFO_CLASS:
6053 case MONO_PATCH_INFO_IMAGE:
6054 case MONO_PATCH_INFO_FIELD:
6055 case MONO_PATCH_INFO_VTABLE:
6056 case MONO_PATCH_INFO_IID:
6057 case MONO_PATCH_INFO_SFLDA:
6058 case MONO_PATCH_INFO_LDSTR:
6059 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
6060 case MONO_PATCH_INFO_LDTOKEN:
6061 g_assert_not_reached ();
6062 /* from OP_AOTCONST : lis + ori */
6063 patch_lis_ori (ip, target);
6065 case MONO_PATCH_INFO_R4:
6066 case MONO_PATCH_INFO_R8:
6067 g_assert_not_reached ();
6068 *((gconstpointer *)(ip + 2)) = target;
6070 case MONO_PATCH_INFO_EXC_NAME:
6071 g_assert_not_reached ();
6072 *((gconstpointer *)(ip + 1)) = target;
6074 case MONO_PATCH_INFO_NONE:
6075 case MONO_PATCH_INFO_BB_OVF:
6076 case MONO_PATCH_INFO_EXC_OVF:
6077 /* everything is dealt with at epilog output time */
6080 arm_patch_general (cfg, domain, ip, target);
6086 mono_arm_unaligned_stack (MonoMethod *method)
6088 g_assert_not_reached ();
6094 * Stack frame layout:
6096 * ------------------- fp
6097 * MonoLMF structure or saved registers
6098 * -------------------
6100 * -------------------
6102 * -------------------
6103 * optional 8 bytes for tracing
6104 * -------------------
6105 * param area size is cfg->param_area
6106 * ------------------- sp
6109 mono_arch_emit_prolog (MonoCompile *cfg)
6111 MonoMethod *method = cfg->method;
6113 MonoMethodSignature *sig;
6115 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6120 int prev_sp_offset, reg_offset;
6122 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6125 sig = mono_method_signature (method);
6126 cfg->code_size = 256 + sig->param_count * 64;
6127 code = cfg->native_code = g_malloc (cfg->code_size);
6129 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6131 alloc_size = cfg->stack_offset;
6137 * The iphone uses R7 as the frame pointer, and it points at the saved
6142 * We can't use r7 as a frame pointer since it points into the middle of
6143 * the frame, so we keep using our own frame pointer.
6144 * FIXME: Optimize this.
6146 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6147 prev_sp_offset += 8; /* r7 and lr */
6148 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6149 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6150 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6153 if (!method->save_lmf) {
6155 /* No need to push LR again */
6156 if (cfg->used_int_regs)
6157 ARM_PUSH (code, cfg->used_int_regs);
6159 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6160 prev_sp_offset += 4;
6162 for (i = 0; i < 16; ++i) {
6163 if (cfg->used_int_regs & (1 << i))
6164 prev_sp_offset += 4;
6166 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6168 for (i = 0; i < 16; ++i) {
6169 if ((cfg->used_int_regs & (1 << i))) {
6170 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6171 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6175 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6176 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6178 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6179 ARM_PUSH (code, 0x5ff0);
6180 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6181 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6183 for (i = 0; i < 16; ++i) {
6184 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6185 /* The original r7 is saved at the start */
6186 if (!(iphone_abi && i == ARMREG_R7))
6187 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6191 g_assert (reg_offset == 4 * 10);
6192 pos += sizeof (MonoLMF) - (4 * 10);
6196 orig_alloc_size = alloc_size;
6197 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6198 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6199 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6200 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6203 /* the stack used in the pushed regs */
6204 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6205 cfg->stack_usage = alloc_size;
6207 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6208 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6210 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6211 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6213 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6215 if (cfg->frame_reg != ARMREG_SP) {
6216 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6217 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6219 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6220 prev_sp_offset += alloc_size;
6222 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6223 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6225 /* compute max_offset in order to use short forward jumps
6226 * we could skip do it on arm because the immediate displacement
6227 * for jumps is large enough, it may be useful later for constant pools
6230 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6231 MonoInst *ins = bb->code;
6232 bb->max_offset = max_offset;
6234 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6237 MONO_BB_FOR_EACH_INS (bb, ins)
6238 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6241 /* stack alignment check */
6245 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6246 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6247 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6248 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6250 ARM_B_COND (code, ARMCOND_EQ, 0);
6251 if (cfg->compile_aot)
6252 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6254 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6255 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6256 code = emit_call_seq (cfg, code);
6257 arm_patch (buf [0], code);
6261 /* store runtime generic context */
6262 if (cfg->rgctx_var) {
6263 MonoInst *ins = cfg->rgctx_var;
6265 g_assert (ins->opcode == OP_REGOFFSET);
6267 if (arm_is_imm12 (ins->inst_offset)) {
6268 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6270 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6271 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6275 /* load arguments allocated to register from the stack */
6278 cinfo = get_call_info (NULL, sig);
6280 if (cinfo->ret.storage == RegTypeStructByAddr) {
6281 ArgInfo *ainfo = &cinfo->ret;
6282 inst = cfg->vret_addr;
6283 g_assert (arm_is_imm12 (inst->inst_offset));
6284 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6287 if (sig->call_convention == MONO_CALL_VARARG) {
6288 ArgInfo *cookie = &cinfo->sig_cookie;
6290 /* Save the sig cookie address */
6291 g_assert (cookie->storage == RegTypeBase);
6293 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6294 g_assert (arm_is_imm12 (cfg->sig_cookie));
6295 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6296 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6299 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6300 ArgInfo *ainfo = cinfo->args + i;
6301 inst = cfg->args [pos];
6303 if (cfg->verbose_level > 2)
6304 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6306 if (inst->opcode == OP_REGVAR) {
6307 if (ainfo->storage == RegTypeGeneral)
6308 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6309 else if (ainfo->storage == RegTypeFP) {
6310 g_assert_not_reached ();
6311 } else if (ainfo->storage == RegTypeBase) {
6312 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6313 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6315 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6316 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6319 g_assert_not_reached ();
6321 if (cfg->verbose_level > 2)
6322 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6324 switch (ainfo->storage) {
6326 for (part = 0; part < ainfo->nregs; part ++) {
6327 if (ainfo->esize == 4)
6328 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6330 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6333 case RegTypeGeneral:
6334 case RegTypeIRegPair:
6335 case RegTypeGSharedVtInReg:
6336 case RegTypeStructByAddr:
6337 switch (ainfo->size) {
6339 if (arm_is_imm12 (inst->inst_offset))
6340 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6342 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6343 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6347 if (arm_is_imm8 (inst->inst_offset)) {
6348 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6350 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6351 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6355 if (arm_is_imm12 (inst->inst_offset)) {
6356 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6358 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6359 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6361 if (arm_is_imm12 (inst->inst_offset + 4)) {
6362 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6364 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6365 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6369 if (arm_is_imm12 (inst->inst_offset)) {
6370 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6372 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6373 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6378 case RegTypeBaseGen:
6379 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6380 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6382 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6383 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6385 if (arm_is_imm12 (inst->inst_offset + 4)) {
6386 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6387 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6389 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6390 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6391 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6392 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6396 case RegTypeGSharedVtOnStack:
6397 case RegTypeStructByAddrOnStack:
6398 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6399 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6401 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6402 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6405 switch (ainfo->size) {
6407 if (arm_is_imm8 (inst->inst_offset)) {
6408 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6410 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6411 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6415 if (arm_is_imm8 (inst->inst_offset)) {
6416 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6418 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6419 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6423 if (arm_is_imm12 (inst->inst_offset)) {
6424 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6426 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6427 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6429 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6430 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6432 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6433 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6435 if (arm_is_imm12 (inst->inst_offset + 4)) {
6436 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6438 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6439 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6443 if (arm_is_imm12 (inst->inst_offset)) {
6444 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6446 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6447 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6453 int imm8, rot_amount;
6455 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6456 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6457 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6459 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6461 if (ainfo->size == 8)
6462 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6464 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6467 case RegTypeStructByVal: {
6468 int doffset = inst->inst_offset;
6472 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6473 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6474 if (arm_is_imm12 (doffset)) {
6475 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6477 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6478 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6480 soffset += sizeof (gpointer);
6481 doffset += sizeof (gpointer);
6483 if (ainfo->vtsize) {
6484 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6485 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6486 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6491 g_assert_not_reached ();
6498 if (method->save_lmf)
6499 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6502 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6504 if (cfg->arch.seq_point_info_var) {
6505 MonoInst *ins = cfg->arch.seq_point_info_var;
6507 /* Initialize the variable from a GOT slot */
6508 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6509 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6511 *(gpointer*)code = NULL;
6513 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6515 g_assert (ins->opcode == OP_REGOFFSET);
6517 if (arm_is_imm12 (ins->inst_offset)) {
6518 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6520 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6521 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6525 /* Initialize ss_trigger_page_var */
6526 if (!cfg->soft_breakpoints) {
6527 MonoInst *info_var = cfg->arch.seq_point_info_var;
6528 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6529 int dreg = ARMREG_LR;
6532 g_assert (info_var->opcode == OP_REGOFFSET);
6533 g_assert (arm_is_imm12 (info_var->inst_offset));
6535 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6536 /* Load the trigger page addr */
6537 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6538 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6542 if (cfg->arch.seq_point_ss_method_var) {
6543 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6544 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6545 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6546 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6547 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6548 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6550 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6552 *(gpointer*)code = &single_step_tramp;
6554 *(gpointer*)code = breakpoint_tramp;
6557 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6558 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6559 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6560 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6563 cfg->code_len = code - cfg->native_code;
6564 g_assert (cfg->code_len < cfg->code_size);
6571 mono_arch_emit_epilog (MonoCompile *cfg)
6573 MonoMethod *method = cfg->method;
6574 int pos, i, rot_amount;
6575 int max_epilog_size = 16 + 20*4;
6579 if (cfg->method->save_lmf)
6580 max_epilog_size += 128;
6582 if (mono_jit_trace_calls != NULL)
6583 max_epilog_size += 50;
6585 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6586 max_epilog_size += 50;
6588 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6589 cfg->code_size *= 2;
6590 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6591 cfg->stat_code_reallocs++;
6595 * Keep in sync with OP_JMP
6597 code = cfg->native_code + cfg->code_len;
6599 /* Save the uwind state which is needed by the out-of-line code */
6600 mono_emit_unwind_op_remember_state (cfg, code);
6602 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6603 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6607 /* Load returned vtypes into registers if needed */
6608 cinfo = cfg->arch.cinfo;
6609 switch (cinfo->ret.storage) {
6610 case RegTypeStructByVal: {
6611 MonoInst *ins = cfg->ret;
6613 if (cinfo->ret.nregs == 1) {
6614 if (arm_is_imm12 (ins->inst_offset)) {
6615 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6617 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6618 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6621 for (i = 0; i < cinfo->ret.nregs; ++i) {
6622 int offset = ins->inst_offset + (i * 4);
6623 if (arm_is_imm12 (offset)) {
6624 ARM_LDR_IMM (code, i, ins->inst_basereg, offset);
6626 code = mono_arm_emit_load_imm (code, ARMREG_LR, offset);
6627 ARM_LDR_REG_REG (code, i, ins->inst_basereg, ARMREG_LR);
6634 MonoInst *ins = cfg->ret;
6636 for (i = 0; i < cinfo->ret.nregs; ++i) {
6637 if (cinfo->ret.esize == 4)
6638 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6640 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6648 if (method->save_lmf) {
6649 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6650 /* all but r0-r3, sp and pc */
6651 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6654 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6656 /* This points to r4 inside MonoLMF->iregs */
6657 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6659 regmask = 0x9ff0; /* restore lr to pc */
6660 /* Skip caller saved registers not used by the method */
6661 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6662 regmask &= ~(1 << reg);
6667 /* Restored later */
6668 regmask &= ~(1 << ARMREG_PC);
6669 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6670 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6671 for (i = 0; i < 16; i++) {
6672 if (regmask & (1 << i))
6675 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6677 ARM_POP (code, regmask);
6679 for (i = 0; i < 16; i++) {
6680 if (regmask & (1 << i))
6681 mono_emit_unwind_op_same_value (cfg, code, i);
6683 /* Restore saved r7, restore LR to PC */
6684 /* Skip lr from the lmf */
6685 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6686 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6687 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6688 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6691 int i, nused_int_regs = 0;
6693 for (i = 0; i < 16; i++) {
6694 if (cfg->used_int_regs & (1 << i))
6698 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6699 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6701 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6702 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6705 if (cfg->frame_reg != ARMREG_SP) {
6706 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6710 /* Restore saved gregs */
6711 if (cfg->used_int_regs) {
6712 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6713 ARM_POP (code, cfg->used_int_regs);
6714 for (i = 0; i < 16; i++) {
6715 if (cfg->used_int_regs & (1 << i))
6716 mono_emit_unwind_op_same_value (cfg, code, i);
6719 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6720 /* Restore saved r7, restore LR to PC */
6721 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6723 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6724 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6728 /* Restore the unwind state to be the same as before the epilog */
6729 mono_emit_unwind_op_restore_state (cfg, code);
6731 cfg->code_len = code - cfg->native_code;
6733 g_assert (cfg->code_len < cfg->code_size);
6738 mono_arch_emit_exceptions (MonoCompile *cfg)
6740 MonoJumpInfo *patch_info;
6743 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6744 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6745 int max_epilog_size = 50;
6747 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6748 exc_throw_pos [i] = NULL;
6749 exc_throw_found [i] = 0;
6752 /* count the number of exception infos */
6755 * make sure we have enough space for exceptions
6757 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6758 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6759 i = mini_exception_id_by_name (patch_info->data.target);
6760 if (!exc_throw_found [i]) {
6761 max_epilog_size += 32;
6762 exc_throw_found [i] = TRUE;
6767 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6768 cfg->code_size *= 2;
6769 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6770 cfg->stat_code_reallocs++;
6773 code = cfg->native_code + cfg->code_len;
6775 /* add code to raise exceptions */
6776 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6777 switch (patch_info->type) {
6778 case MONO_PATCH_INFO_EXC: {
6779 MonoClass *exc_class;
6780 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6782 i = mini_exception_id_by_name (patch_info->data.target);
6783 if (exc_throw_pos [i]) {
6784 arm_patch (ip, exc_throw_pos [i]);
6785 patch_info->type = MONO_PATCH_INFO_NONE;
6788 exc_throw_pos [i] = code;
6790 arm_patch (ip, code);
6792 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6794 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6795 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6796 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6797 patch_info->data.name = "mono_arch_throw_corlib_exception";
6798 patch_info->ip.i = code - cfg->native_code;
6800 cfg->thunk_area += THUNK_SIZE;
6801 *(guint32*)(gpointer)code = exc_class->type_token - MONO_TOKEN_TYPE_DEF;
6811 cfg->code_len = code - cfg->native_code;
6813 g_assert (cfg->code_len < cfg->code_size);
6817 #endif /* #ifndef DISABLE_JIT */
6820 mono_arch_finish_init (void)
6825 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6830 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6837 mono_arch_print_tree (MonoInst *tree, int arity)
6847 mono_arch_get_patch_offset (guint8 *code)
6854 mono_arch_flush_register_windows (void)
6859 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6861 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6865 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6867 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6871 mono_arch_get_cie_program (void)
6875 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6880 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6881 #define BASE_SIZE (6 * 4)
6882 #define BSEARCH_ENTRY_SIZE (4 * 4)
6883 #define CMP_SIZE (3 * 4)
6884 #define BRANCH_SIZE (1 * 4)
6885 #define CALL_SIZE (2 * 4)
6886 #define WMC_SIZE (8 * 4)
6887 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6890 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6892 guint32 delta = DISTANCE (target, code);
6894 g_assert (delta >= 0 && delta <= 0xFFF);
6895 *target = *target | delta;
6900 #ifdef ENABLE_WRONG_METHOD_CHECK
6902 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6904 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6910 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6911 gpointer fail_tramp)
6914 arminstr_t *code, *start;
6915 gboolean large_offsets = FALSE;
6916 guint32 **constant_pool_starts;
6917 arminstr_t *vtable_target = NULL;
6918 int extra_space = 0;
6919 #ifdef ENABLE_WRONG_METHOD_CHECK
6925 constant_pool_starts = g_new0 (guint32*, count);
6927 for (i = 0; i < count; ++i) {
6928 MonoIMTCheckItem *item = imt_entries [i];
6929 if (item->is_equals) {
6930 gboolean fail_case = !item->check_target_idx && fail_tramp;
6932 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6933 item->chunk_size += 32;
6934 large_offsets = TRUE;
6937 if (item->check_target_idx || fail_case) {
6938 if (!item->compare_done || fail_case)
6939 item->chunk_size += CMP_SIZE;
6940 item->chunk_size += BRANCH_SIZE;
6942 #ifdef ENABLE_WRONG_METHOD_CHECK
6943 item->chunk_size += WMC_SIZE;
6947 item->chunk_size += 16;
6948 large_offsets = TRUE;
6950 item->chunk_size += CALL_SIZE;
6952 item->chunk_size += BSEARCH_ENTRY_SIZE;
6953 imt_entries [item->check_target_idx]->compare_done = TRUE;
6955 size += item->chunk_size;
6959 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6962 code = mono_method_alloc_generic_virtual_thunk (domain, size);
6964 code = mono_domain_code_reserve (domain, size);
6967 unwind_ops = mono_arch_get_cie_program ();
6970 g_print ("Building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6971 for (i = 0; i < count; ++i) {
6972 MonoIMTCheckItem *item = imt_entries [i];
6973 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
6977 if (large_offsets) {
6978 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6979 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
6981 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
6982 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6984 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
6985 vtable_target = code;
6986 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
6987 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
6989 for (i = 0; i < count; ++i) {
6990 MonoIMTCheckItem *item = imt_entries [i];
6991 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
6992 gint32 vtable_offset;
6994 item->code_target = (guint8*)code;
6996 if (item->is_equals) {
6997 gboolean fail_case = !item->check_target_idx && fail_tramp;
6999 if (item->check_target_idx || fail_case) {
7000 if (!item->compare_done || fail_case) {
7002 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7003 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7005 item->jmp_code = (guint8*)code;
7006 ARM_B_COND (code, ARMCOND_NE, 0);
7008 /*Enable the commented code to assert on wrong method*/
7009 #ifdef ENABLE_WRONG_METHOD_CHECK
7011 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7012 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7014 ARM_B_COND (code, ARMCOND_EQ, 0);
7016 /* Define this if your system is so bad that gdb is failing. */
7017 #ifdef BROKEN_DEV_ENV
7018 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
7020 arm_patch (code - 1, mini_dump_bad_imt);
7024 arm_patch (cond, code);
7028 if (item->has_target_code) {
7029 /* Load target address */
7030 target_code_ins = code;
7031 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7032 /* Save it to the fourth slot */
7033 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7034 /* Restore registers and branch */
7035 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7037 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
7039 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
7040 if (!arm_is_imm12 (vtable_offset)) {
7042 * We need to branch to a computed address but we don't have
7043 * a free register to store it, since IP must contain the
7044 * vtable address. So we push the two values to the stack, and
7045 * load them both using LDM.
7047 /* Compute target address */
7048 vtable_offset_ins = code;
7049 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7050 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
7051 /* Save it to the fourth slot */
7052 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7053 /* Restore registers and branch */
7054 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7056 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
7058 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
7059 if (large_offsets) {
7060 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7061 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
7063 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7064 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
7069 arm_patch (item->jmp_code, (guchar*)code);
7071 target_code_ins = code;
7072 /* Load target address */
7073 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7074 /* Save it to the fourth slot */
7075 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7076 /* Restore registers and branch */
7077 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7079 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7080 item->jmp_code = NULL;
7084 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7086 /*must emit after unconditional branch*/
7087 if (vtable_target) {
7088 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7089 item->chunk_size += 4;
7090 vtable_target = NULL;
7093 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7094 constant_pool_starts [i] = code;
7096 code += extra_space;
7100 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7101 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7103 item->jmp_code = (guint8*)code;
7104 ARM_B_COND (code, ARMCOND_HS, 0);
7109 for (i = 0; i < count; ++i) {
7110 MonoIMTCheckItem *item = imt_entries [i];
7111 if (item->jmp_code) {
7112 if (item->check_target_idx)
7113 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7115 if (i > 0 && item->is_equals) {
7117 arminstr_t *space_start = constant_pool_starts [i];
7118 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7119 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7126 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7127 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7132 g_free (constant_pool_starts);
7134 mono_arch_flush_icache ((guint8*)start, size);
7135 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7136 mono_stats.imt_thunks_size += code - start;
7138 g_assert (DISTANCE (start, code) <= size);
7140 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7146 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7148 return ctx->regs [reg];
7152 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7154 ctx->regs [reg] = val;
7158 * mono_arch_get_trampolines:
7160 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7164 mono_arch_get_trampolines (gboolean aot)
7166 return mono_arm_get_exception_trampolines (aot);
7170 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7177 bp = MONO_CONTEXT_GET_BP (ctx);
7178 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7180 old_value = *lr_loc;
7181 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7184 *lr_loc = new_value;
7189 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7191 * mono_arch_set_breakpoint:
7193 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7194 * The location should contain code emitted by OP_SEQ_POINT.
7197 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7200 guint32 native_offset = ip - (guint8*)ji->code_start;
7201 MonoDebugOptions *opt = mini_get_debug_options ();
7204 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7206 g_assert (native_offset % 4 == 0);
7207 g_assert (info->bp_addrs [native_offset / 4] == 0);
7208 info->bp_addrs [native_offset / 4] = opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page;
7209 } else if (opt->soft_breakpoints) {
7211 ARM_BLX_REG (code, ARMREG_LR);
7212 mono_arch_flush_icache (code - 4, 4);
7214 int dreg = ARMREG_LR;
7216 /* Read from another trigger page */
7217 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7219 *(int*)code = (int)bp_trigger_page;
7221 ARM_LDR_IMM (code, dreg, dreg, 0);
7223 mono_arch_flush_icache (code - 16, 16);
7226 /* This is currently implemented by emitting an SWI instruction, which
7227 * qemu/linux seems to convert to a SIGILL.
7229 *(int*)code = (0xef << 24) | 8;
7231 mono_arch_flush_icache (code - 4, 4);
7237 * mono_arch_clear_breakpoint:
7239 * Clear the breakpoint at IP.
7242 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7244 MonoDebugOptions *opt = mini_get_debug_options ();
7249 guint32 native_offset = ip - (guint8*)ji->code_start;
7250 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7252 g_assert (native_offset % 4 == 0);
7253 g_assert (info->bp_addrs [native_offset / 4] == (opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page));
7254 info->bp_addrs [native_offset / 4] = 0;
7255 } else if (opt->soft_breakpoints) {
7258 mono_arch_flush_icache (code - 4, 4);
7260 for (i = 0; i < 4; ++i)
7263 mono_arch_flush_icache (ip, code - ip);
7268 * mono_arch_start_single_stepping:
7270 * Start single stepping.
7273 mono_arch_start_single_stepping (void)
7275 if (ss_trigger_page)
7276 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7278 single_step_tramp = mini_get_single_step_trampoline ();
7282 * mono_arch_stop_single_stepping:
7284 * Stop single stepping.
7287 mono_arch_stop_single_stepping (void)
7289 if (ss_trigger_page)
7290 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7292 single_step_tramp = NULL;
7296 #define DBG_SIGNAL SIGBUS
7298 #define DBG_SIGNAL SIGSEGV
7302 * mono_arch_is_single_step_event:
7304 * Return whenever the machine state in SIGCTX corresponds to a single
7308 mono_arch_is_single_step_event (void *info, void *sigctx)
7310 siginfo_t *sinfo = info;
7312 if (!ss_trigger_page)
7315 /* Sometimes the address is off by 4 */
7316 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7323 * mono_arch_is_breakpoint_event:
7325 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7328 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7330 siginfo_t *sinfo = info;
7332 if (!ss_trigger_page)
7335 if (sinfo->si_signo == DBG_SIGNAL) {
7336 /* Sometimes the address is off by 4 */
7337 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7347 * mono_arch_skip_breakpoint:
7349 * See mini-amd64.c for docs.
7352 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7354 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7358 * mono_arch_skip_single_step:
7360 * See mini-amd64.c for docs.
7363 mono_arch_skip_single_step (MonoContext *ctx)
7365 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7368 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7371 * mono_arch_get_seq_point_info:
7373 * See mini-amd64.c for docs.
7376 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7381 // FIXME: Add a free function
7383 mono_domain_lock (domain);
7384 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7386 mono_domain_unlock (domain);
7389 ji = mono_jit_info_table_find (domain, (char*)code);
7392 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7394 info->ss_trigger_page = ss_trigger_page;
7395 info->bp_trigger_page = bp_trigger_page;
7397 mono_domain_lock (domain);
7398 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7400 mono_domain_unlock (domain);
7407 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7409 ext->lmf.previous_lmf = prev_lmf;
7410 /* Mark that this is a MonoLMFExt */
7411 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7412 ext->lmf.sp = (gssize)ext;
7416 * mono_arch_set_target:
7418 * Set the target architecture the JIT backend should generate code for, in the form
7419 * of a GNU target triplet. Only used in AOT mode.
7422 mono_arch_set_target (char *mtriple)
7424 /* The GNU target triple format is not very well documented */
7425 if (strstr (mtriple, "armv7")) {
7426 v5_supported = TRUE;
7427 v6_supported = TRUE;
7428 v7_supported = TRUE;
7430 if (strstr (mtriple, "armv6")) {
7431 v5_supported = TRUE;
7432 v6_supported = TRUE;
7434 if (strstr (mtriple, "armv7s")) {
7435 v7s_supported = TRUE;
7437 if (strstr (mtriple, "armv7k")) {
7438 v7k_supported = TRUE;
7440 if (strstr (mtriple, "thumbv7s")) {
7441 v5_supported = TRUE;
7442 v6_supported = TRUE;
7443 v7_supported = TRUE;
7444 v7s_supported = TRUE;
7445 thumb_supported = TRUE;
7446 thumb2_supported = TRUE;
7448 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7449 v5_supported = TRUE;
7450 v6_supported = TRUE;
7451 thumb_supported = TRUE;
7454 if (strstr (mtriple, "gnueabi"))
7455 eabi_supported = TRUE;
7459 mono_arch_opcode_supported (int opcode)
7462 case OP_ATOMIC_ADD_I4:
7463 case OP_ATOMIC_EXCHANGE_I4:
7464 case OP_ATOMIC_CAS_I4:
7465 case OP_ATOMIC_LOAD_I1:
7466 case OP_ATOMIC_LOAD_I2:
7467 case OP_ATOMIC_LOAD_I4:
7468 case OP_ATOMIC_LOAD_U1:
7469 case OP_ATOMIC_LOAD_U2:
7470 case OP_ATOMIC_LOAD_U4:
7471 case OP_ATOMIC_STORE_I1:
7472 case OP_ATOMIC_STORE_I2:
7473 case OP_ATOMIC_STORE_I4:
7474 case OP_ATOMIC_STORE_U1:
7475 case OP_ATOMIC_STORE_U2:
7476 case OP_ATOMIC_STORE_U4:
7477 return v7_supported;
7478 case OP_ATOMIC_LOAD_R4:
7479 case OP_ATOMIC_LOAD_R8:
7480 case OP_ATOMIC_STORE_R4:
7481 case OP_ATOMIC_STORE_R8:
7482 return v7_supported && IS_VFP;
7489 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
7491 return get_call_info (mp, sig);