3 * ARM backend for the Mono code generator
6 * Paolo Molaro (lupus@ximian.com)
7 * Dietmar Maurer (dietmar@ximian.com)
9 * (C) 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
11 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
12 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
17 #include <mono/metadata/abi-details.h>
18 #include <mono/metadata/appdomain.h>
19 #include <mono/metadata/profiler-private.h>
20 #include <mono/metadata/debug-helpers.h>
21 #include <mono/utils/mono-mmap.h>
22 #include <mono/utils/mono-hwcap.h>
23 #include <mono/utils/mono-memory-model.h>
24 #include <mono/utils/mono-threads-coop.h>
30 #include "debugger-agent.h"
32 #include "mono/arch/arm/arm-vfp-codegen.h"
34 /* Sanity check: This makes no sense */
35 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
36 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
40 * IS_SOFT_FLOAT: Is full software floating point used?
41 * IS_HARD_FLOAT: Is full hardware floating point used?
42 * IS_VFP: Is hardware floating point with software ABI used?
44 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
45 * IS_VFP may delegate to mono_arch_is_soft_float ().
48 #if defined(ARM_FPU_VFP_HARD)
49 #define IS_SOFT_FLOAT (FALSE)
50 #define IS_HARD_FLOAT (TRUE)
52 #elif defined(ARM_FPU_NONE)
53 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
54 #define IS_HARD_FLOAT (FALSE)
55 #define IS_VFP (!mono_arch_is_soft_float ())
57 #define IS_SOFT_FLOAT (FALSE)
58 #define IS_HARD_FLOAT (FALSE)
62 #define THUNK_SIZE (3 * 4)
64 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
67 void sys_icache_invalidate (void *start, size_t len);
70 /* This mutex protects architecture specific caches */
71 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
72 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
73 static mono_mutex_t mini_arch_mutex;
75 static gboolean v5_supported = FALSE;
76 static gboolean v6_supported = FALSE;
77 static gboolean v7_supported = FALSE;
78 static gboolean v7s_supported = FALSE;
79 static gboolean v7k_supported = FALSE;
80 static gboolean thumb_supported = FALSE;
81 static gboolean thumb2_supported = FALSE;
83 * Whenever to use the ARM EABI
85 static gboolean eabi_supported = FALSE;
88 * Whenever to use the iphone ABI extensions:
89 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
90 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
91 * This is required for debugging/profiling tools to work, but it has some overhead so it should
92 * only be turned on in debug builds.
94 static gboolean iphone_abi = FALSE;
97 * The FPU we are generating code for. This is NOT runtime configurable right now,
98 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
100 static MonoArmFPU arm_fpu;
102 #if defined(ARM_FPU_VFP_HARD)
104 * On armhf, d0-d7 are used for argument passing and d8-d15
105 * must be preserved across calls, which leaves us no room
106 * for scratch registers. So we use d14-d15 but back up their
107 * previous contents to a stack slot before using them - see
108 * mono_arm_emit_vfp_scratch_save/_restore ().
110 static int vfp_scratch1 = ARM_VFP_D14;
111 static int vfp_scratch2 = ARM_VFP_D15;
114 * On armel, d0-d7 do not need to be preserved, so we can
115 * freely make use of them as scratch registers.
117 static int vfp_scratch1 = ARM_VFP_D0;
118 static int vfp_scratch2 = ARM_VFP_D1;
123 static gpointer single_step_tramp, breakpoint_tramp;
124 static gpointer get_tls_tramp;
127 * The code generated for sequence points reads from this location, which is
128 * made read-only when single stepping is enabled.
130 static gpointer ss_trigger_page;
132 /* Enabled breakpoints read from this trigger page */
133 static gpointer bp_trigger_page;
137 * floating point support: on ARM it is a mess, there are at least 3
138 * different setups, each of which binary incompat with the other.
139 * 1) FPA: old and ugly, but unfortunately what current distros use
140 * the double binary format has the two words swapped. 8 double registers.
141 * Implemented usually by kernel emulation.
142 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
143 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
144 * 3) VFP: the new and actually sensible and useful FP support. Implemented
145 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
147 * We do not care about FPA. We will support soft float and VFP.
149 int mono_exc_esp_offset = 0;
151 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
152 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
153 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
155 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
156 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
157 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
159 //#define DEBUG_IMT 0
162 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
166 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data);
169 mono_arch_regname (int reg)
171 static const char * rnames[] = {
172 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
173 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
174 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
177 if (reg >= 0 && reg < 16)
183 mono_arch_fregname (int reg)
185 static const char * rnames[] = {
186 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
187 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
188 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
189 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
190 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
191 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
194 if (reg >= 0 && reg < 32)
202 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
204 int imm8, rot_amount;
205 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
206 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
210 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
211 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
213 code = mono_arm_emit_load_imm (code, dreg, imm);
214 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
219 /* If dreg == sreg, this clobbers IP */
221 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
223 int imm8, rot_amount;
224 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
225 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
229 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
230 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
232 code = mono_arm_emit_load_imm (code, dreg, imm);
233 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
239 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
241 /* we can use r0-r3, since this is called only for incoming args on the stack */
242 if (size > sizeof (gpointer) * 4) {
244 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
245 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
246 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
247 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
248 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
249 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
250 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
251 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
252 ARM_B_COND (code, ARMCOND_NE, 0);
253 arm_patch (code - 4, start_loop);
256 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
257 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
259 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
260 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
266 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
267 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
268 doffset = soffset = 0;
270 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
271 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
277 g_assert (size == 0);
282 emit_call_reg (guint8 *code, int reg)
285 ARM_BLX_REG (code, reg);
287 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
291 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
297 emit_call_seq (MonoCompile *cfg, guint8 *code)
299 if (cfg->method->dynamic) {
300 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
302 *(gpointer*)code = NULL;
304 code = emit_call_reg (code, ARMREG_IP);
308 cfg->thunk_area += THUNK_SIZE;
313 mono_arm_patchable_b (guint8 *code, int cond)
315 ARM_B_COND (code, cond, 0);
320 mono_arm_patchable_bl (guint8 *code, int cond)
322 ARM_BL_COND (code, cond, 0);
326 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID) && !defined(__native_client__)
327 #define HAVE_AEABI_READ_TP 1
330 #ifdef HAVE_AEABI_READ_TP
331 gpointer __aeabi_read_tp (void);
335 mono_arch_have_fast_tls (void)
337 #ifdef HAVE_AEABI_READ_TP
338 static gboolean have_fast_tls = FALSE;
339 static gboolean inited = FALSE;
342 if (mini_get_debug_options ()->use_fallback_tls)
346 return have_fast_tls;
348 tp1 = __aeabi_read_tp ();
349 asm volatile("mrc p15, 0, %0, c13, c0, 3" : "=r" (tp2));
351 have_fast_tls = tp1 && tp1 == tp2;
353 return have_fast_tls;
360 emit_tls_get (guint8 *code, int dreg, int tls_offset)
362 ARM_MRC (code, 15, 0, dreg, 13, 0, 3);
363 ARM_LDR_IMM (code, dreg, dreg, tls_offset);
368 emit_tls_set (guint8 *code, int sreg, int tls_offset)
370 int tp_reg = (sreg != ARMREG_R0) ? ARMREG_R0 : ARMREG_R1;
371 ARM_MRC (code, 15, 0, tp_reg, 13, 0, 3);
372 ARM_STR_IMM (code, sreg, tp_reg, tls_offset);
379 * Emit code to push an LMF structure on the LMF stack.
380 * On arm, this is intermixed with the initialization of other fields of the structure.
383 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
387 if (mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_LMF_ADDR) != -1) {
388 code = emit_tls_get (code, ARMREG_R0, mono_tls_get_tls_offset (TLS_KEY_LMF_ADDR));
390 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
391 (gpointer)"mono_tls_get_lmf_addr");
392 code = emit_call_seq (cfg, code);
394 /* we build the MonoLMF structure on the stack - see mini-arm.h */
395 /* lmf_offset is the offset from the previous stack pointer,
396 * alloc_size is the total stack space allocated, so the offset
397 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
398 * The pointer to the struct is put in r1 (new_lmf).
399 * ip is used as scratch
400 * The callee-saved registers are already in the MonoLMF structure
402 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
403 /* r0 is the result from mono_get_lmf_addr () */
404 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
405 /* new_lmf->previous_lmf = *lmf_addr */
406 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
407 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
408 /* *(lmf_addr) = r1 */
409 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
410 /* Skip method (only needed for trampoline LMF frames) */
411 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
412 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
413 /* save the current IP */
414 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
415 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
417 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
418 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
429 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
433 for (list = inst->float_args; list; list = list->next) {
434 FloatArgData *fad = list->data;
435 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
436 gboolean imm = arm_is_fpimm8 (var->inst_offset);
438 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
444 if (*offset + *max_len > cfg->code_size) {
445 cfg->code_size += *max_len;
446 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
448 code = cfg->native_code + *offset;
452 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
453 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
455 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
457 *offset = code - cfg->native_code;
464 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
468 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
470 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
473 if (!arm_is_fpimm8 (inst->inst_offset)) {
474 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
475 ARM_FSTD (code, reg, ARMREG_LR, 0);
477 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
484 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
488 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
490 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
493 if (!arm_is_fpimm8 (inst->inst_offset)) {
494 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
495 ARM_FLDD (code, reg, ARMREG_LR, 0);
497 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
506 * Emit code to pop an LMF structure from the LMF stack.
509 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
513 if (lmf_offset < 32) {
514 basereg = cfg->frame_reg;
519 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
522 /* ip = previous_lmf */
523 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
525 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
526 /* *(lmf_addr) = previous_lmf */
527 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
532 #endif /* #ifndef DISABLE_JIT */
535 * mono_arch_get_argument_info:
536 * @csig: a method signature
537 * @param_count: the number of parameters to consider
538 * @arg_info: an array to store the result infos
540 * Gathers information on parameters such as size, alignment and
541 * padding. arg_info should be large enought to hold param_count + 1 entries.
543 * Returns the size of the activation frame.
546 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
548 int k, frame_size = 0;
549 guint32 size, align, pad;
553 t = mini_get_underlying_type (csig->ret);
554 if (MONO_TYPE_ISSTRUCT (t)) {
555 frame_size += sizeof (gpointer);
559 arg_info [0].offset = offset;
562 frame_size += sizeof (gpointer);
566 arg_info [0].size = frame_size;
568 for (k = 0; k < param_count; k++) {
569 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
571 /* ignore alignment for now */
574 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
575 arg_info [k].pad = pad;
577 arg_info [k + 1].pad = 0;
578 arg_info [k + 1].size = size;
580 arg_info [k + 1].offset = offset;
584 align = MONO_ARCH_FRAME_ALIGNMENT;
585 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
586 arg_info [k].pad = pad;
591 #define MAX_ARCH_DELEGATE_PARAMS 3
594 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
596 guint8 *code, *start;
597 GSList *unwind_ops = mono_arch_get_cie_program ();
600 start = code = mono_global_codeman_reserve (12);
602 /* Replace the this argument with the target */
603 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
604 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
605 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
607 g_assert ((code - start) <= 12);
609 mono_arch_flush_icache (start, 12);
613 size = 8 + param_count * 4;
614 start = code = mono_global_codeman_reserve (size);
616 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
617 /* slide down the arguments */
618 for (i = 0; i < param_count; ++i) {
619 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
621 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
623 g_assert ((code - start) <= size);
625 mono_arch_flush_icache (start, size);
629 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
631 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
632 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
636 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
642 * mono_arch_get_delegate_invoke_impls:
644 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
648 mono_arch_get_delegate_invoke_impls (void)
654 get_delegate_invoke_impl (&info, TRUE, 0);
655 res = g_slist_prepend (res, info);
657 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
658 get_delegate_invoke_impl (&info, FALSE, i);
659 res = g_slist_prepend (res, info);
666 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
668 guint8 *code, *start;
671 /* FIXME: Support more cases */
672 sig_ret = mini_get_underlying_type (sig->ret);
673 if (MONO_TYPE_ISSTRUCT (sig_ret))
677 static guint8* cached = NULL;
678 mono_mini_arch_lock ();
680 mono_mini_arch_unlock ();
685 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
688 start = get_delegate_invoke_impl (&info, TRUE, 0);
689 mono_tramp_info_register (info, NULL);
692 mono_mini_arch_unlock ();
695 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
698 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
700 for (i = 0; i < sig->param_count; ++i)
701 if (!mono_is_regsize_var (sig->params [i]))
704 mono_mini_arch_lock ();
705 code = cache [sig->param_count];
707 mono_mini_arch_unlock ();
712 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
713 start = mono_aot_get_trampoline (name);
717 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
718 mono_tramp_info_register (info, NULL);
720 cache [sig->param_count] = start;
721 mono_mini_arch_unlock ();
729 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
735 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
737 return (gpointer)regs [ARMREG_R0];
741 * Initialize the cpu to execute managed code.
744 mono_arch_cpu_init (void)
746 i8_align = MONO_ABI_ALIGNOF (gint64);
747 #ifdef MONO_CROSS_COMPILE
748 /* Need to set the alignment of i8 since it can different on the target */
749 #ifdef TARGET_ANDROID
751 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
757 * Initialize architecture specific code.
760 mono_arch_init (void)
762 const char *cpu_arch;
764 #ifdef TARGET_WATCHOS
765 mini_get_debug_options ()->soft_breakpoints = TRUE;
768 mono_os_mutex_init_recursive (&mini_arch_mutex);
769 if (mini_get_debug_options ()->soft_breakpoints) {
771 breakpoint_tramp = mini_get_breakpoint_trampoline ();
773 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT, MONO_MEM_ACCOUNT_OTHER);
774 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT, MONO_MEM_ACCOUNT_OTHER);
775 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
778 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
779 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
780 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
781 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
782 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
784 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
785 mono_aot_register_jit_icall ("mono_arm_handler_block_trampoline_helper", mono_arm_handler_block_trampoline_helper);
786 #if defined(__ARM_EABI__)
787 eabi_supported = TRUE;
790 #if defined(ARM_FPU_VFP_HARD)
791 arm_fpu = MONO_ARM_FPU_VFP_HARD;
793 arm_fpu = MONO_ARM_FPU_VFP;
795 #if defined(ARM_FPU_NONE) && !defined(TARGET_IOS)
797 * If we're compiling with a soft float fallback and it
798 * turns out that no VFP unit is available, we need to
799 * switch to soft float. We don't do this for iOS, since
800 * iOS devices always have a VFP unit.
802 if (!mono_hwcap_arm_has_vfp)
803 arm_fpu = MONO_ARM_FPU_NONE;
806 * This environment variable can be useful in testing
807 * environments to make sure the soft float fallback
808 * works. Most ARM devices have VFP units these days, so
809 * normally soft float code would not be exercised much.
811 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
813 if (soft && !strncmp (soft, "1", 1))
814 arm_fpu = MONO_ARM_FPU_NONE;
819 v5_supported = mono_hwcap_arm_is_v5;
820 v6_supported = mono_hwcap_arm_is_v6;
821 v7_supported = mono_hwcap_arm_is_v7;
824 * On weird devices, the hwcap code may fail to detect
825 * the ARM version. In that case, we can at least safely
826 * assume the version the runtime was compiled for.
838 #if defined(TARGET_IOS)
839 /* iOS is special-cased here because we don't yet
840 have a way to properly detect CPU features on it. */
841 thumb_supported = TRUE;
844 thumb_supported = mono_hwcap_arm_has_thumb;
845 thumb2_supported = mono_hwcap_arm_has_thumb2;
848 /* Format: armv(5|6|7[s])[-thumb[2]] */
849 cpu_arch = g_getenv ("MONO_CPU_ARCH");
851 /* Do this here so it overrides any detection. */
853 if (strncmp (cpu_arch, "armv", 4) == 0) {
854 v5_supported = cpu_arch [4] >= '5';
855 v6_supported = cpu_arch [4] >= '6';
856 v7_supported = cpu_arch [4] >= '7';
857 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
858 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
861 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
862 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
868 * Cleanup architecture specific code.
871 mono_arch_cleanup (void)
876 * This function returns the optimizations supported on this cpu.
879 mono_arch_cpu_optimizations (guint32 *exclude_mask)
881 /* no arm-specific optimizations yet */
887 * This function test for all SIMD functions supported.
889 * Returns a bitmask corresponding to all supported versions.
893 mono_arch_cpu_enumerate_simd_versions (void)
895 /* SIMD is currently unimplemented */
900 mono_arm_is_hard_float (void)
902 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
908 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
910 if (v7s_supported || v7k_supported) {
924 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
926 mono_arch_is_soft_float (void)
928 return arm_fpu == MONO_ARM_FPU_NONE;
933 is_regsize_var (MonoType *t)
937 t = mini_get_underlying_type (t);
944 case MONO_TYPE_FNPTR:
946 case MONO_TYPE_OBJECT:
948 case MONO_TYPE_GENERICINST:
949 if (!mono_type_generic_inst_is_valuetype (t))
952 case MONO_TYPE_VALUETYPE:
959 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
964 for (i = 0; i < cfg->num_varinfo; i++) {
965 MonoInst *ins = cfg->varinfo [i];
966 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
969 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
972 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
975 /* we can only allocate 32 bit values */
976 if (is_regsize_var (ins->inst_vtype)) {
977 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
978 g_assert (i == vmv->idx);
979 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
987 mono_arch_get_global_int_regs (MonoCompile *cfg)
991 mono_arch_compute_omit_fp (cfg);
994 * FIXME: Interface calls might go through a static rgctx trampoline which
995 * sets V5, but it doesn't save it, so we need to save it ourselves, and
998 if (cfg->flags & MONO_CFG_HAS_CALLS)
999 cfg->uses_rgctx_reg = TRUE;
1001 if (cfg->arch.omit_fp)
1002 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1003 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1004 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1005 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1007 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1008 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1010 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1011 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1012 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1013 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1014 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1015 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1021 * mono_arch_regalloc_cost:
1023 * Return the cost, in number of memory references, of the action of
1024 * allocating the variable VMV into a register during global register
1028 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1034 #endif /* #ifndef DISABLE_JIT */
1037 mono_arch_flush_icache (guint8 *code, gint size)
1039 #if defined(MONO_CROSS_COMPILE)
1041 sys_icache_invalidate (code, size);
1043 __builtin___clear_cache (code, code + size);
1050 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1053 if (*gr > ARMREG_R3) {
1055 ainfo->offset = *stack_size;
1056 ainfo->reg = ARMREG_SP; /* in the caller */
1057 ainfo->storage = RegTypeBase;
1060 ainfo->storage = RegTypeGeneral;
1067 split = i8_align == 4;
1072 if (*gr == ARMREG_R3 && split) {
1073 /* first word in r3 and the second on the stack */
1074 ainfo->offset = *stack_size;
1075 ainfo->reg = ARMREG_SP; /* in the caller */
1076 ainfo->storage = RegTypeBaseGen;
1078 } else if (*gr >= ARMREG_R3) {
1079 if (eabi_supported) {
1080 /* darwin aligns longs to 4 byte only */
1081 if (i8_align == 8) {
1086 ainfo->offset = *stack_size;
1087 ainfo->reg = ARMREG_SP; /* in the caller */
1088 ainfo->storage = RegTypeBase;
1091 if (eabi_supported) {
1092 if (i8_align == 8 && ((*gr) & 1))
1095 ainfo->storage = RegTypeIRegPair;
1104 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1107 * If we're calling a function like this:
1109 * void foo(float a, double b, float c)
1111 * We pass a in s0 and b in d1. That leaves us
1112 * with s1 being unused. The armhf ABI recognizes
1113 * this and requires register assignment to then
1114 * use that for the next single-precision arg,
1115 * i.e. c in this example. So float_spare either
1116 * tells us which reg to use for the next single-
1117 * precision arg, or it's -1, meaning use *fpr.
1119 * Note that even though most of the JIT speaks
1120 * double-precision, fpr represents single-
1121 * precision registers.
1123 * See parts 5.5 and 6.1.2 of the AAPCS for how
1127 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1128 ainfo->storage = RegTypeFP;
1132 * If we're passing a double-precision value
1133 * and *fpr is odd (e.g. it's s1, s3, ...)
1134 * we need to use the next even register. So
1135 * we mark the current *fpr as a spare that
1136 * can be used for the next single-precision
1140 *float_spare = *fpr;
1145 * At this point, we have an even register
1146 * so we assign that and move along.
1150 } else if (*float_spare >= 0) {
1152 * We're passing a single-precision value
1153 * and it looks like a spare single-
1154 * precision register is available. Let's
1158 ainfo->reg = *float_spare;
1162 * If we hit this branch, we're passing a
1163 * single-precision value and we can simply
1164 * use the next available register.
1172 * We've exhausted available floating point
1173 * regs, so pass the rest on the stack.
1181 ainfo->offset = *stack_size;
1182 ainfo->reg = ARMREG_SP;
1183 ainfo->storage = RegTypeBase;
1190 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1194 MonoClassField *field;
1195 MonoType *ftype, *prev_ftype = NULL;
1198 klass = mono_class_from_mono_type (t);
1200 while ((field = mono_class_get_fields (klass, &iter))) {
1201 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1203 ftype = mono_field_get_type (field);
1204 ftype = mini_get_underlying_type (ftype);
1206 if (MONO_TYPE_ISSTRUCT (ftype)) {
1207 int nested_nfields, nested_esize;
1209 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1211 if (nested_esize == 4)
1212 ftype = &mono_defaults.single_class->byval_arg;
1214 ftype = &mono_defaults.double_class->byval_arg;
1215 if (prev_ftype && prev_ftype->type != ftype->type)
1218 nfields += nested_nfields;
1220 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1222 if (prev_ftype && prev_ftype->type != ftype->type)
1228 if (nfields == 0 || nfields > 4)
1230 *out_nfields = nfields;
1231 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1236 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1238 guint i, gr, fpr, pstart;
1240 int n = sig->hasthis + sig->param_count;
1244 guint32 stack_size = 0;
1246 gboolean is_pinvoke = sig->pinvoke;
1247 gboolean vtype_retaddr = FALSE;
1250 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1252 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1259 t = mini_get_underlying_type (sig->ret);
1270 case MONO_TYPE_FNPTR:
1271 case MONO_TYPE_OBJECT:
1272 cinfo->ret.storage = RegTypeGeneral;
1273 cinfo->ret.reg = ARMREG_R0;
1277 cinfo->ret.storage = RegTypeIRegPair;
1278 cinfo->ret.reg = ARMREG_R0;
1282 cinfo->ret.storage = RegTypeFP;
1284 if (t->type == MONO_TYPE_R4)
1285 cinfo->ret.size = 4;
1287 cinfo->ret.size = 8;
1289 if (IS_HARD_FLOAT) {
1290 cinfo->ret.reg = ARM_VFP_F0;
1292 cinfo->ret.reg = ARMREG_R0;
1295 case MONO_TYPE_GENERICINST:
1296 if (!mono_type_generic_inst_is_valuetype (t)) {
1297 cinfo->ret.storage = RegTypeGeneral;
1298 cinfo->ret.reg = ARMREG_R0;
1301 if (mini_is_gsharedvt_variable_type (t)) {
1302 cinfo->ret.storage = RegTypeStructByAddr;
1306 case MONO_TYPE_VALUETYPE:
1307 case MONO_TYPE_TYPEDBYREF:
1308 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1309 cinfo->ret.storage = RegTypeHFA;
1311 cinfo->ret.nregs = nfields;
1312 cinfo->ret.esize = esize;
1315 int native_size = mono_class_native_size (mono_class_from_mono_type (t), &align);
1318 #ifdef TARGET_WATCHOS
1323 if (native_size <= max_size) {
1324 cinfo->ret.storage = RegTypeStructByVal;
1325 cinfo->ret.struct_size = native_size;
1326 cinfo->ret.nregs = ALIGN_TO (native_size, 4) / 4;
1328 cinfo->ret.storage = RegTypeStructByAddr;
1331 cinfo->ret.storage = RegTypeStructByAddr;
1336 case MONO_TYPE_MVAR:
1337 g_assert (mini_is_gsharedvt_type (t));
1338 cinfo->ret.storage = RegTypeStructByAddr;
1340 case MONO_TYPE_VOID:
1343 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1346 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1351 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1352 * the first argument, allowing 'this' to be always passed in the first arg reg.
1353 * Also do this if the first argument is a reference type, since virtual calls
1354 * are sometimes made using calli without sig->hasthis set, like in the delegate
1357 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1359 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1361 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1365 cinfo->ret.reg = gr;
1367 cinfo->vret_arg_index = 1;
1371 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1374 if (vtype_retaddr) {
1375 cinfo->ret.reg = gr;
1380 DEBUG(g_print("params: %d\n", sig->param_count));
1381 for (i = pstart; i < sig->param_count; ++i) {
1382 ArgInfo *ainfo = &cinfo->args [n];
1384 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1385 /* Prevent implicit arguments and sig_cookie from
1386 being passed in registers */
1389 /* Emit the signature cookie just before the implicit arguments */
1390 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1392 DEBUG(g_print("param %d: ", i));
1393 if (sig->params [i]->byref) {
1394 DEBUG(g_print("byref\n"));
1395 add_general (&gr, &stack_size, ainfo, TRUE);
1399 t = mini_get_underlying_type (sig->params [i]);
1403 cinfo->args [n].size = 1;
1404 add_general (&gr, &stack_size, ainfo, TRUE);
1408 cinfo->args [n].size = 2;
1409 add_general (&gr, &stack_size, ainfo, TRUE);
1413 cinfo->args [n].size = 4;
1414 add_general (&gr, &stack_size, ainfo, TRUE);
1419 case MONO_TYPE_FNPTR:
1420 case MONO_TYPE_OBJECT:
1421 cinfo->args [n].size = sizeof (gpointer);
1422 add_general (&gr, &stack_size, ainfo, TRUE);
1424 case MONO_TYPE_GENERICINST:
1425 if (!mono_type_generic_inst_is_valuetype (t)) {
1426 cinfo->args [n].size = sizeof (gpointer);
1427 add_general (&gr, &stack_size, ainfo, TRUE);
1430 if (mini_is_gsharedvt_variable_type (t)) {
1431 /* gsharedvt arguments are passed by ref */
1432 g_assert (mini_is_gsharedvt_type (t));
1433 add_general (&gr, &stack_size, ainfo, TRUE);
1434 switch (ainfo->storage) {
1435 case RegTypeGeneral:
1436 ainfo->storage = RegTypeGSharedVtInReg;
1439 ainfo->storage = RegTypeGSharedVtOnStack;
1442 g_assert_not_reached ();
1447 case MONO_TYPE_TYPEDBYREF:
1448 case MONO_TYPE_VALUETYPE: {
1451 int nwords, nfields, esize;
1454 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1455 if (fpr + nfields < ARM_VFP_F16) {
1456 ainfo->storage = RegTypeHFA;
1458 ainfo->nregs = nfields;
1459 ainfo->esize = esize;
1470 if (t->type == MONO_TYPE_TYPEDBYREF) {
1471 size = sizeof (MonoTypedRef);
1472 align = sizeof (gpointer);
1474 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1476 size = mono_class_native_size (klass, &align);
1478 size = mini_type_stack_size_full (t, &align, FALSE);
1480 DEBUG(g_print ("load %d bytes struct\n", size));
1482 #ifdef TARGET_WATCHOS
1483 /* Watchos pass large structures by ref */
1484 /* We only do this for pinvoke to make gsharedvt/dyncall simpler */
1485 if (sig->pinvoke && size > 16) {
1486 add_general (&gr, &stack_size, ainfo, TRUE);
1487 switch (ainfo->storage) {
1488 case RegTypeGeneral:
1489 ainfo->storage = RegTypeStructByAddr;
1492 ainfo->storage = RegTypeStructByAddrOnStack;
1495 g_assert_not_reached ();
1504 align_size += (sizeof (gpointer) - 1);
1505 align_size &= ~(sizeof (gpointer) - 1);
1506 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1507 ainfo->storage = RegTypeStructByVal;
1508 ainfo->struct_size = size;
1509 ainfo->align = align;
1510 /* FIXME: align stack_size if needed */
1511 if (eabi_supported) {
1512 if (align >= 8 && (gr & 1))
1515 if (gr > ARMREG_R3) {
1517 ainfo->vtsize = nwords;
1519 int rest = ARMREG_R3 - gr + 1;
1520 int n_in_regs = rest >= nwords? nwords: rest;
1522 ainfo->size = n_in_regs;
1523 ainfo->vtsize = nwords - n_in_regs;
1526 nwords -= n_in_regs;
1528 if (sig->call_convention == MONO_CALL_VARARG)
1529 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1530 stack_size = ALIGN_TO (stack_size, align);
1531 ainfo->offset = stack_size;
1532 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1533 stack_size += nwords * sizeof (gpointer);
1539 add_general (&gr, &stack_size, ainfo, FALSE);
1545 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1547 add_general (&gr, &stack_size, ainfo, TRUE);
1553 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1555 add_general (&gr, &stack_size, ainfo, FALSE);
1558 case MONO_TYPE_MVAR:
1559 /* gsharedvt arguments are passed by ref */
1560 g_assert (mini_is_gsharedvt_type (t));
1561 add_general (&gr, &stack_size, ainfo, TRUE);
1562 switch (ainfo->storage) {
1563 case RegTypeGeneral:
1564 ainfo->storage = RegTypeGSharedVtInReg;
1567 ainfo->storage = RegTypeGSharedVtOnStack;
1570 g_assert_not_reached ();
1574 g_error ("Can't handle 0x%x", sig->params [i]->type);
1579 /* Handle the case where there are no implicit arguments */
1580 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1581 /* Prevent implicit arguments and sig_cookie from
1582 being passed in registers */
1585 /* Emit the signature cookie just before the implicit arguments */
1586 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1589 /* align stack size to 8 */
1590 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1591 stack_size = (stack_size + 7) & ~7;
1593 cinfo->stack_usage = stack_size;
1599 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1601 MonoType *callee_ret;
1605 c1 = get_call_info (NULL, caller_sig);
1606 c2 = get_call_info (NULL, callee_sig);
1609 * Tail calls with more callee stack usage than the caller cannot be supported, since
1610 * the extra stack space would be left on the stack after the tail call.
1612 res = c1->stack_usage >= c2->stack_usage;
1613 callee_ret = mini_get_underlying_type (callee_sig->ret);
1614 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1615 /* An address on the callee's stack is passed as the first argument */
1618 if (c2->stack_usage > 16 * 4)
1630 debug_omit_fp (void)
1633 return mono_debug_count ();
1640 * mono_arch_compute_omit_fp:
1641 * Determine whether the frame pointer can be eliminated.
1644 mono_arch_compute_omit_fp (MonoCompile *cfg)
1646 MonoMethodSignature *sig;
1647 MonoMethodHeader *header;
1651 if (cfg->arch.omit_fp_computed)
1654 header = cfg->header;
1656 sig = mono_method_signature (cfg->method);
1658 if (!cfg->arch.cinfo)
1659 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1660 cinfo = cfg->arch.cinfo;
1663 * FIXME: Remove some of the restrictions.
1665 cfg->arch.omit_fp = TRUE;
1666 cfg->arch.omit_fp_computed = TRUE;
1668 if (cfg->disable_omit_fp)
1669 cfg->arch.omit_fp = FALSE;
1670 if (!debug_omit_fp ())
1671 cfg->arch.omit_fp = FALSE;
1673 if (cfg->method->save_lmf)
1674 cfg->arch.omit_fp = FALSE;
1676 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1677 cfg->arch.omit_fp = FALSE;
1678 if (header->num_clauses)
1679 cfg->arch.omit_fp = FALSE;
1680 if (cfg->param_area)
1681 cfg->arch.omit_fp = FALSE;
1682 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1683 cfg->arch.omit_fp = FALSE;
1684 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1685 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1686 cfg->arch.omit_fp = FALSE;
1687 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1688 ArgInfo *ainfo = &cinfo->args [i];
1690 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1692 * The stack offset can only be determined when the frame
1695 cfg->arch.omit_fp = FALSE;
1700 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1701 MonoInst *ins = cfg->varinfo [i];
1704 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1709 * Set var information according to the calling convention. arm version.
1710 * The locals var stuff should most likely be split in another method.
1713 mono_arch_allocate_vars (MonoCompile *cfg)
1715 MonoMethodSignature *sig;
1716 MonoMethodHeader *header;
1719 int i, offset, size, align, curinst;
1724 sig = mono_method_signature (cfg->method);
1726 if (!cfg->arch.cinfo)
1727 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1728 cinfo = cfg->arch.cinfo;
1729 sig_ret = mini_get_underlying_type (sig->ret);
1731 mono_arch_compute_omit_fp (cfg);
1733 if (cfg->arch.omit_fp)
1734 cfg->frame_reg = ARMREG_SP;
1736 cfg->frame_reg = ARMREG_FP;
1738 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1740 /* allow room for the vararg method args: void* and long/double */
1741 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1742 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1744 header = cfg->header;
1746 /* See mono_arch_get_global_int_regs () */
1747 if (cfg->flags & MONO_CFG_HAS_CALLS)
1748 cfg->uses_rgctx_reg = TRUE;
1750 if (cfg->frame_reg != ARMREG_SP)
1751 cfg->used_int_regs |= 1 << cfg->frame_reg;
1753 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1754 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1755 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1759 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1760 if (sig_ret->type != MONO_TYPE_VOID) {
1761 cfg->ret->opcode = OP_REGVAR;
1762 cfg->ret->inst_c0 = ARMREG_R0;
1765 /* local vars are at a positive offset from the stack pointer */
1767 * also note that if the function uses alloca, we use FP
1768 * to point at the local variables.
1770 offset = 0; /* linkage area */
1771 /* align the offset to 16 bytes: not sure this is needed here */
1773 //offset &= ~(8 - 1);
1775 /* add parameter area size for called functions */
1776 offset += cfg->param_area;
1779 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1782 /* allow room to save the return value */
1783 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1786 switch (cinfo->ret.storage) {
1787 case RegTypeStructByVal:
1789 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1790 offset = ALIGN_TO (offset, 8);
1791 cfg->ret->opcode = OP_REGOFFSET;
1792 cfg->ret->inst_basereg = cfg->frame_reg;
1793 cfg->ret->inst_offset = offset;
1794 if (cinfo->ret.storage == RegTypeStructByVal)
1795 offset += cinfo->ret.nregs * sizeof (gpointer);
1799 case RegTypeStructByAddr:
1800 ins = cfg->vret_addr;
1801 offset += sizeof(gpointer) - 1;
1802 offset &= ~(sizeof(gpointer) - 1);
1803 ins->inst_offset = offset;
1804 ins->opcode = OP_REGOFFSET;
1805 ins->inst_basereg = cfg->frame_reg;
1806 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1807 g_print ("vret_addr =");
1808 mono_print_ins (cfg->vret_addr);
1810 offset += sizeof(gpointer);
1816 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1817 if (cfg->arch.seq_point_info_var) {
1820 ins = cfg->arch.seq_point_info_var;
1824 offset += align - 1;
1825 offset &= ~(align - 1);
1826 ins->opcode = OP_REGOFFSET;
1827 ins->inst_basereg = cfg->frame_reg;
1828 ins->inst_offset = offset;
1831 if (cfg->arch.ss_trigger_page_var) {
1834 ins = cfg->arch.ss_trigger_page_var;
1837 offset += align - 1;
1838 offset &= ~(align - 1);
1839 ins->opcode = OP_REGOFFSET;
1840 ins->inst_basereg = cfg->frame_reg;
1841 ins->inst_offset = offset;
1845 if (cfg->arch.seq_point_ss_method_var) {
1848 ins = cfg->arch.seq_point_ss_method_var;
1851 offset += align - 1;
1852 offset &= ~(align - 1);
1853 ins->opcode = OP_REGOFFSET;
1854 ins->inst_basereg = cfg->frame_reg;
1855 ins->inst_offset = offset;
1858 if (cfg->arch.seq_point_bp_method_var) {
1861 ins = cfg->arch.seq_point_bp_method_var;
1864 offset += align - 1;
1865 offset &= ~(align - 1);
1866 ins->opcode = OP_REGOFFSET;
1867 ins->inst_basereg = cfg->frame_reg;
1868 ins->inst_offset = offset;
1872 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
1873 /* Allocate a temporary used by the atomic ops */
1877 /* Allocate a local slot to hold the sig cookie address */
1878 offset += align - 1;
1879 offset &= ~(align - 1);
1880 cfg->arch.atomic_tmp_offset = offset;
1883 cfg->arch.atomic_tmp_offset = -1;
1886 cfg->locals_min_stack_offset = offset;
1888 curinst = cfg->locals_start;
1889 for (i = curinst; i < cfg->num_varinfo; ++i) {
1892 ins = cfg->varinfo [i];
1893 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1896 t = ins->inst_vtype;
1897 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
1900 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1901 * pinvoke wrappers when they call functions returning structure */
1902 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
1903 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
1907 size = mono_type_size (t, &align);
1909 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1910 * since it loads/stores misaligned words, which don't do the right thing.
1912 if (align < 4 && size >= 4)
1914 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1915 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1916 offset += align - 1;
1917 offset &= ~(align - 1);
1918 ins->opcode = OP_REGOFFSET;
1919 ins->inst_offset = offset;
1920 ins->inst_basereg = cfg->frame_reg;
1922 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1925 cfg->locals_max_stack_offset = offset;
1929 ins = cfg->args [curinst];
1930 if (ins->opcode != OP_REGVAR) {
1931 ins->opcode = OP_REGOFFSET;
1932 ins->inst_basereg = cfg->frame_reg;
1933 offset += sizeof (gpointer) - 1;
1934 offset &= ~(sizeof (gpointer) - 1);
1935 ins->inst_offset = offset;
1936 offset += sizeof (gpointer);
1941 if (sig->call_convention == MONO_CALL_VARARG) {
1945 /* Allocate a local slot to hold the sig cookie address */
1946 offset += align - 1;
1947 offset &= ~(align - 1);
1948 cfg->sig_cookie = offset;
1952 for (i = 0; i < sig->param_count; ++i) {
1953 ainfo = cinfo->args + i;
1955 ins = cfg->args [curinst];
1957 switch (ainfo->storage) {
1959 offset = ALIGN_TO (offset, 8);
1960 ins->opcode = OP_REGOFFSET;
1961 ins->inst_basereg = cfg->frame_reg;
1962 /* These arguments are saved to the stack in the prolog */
1963 ins->inst_offset = offset;
1964 if (cfg->verbose_level >= 2)
1965 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
1973 if (ins->opcode != OP_REGVAR) {
1974 ins->opcode = OP_REGOFFSET;
1975 ins->inst_basereg = cfg->frame_reg;
1976 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
1978 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1979 * since it loads/stores misaligned words, which don't do the right thing.
1981 if (align < 4 && size >= 4)
1983 /* The code in the prolog () stores words when storing vtypes received in a register */
1984 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
1986 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1987 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1988 offset += align - 1;
1989 offset &= ~(align - 1);
1990 ins->inst_offset = offset;
1996 /* align the offset to 8 bytes */
1997 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
1998 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2003 cfg->stack_offset = offset;
2007 mono_arch_create_vars (MonoCompile *cfg)
2009 MonoMethodSignature *sig;
2013 sig = mono_method_signature (cfg->method);
2015 if (!cfg->arch.cinfo)
2016 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2017 cinfo = cfg->arch.cinfo;
2019 if (IS_HARD_FLOAT) {
2020 for (i = 0; i < 2; i++) {
2021 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2022 inst->flags |= MONO_INST_VOLATILE;
2024 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2028 if (cinfo->ret.storage == RegTypeStructByVal)
2029 cfg->ret_var_is_local = TRUE;
2031 if (cinfo->ret.storage == RegTypeStructByAddr) {
2032 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2033 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2034 g_print ("vret_addr = ");
2035 mono_print_ins (cfg->vret_addr);
2039 if (cfg->gen_sdb_seq_points) {
2040 if (cfg->compile_aot) {
2041 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2042 ins->flags |= MONO_INST_VOLATILE;
2043 cfg->arch.seq_point_info_var = ins;
2045 if (!cfg->soft_breakpoints) {
2046 /* Allocate a separate variable for this to save 1 load per seq point */
2047 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2048 ins->flags |= MONO_INST_VOLATILE;
2049 cfg->arch.ss_trigger_page_var = ins;
2052 if (cfg->soft_breakpoints) {
2055 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2056 ins->flags |= MONO_INST_VOLATILE;
2057 cfg->arch.seq_point_ss_method_var = ins;
2059 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2060 ins->flags |= MONO_INST_VOLATILE;
2061 cfg->arch.seq_point_bp_method_var = ins;
2067 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2069 MonoMethodSignature *tmp_sig;
2072 if (call->tail_call)
2075 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2078 * mono_ArgIterator_Setup assumes the signature cookie is
2079 * passed first and all the arguments which were before it are
2080 * passed on the stack after the signature. So compensate by
2081 * passing a different signature.
2083 tmp_sig = mono_metadata_signature_dup (call->signature);
2084 tmp_sig->param_count -= call->signature->sentinelpos;
2085 tmp_sig->sentinelpos = 0;
2086 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2088 sig_reg = mono_alloc_ireg (cfg);
2089 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2091 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2096 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2101 LLVMCallInfo *linfo;
2103 n = sig->param_count + sig->hasthis;
2105 cinfo = get_call_info (cfg->mempool, sig);
2107 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2110 * LLVM always uses the native ABI while we use our own ABI, the
2111 * only difference is the handling of vtypes:
2112 * - we only pass/receive them in registers in some cases, and only
2113 * in 1 or 2 integer registers.
2115 switch (cinfo->ret.storage) {
2116 case RegTypeGeneral:
2119 case RegTypeIRegPair:
2121 case RegTypeStructByAddr:
2122 /* Vtype returned using a hidden argument */
2123 linfo->ret.storage = LLVMArgVtypeRetAddr;
2124 linfo->vret_arg_index = cinfo->vret_arg_index;
2127 case RegTypeStructByVal:
2128 /* LLVM models this by returning an int array */
2129 linfo->ret.storage = LLVMArgAsIArgs;
2130 linfo->ret.nslots = cinfo->ret.nregs;
2134 linfo->ret.storage = LLVMArgFpStruct;
2135 linfo->ret.nslots = cinfo->ret.nregs;
2136 linfo->ret.esize = cinfo->ret.esize;
2139 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2140 cfg->disable_llvm = TRUE;
2144 for (i = 0; i < n; ++i) {
2145 LLVMArgInfo *lainfo = &linfo->args [i];
2146 ainfo = cinfo->args + i;
2148 lainfo->storage = LLVMArgNone;
2150 switch (ainfo->storage) {
2151 case RegTypeGeneral:
2152 case RegTypeIRegPair:
2154 case RegTypeBaseGen:
2156 lainfo->storage = LLVMArgNormal;
2158 case RegTypeStructByVal:
2159 lainfo->storage = LLVMArgAsIArgs;
2160 if (eabi_supported && ainfo->align == 8) {
2161 /* LLVM models this by passing an int64 array */
2162 lainfo->nslots = ALIGN_TO (ainfo->struct_size, 8) / 8;
2165 lainfo->nslots = ainfo->struct_size / sizeof (gpointer);
2169 printf ("D: %d\n", ainfo->align);
2171 case RegTypeStructByAddr:
2172 case RegTypeStructByAddrOnStack:
2173 lainfo->storage = LLVMArgVtypeByRef;
2178 lainfo->storage = LLVMArgAsFpArgs;
2179 lainfo->nslots = ainfo->nregs;
2180 lainfo->esize = ainfo->esize;
2181 for (j = 0; j < ainfo->nregs; ++j)
2182 lainfo->pair_storage [j] = LLVMArgInFPReg;
2186 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2187 cfg->disable_llvm = TRUE;
2197 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2200 MonoMethodSignature *sig;
2204 sig = call->signature;
2205 n = sig->param_count + sig->hasthis;
2207 cinfo = get_call_info (cfg->mempool, sig);
2209 switch (cinfo->ret.storage) {
2210 case RegTypeStructByVal:
2212 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
2213 /* The JIT will transform this into a normal call */
2214 call->vret_in_reg = TRUE;
2217 if (call->inst.opcode == OP_TAILCALL)
2220 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2221 * the location pointed to by it after call in emit_move_return_value ().
2223 if (!cfg->arch.vret_addr_loc) {
2224 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2225 /* Prevent it from being register allocated or optimized away */
2226 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2229 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2231 case RegTypeStructByAddr: {
2233 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2234 vtarg->sreg1 = call->vret_var->dreg;
2235 vtarg->dreg = mono_alloc_preg (cfg);
2236 MONO_ADD_INS (cfg->cbb, vtarg);
2238 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2245 for (i = 0; i < n; ++i) {
2246 ArgInfo *ainfo = cinfo->args + i;
2249 if (i >= sig->hasthis)
2250 t = sig->params [i - sig->hasthis];
2252 t = &mono_defaults.int_class->byval_arg;
2253 t = mini_get_underlying_type (t);
2255 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2256 /* Emit the signature cookie just before the implicit arguments */
2257 emit_sig_cookie (cfg, call, cinfo);
2260 in = call->args [i];
2262 switch (ainfo->storage) {
2263 case RegTypeGeneral:
2264 case RegTypeIRegPair:
2265 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2266 MONO_INST_NEW (cfg, ins, OP_MOVE);
2267 ins->dreg = mono_alloc_ireg (cfg);
2268 ins->sreg1 = MONO_LVREG_LS (in->dreg);
2269 MONO_ADD_INS (cfg->cbb, ins);
2270 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2272 MONO_INST_NEW (cfg, ins, OP_MOVE);
2273 ins->dreg = mono_alloc_ireg (cfg);
2274 ins->sreg1 = MONO_LVREG_MS (in->dreg);
2275 MONO_ADD_INS (cfg->cbb, ins);
2276 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2277 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2278 if (ainfo->size == 4) {
2279 if (IS_SOFT_FLOAT) {
2280 /* mono_emit_call_args () have already done the r8->r4 conversion */
2281 /* The converted value is in an int vreg */
2282 MONO_INST_NEW (cfg, ins, OP_MOVE);
2283 ins->dreg = mono_alloc_ireg (cfg);
2284 ins->sreg1 = in->dreg;
2285 MONO_ADD_INS (cfg->cbb, ins);
2286 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2290 cfg->param_area = MAX (cfg->param_area, 8);
2291 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2292 creg = mono_alloc_ireg (cfg);
2293 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2294 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2297 if (IS_SOFT_FLOAT) {
2298 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2299 ins->dreg = mono_alloc_ireg (cfg);
2300 ins->sreg1 = in->dreg;
2301 MONO_ADD_INS (cfg->cbb, ins);
2302 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2304 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2305 ins->dreg = mono_alloc_ireg (cfg);
2306 ins->sreg1 = in->dreg;
2307 MONO_ADD_INS (cfg->cbb, ins);
2308 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2312 cfg->param_area = MAX (cfg->param_area, 8);
2313 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2314 creg = mono_alloc_ireg (cfg);
2315 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2316 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2317 creg = mono_alloc_ireg (cfg);
2318 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2319 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2322 cfg->flags |= MONO_CFG_HAS_FPOUT;
2324 MONO_INST_NEW (cfg, ins, OP_MOVE);
2325 ins->dreg = mono_alloc_ireg (cfg);
2326 ins->sreg1 = in->dreg;
2327 MONO_ADD_INS (cfg->cbb, ins);
2329 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2332 case RegTypeStructByVal:
2333 case RegTypeGSharedVtInReg:
2334 case RegTypeGSharedVtOnStack:
2336 case RegTypeStructByAddr:
2337 case RegTypeStructByAddrOnStack:
2338 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2339 ins->opcode = OP_OUTARG_VT;
2340 ins->sreg1 = in->dreg;
2341 ins->klass = in->klass;
2342 ins->inst_p0 = call;
2343 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2344 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2345 mono_call_inst_add_outarg_vt (cfg, call, ins);
2346 MONO_ADD_INS (cfg->cbb, ins);
2349 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2350 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2351 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2352 if (t->type == MONO_TYPE_R8) {
2353 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2356 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2358 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2361 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2364 case RegTypeBaseGen:
2365 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2366 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? MONO_LVREG_LS (in->dreg) : MONO_LVREG_MS (in->dreg));
2367 MONO_INST_NEW (cfg, ins, OP_MOVE);
2368 ins->dreg = mono_alloc_ireg (cfg);
2369 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? MONO_LVREG_MS (in->dreg) : MONO_LVREG_LS (in->dreg);
2370 MONO_ADD_INS (cfg->cbb, ins);
2371 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2372 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2375 /* This should work for soft-float as well */
2377 cfg->param_area = MAX (cfg->param_area, 8);
2378 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2379 creg = mono_alloc_ireg (cfg);
2380 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2381 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2382 creg = mono_alloc_ireg (cfg);
2383 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2384 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2385 cfg->flags |= MONO_CFG_HAS_FPOUT;
2387 g_assert_not_reached ();
2391 int fdreg = mono_alloc_freg (cfg);
2393 if (ainfo->size == 8) {
2394 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2395 ins->sreg1 = in->dreg;
2397 MONO_ADD_INS (cfg->cbb, ins);
2399 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2404 * Mono's register allocator doesn't speak single-precision registers that
2405 * overlap double-precision registers (i.e. armhf). So we have to work around
2406 * the register allocator and load the value from memory manually.
2408 * So we create a variable for the float argument and an instruction to store
2409 * the argument into the variable. We then store the list of these arguments
2410 * in call->float_args. This list is then used by emit_float_args later to
2411 * pass the arguments in the various call opcodes.
2413 * This is not very nice, and we should really try to fix the allocator.
2416 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2418 /* Make sure the instruction isn't seen as pointless and removed.
2420 float_arg->flags |= MONO_INST_VOLATILE;
2422 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2424 /* We use the dreg to look up the instruction later. The hreg is used to
2425 * emit the instruction that loads the value into the FP reg.
2427 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2428 fad->vreg = float_arg->dreg;
2429 fad->hreg = ainfo->reg;
2431 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2434 call->used_iregs |= 1 << ainfo->reg;
2435 cfg->flags |= MONO_CFG_HAS_FPOUT;
2439 g_assert_not_reached ();
2443 /* Handle the case where there are no implicit arguments */
2444 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2445 emit_sig_cookie (cfg, call, cinfo);
2447 call->call_info = cinfo;
2448 call->stack_usage = cinfo->stack_usage;
2452 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2458 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2459 ins->dreg = mono_alloc_freg (cfg);
2460 ins->sreg1 = arg->dreg;
2461 MONO_ADD_INS (cfg->cbb, ins);
2462 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2465 g_assert_not_reached ();
2471 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2473 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2475 ArgInfo *ainfo = ins->inst_p1;
2476 int ovf_size = ainfo->vtsize;
2477 int doffset = ainfo->offset;
2478 int struct_size = ainfo->struct_size;
2479 int i, soffset, dreg, tmpreg;
2481 switch (ainfo->storage) {
2482 case RegTypeGSharedVtInReg:
2483 case RegTypeStructByAddr:
2485 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2487 case RegTypeGSharedVtOnStack:
2488 case RegTypeStructByAddrOnStack:
2489 /* Pass by addr on stack */
2490 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2493 for (i = 0; i < ainfo->nregs; ++i) {
2494 if (ainfo->esize == 4)
2495 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2497 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2498 load->dreg = mono_alloc_freg (cfg);
2499 load->inst_basereg = src->dreg;
2500 load->inst_offset = i * ainfo->esize;
2501 MONO_ADD_INS (cfg->cbb, load);
2503 if (ainfo->esize == 4) {
2506 /* See RegTypeFP in mono_arch_emit_call () */
2507 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2508 float_arg->flags |= MONO_INST_VOLATILE;
2509 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2511 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2512 fad->vreg = float_arg->dreg;
2513 fad->hreg = ainfo->reg + i;
2515 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2517 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2523 for (i = 0; i < ainfo->size; ++i) {
2524 dreg = mono_alloc_ireg (cfg);
2525 switch (struct_size) {
2527 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2530 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2533 tmpreg = mono_alloc_ireg (cfg);
2534 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2535 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2536 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2537 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2538 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2539 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2540 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2543 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2546 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2547 soffset += sizeof (gpointer);
2548 struct_size -= sizeof (gpointer);
2550 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2552 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2558 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2560 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2563 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2566 if (COMPILE_LLVM (cfg)) {
2567 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2569 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2570 ins->sreg1 = MONO_LVREG_LS (val->dreg);
2571 ins->sreg2 = MONO_LVREG_MS (val->dreg);
2572 MONO_ADD_INS (cfg->cbb, ins);
2577 case MONO_ARM_FPU_NONE:
2578 if (ret->type == MONO_TYPE_R8) {
2581 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2582 ins->dreg = cfg->ret->dreg;
2583 ins->sreg1 = val->dreg;
2584 MONO_ADD_INS (cfg->cbb, ins);
2587 if (ret->type == MONO_TYPE_R4) {
2588 /* Already converted to an int in method_to_ir () */
2589 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2593 case MONO_ARM_FPU_VFP:
2594 case MONO_ARM_FPU_VFP_HARD:
2595 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2598 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2599 ins->dreg = cfg->ret->dreg;
2600 ins->sreg1 = val->dreg;
2601 MONO_ADD_INS (cfg->cbb, ins);
2606 g_assert_not_reached ();
2610 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2613 #endif /* #ifndef DISABLE_JIT */
2616 mono_arch_is_inst_imm (gint64 imm)
2622 MonoMethodSignature *sig;
2625 MonoType **param_types;
2629 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2633 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2636 switch (cinfo->ret.storage) {
2638 case RegTypeGeneral:
2639 case RegTypeIRegPair:
2640 case RegTypeStructByAddr:
2651 for (i = 0; i < cinfo->nargs; ++i) {
2652 ArgInfo *ainfo = &cinfo->args [i];
2655 switch (ainfo->storage) {
2656 case RegTypeGeneral:
2657 case RegTypeIRegPair:
2658 case RegTypeBaseGen:
2662 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2665 case RegTypeStructByVal:
2666 if (ainfo->size == 0)
2667 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2669 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2670 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2678 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2679 for (i = 0; i < sig->param_count; ++i) {
2680 MonoType *t = sig->params [i];
2685 t = mini_get_underlying_type (t);
2708 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2710 ArchDynCallInfo *info;
2714 cinfo = get_call_info (NULL, sig);
2716 if (!dyn_call_supported (cinfo, sig)) {
2721 info = g_new0 (ArchDynCallInfo, 1);
2722 // FIXME: Preprocess the info to speed up start_dyn_call ()
2724 info->cinfo = cinfo;
2725 info->rtype = mini_get_underlying_type (sig->ret);
2726 info->param_types = g_new0 (MonoType*, sig->param_count);
2727 for (i = 0; i < sig->param_count; ++i)
2728 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2730 return (MonoDynCallInfo*)info;
2734 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2736 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2738 g_free (ainfo->cinfo);
2743 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2745 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2746 DynCallArgs *p = (DynCallArgs*)buf;
2747 int arg_index, greg, i, j, pindex;
2748 MonoMethodSignature *sig = dinfo->sig;
2750 g_assert (buf_len >= sizeof (DynCallArgs));
2760 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2761 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2766 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2767 p->regs [greg ++] = (mgreg_t)ret;
2769 for (i = pindex; i < sig->param_count; i++) {
2770 MonoType *t = dinfo->param_types [i];
2771 gpointer *arg = args [arg_index ++];
2772 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2775 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2777 } else if (ainfo->storage == RegTypeFP) {
2778 } else if (ainfo->storage == RegTypeBase) {
2779 slot = PARAM_REGS + (ainfo->offset / 4);
2780 } else if (ainfo->storage == RegTypeBaseGen) {
2781 /* slot + 1 is the first stack slot, so the code below will work */
2784 g_assert_not_reached ();
2788 p->regs [slot] = (mgreg_t)*arg;
2793 case MONO_TYPE_OBJECT:
2797 p->regs [slot] = (mgreg_t)*arg;
2800 p->regs [slot] = *(guint8*)arg;
2803 p->regs [slot] = *(gint8*)arg;
2806 p->regs [slot] = *(gint16*)arg;
2809 p->regs [slot] = *(guint16*)arg;
2812 p->regs [slot] = *(gint32*)arg;
2815 p->regs [slot] = *(guint32*)arg;
2819 p->regs [slot ++] = (mgreg_t)arg [0];
2820 p->regs [slot] = (mgreg_t)arg [1];
2823 if (ainfo->storage == RegTypeFP) {
2824 float f = *(float*)arg;
2825 p->fpregs [ainfo->reg / 2] = *(double*)&f;
2828 p->regs [slot] = *(mgreg_t*)arg;
2832 if (ainfo->storage == RegTypeFP) {
2833 p->fpregs [ainfo->reg / 2] = *(double*)arg;
2836 p->regs [slot ++] = (mgreg_t)arg [0];
2837 p->regs [slot] = (mgreg_t)arg [1];
2840 case MONO_TYPE_GENERICINST:
2841 if (MONO_TYPE_IS_REFERENCE (t)) {
2842 p->regs [slot] = (mgreg_t)*arg;
2845 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2846 MonoClass *klass = mono_class_from_mono_type (t);
2847 guint8 *nullable_buf;
2850 size = mono_class_value_size (klass, NULL);
2851 nullable_buf = g_alloca (size);
2852 g_assert (nullable_buf);
2854 /* The argument pointed to by arg is either a boxed vtype or null */
2855 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2857 arg = (gpointer*)nullable_buf;
2863 case MONO_TYPE_VALUETYPE:
2864 g_assert (ainfo->storage == RegTypeStructByVal);
2866 if (ainfo->size == 0)
2867 slot = PARAM_REGS + (ainfo->offset / 4);
2871 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2872 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2875 g_assert_not_reached ();
2881 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2883 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2884 DynCallArgs *p = (DynCallArgs*)buf;
2885 MonoType *ptype = ainfo->rtype;
2886 guint8 *ret = p->ret;
2887 mgreg_t res = p->res;
2888 mgreg_t res2 = p->res2;
2890 switch (ptype->type) {
2891 case MONO_TYPE_VOID:
2892 *(gpointer*)ret = NULL;
2894 case MONO_TYPE_OBJECT:
2898 *(gpointer*)ret = (gpointer)res;
2904 *(guint8*)ret = res;
2907 *(gint16*)ret = res;
2910 *(guint16*)ret = res;
2913 *(gint32*)ret = res;
2916 *(guint32*)ret = res;
2920 /* This handles endianness as well */
2921 ((gint32*)ret) [0] = res;
2922 ((gint32*)ret) [1] = res2;
2924 case MONO_TYPE_GENERICINST:
2925 if (MONO_TYPE_IS_REFERENCE (ptype)) {
2926 *(gpointer*)ret = (gpointer)res;
2931 case MONO_TYPE_VALUETYPE:
2932 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
2938 *(float*)ret = *(float*)&p->fpregs [0];
2940 *(float*)ret = *(float*)&res;
2942 case MONO_TYPE_R8: {
2946 if (IS_HARD_FLOAT) {
2947 *(double*)ret = p->fpregs [0];
2952 *(double*)ret = *(double*)®s;
2957 g_assert_not_reached ();
2964 * Allow tracing to work with this interface (with an optional argument)
2968 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2972 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2973 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2974 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2975 code = emit_call_reg (code, ARMREG_R2);
2989 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2992 int save_mode = SAVE_NONE;
2994 MonoMethod *method = cfg->method;
2995 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
2996 int rtype = ret_type->type;
2997 int save_offset = cfg->param_area;
3001 offset = code - cfg->native_code;
3002 /* we need about 16 instructions */
3003 if (offset > (cfg->code_size - 16 * 4)) {
3004 cfg->code_size *= 2;
3005 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3006 code = cfg->native_code + offset;
3009 case MONO_TYPE_VOID:
3010 /* special case string .ctor icall */
3011 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3012 save_mode = SAVE_ONE;
3014 save_mode = SAVE_NONE;
3018 save_mode = SAVE_TWO;
3022 save_mode = SAVE_ONE_FP;
3024 save_mode = SAVE_ONE;
3028 save_mode = SAVE_TWO_FP;
3030 save_mode = SAVE_TWO;
3032 case MONO_TYPE_GENERICINST:
3033 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3034 save_mode = SAVE_ONE;
3038 case MONO_TYPE_VALUETYPE:
3039 save_mode = SAVE_STRUCT;
3042 save_mode = SAVE_ONE;
3046 switch (save_mode) {
3048 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3049 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3050 if (enable_arguments) {
3051 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3052 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3056 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3057 if (enable_arguments) {
3058 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3062 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3063 if (enable_arguments) {
3064 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3068 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3069 if (enable_arguments) {
3070 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3074 if (enable_arguments) {
3075 /* FIXME: get the actual address */
3076 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3084 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3085 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3086 code = emit_call_reg (code, ARMREG_IP);
3088 switch (save_mode) {
3090 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3091 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3094 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3097 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3100 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3111 * The immediate field for cond branches is big enough for all reasonable methods
3113 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3114 if (0 && ins->inst_true_bb->native_offset) { \
3115 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3117 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3118 ARM_B_COND (code, (condcode), 0); \
3121 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3123 /* emit an exception if condition is fail
3125 * We assign the extra code used to throw the implicit exceptions
3126 * to cfg->bb_exit as far as the big branch handling is concerned
3128 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3130 mono_add_patch_info (cfg, code - cfg->native_code, \
3131 MONO_PATCH_INFO_EXC, exc_name); \
3132 ARM_BL_COND (code, (condcode), 0); \
3135 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3138 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3143 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3147 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3148 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3150 switch (ins->opcode) {
3153 /* Already done by an arch-independent pass */
3155 case OP_LOAD_MEMBASE:
3156 case OP_LOADI4_MEMBASE:
3158 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3159 * OP_LOAD_MEMBASE offset(basereg), reg
3161 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3162 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3163 ins->inst_basereg == last_ins->inst_destbasereg &&
3164 ins->inst_offset == last_ins->inst_offset) {
3165 if (ins->dreg == last_ins->sreg1) {
3166 MONO_DELETE_INS (bb, ins);
3169 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3170 ins->opcode = OP_MOVE;
3171 ins->sreg1 = last_ins->sreg1;
3175 * Note: reg1 must be different from the basereg in the second load
3176 * OP_LOAD_MEMBASE offset(basereg), reg1
3177 * OP_LOAD_MEMBASE offset(basereg), reg2
3179 * OP_LOAD_MEMBASE offset(basereg), reg1
3180 * OP_MOVE reg1, reg2
3182 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3183 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3184 ins->inst_basereg != last_ins->dreg &&
3185 ins->inst_basereg == last_ins->inst_basereg &&
3186 ins->inst_offset == last_ins->inst_offset) {
3188 if (ins->dreg == last_ins->dreg) {
3189 MONO_DELETE_INS (bb, ins);
3192 ins->opcode = OP_MOVE;
3193 ins->sreg1 = last_ins->dreg;
3196 //g_assert_not_reached ();
3200 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3201 * OP_LOAD_MEMBASE offset(basereg), reg
3203 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3204 * OP_ICONST reg, imm
3206 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3207 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3208 ins->inst_basereg == last_ins->inst_destbasereg &&
3209 ins->inst_offset == last_ins->inst_offset) {
3210 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3211 ins->opcode = OP_ICONST;
3212 ins->inst_c0 = last_ins->inst_imm;
3213 g_assert_not_reached (); // check this rule
3217 case OP_LOADU1_MEMBASE:
3218 case OP_LOADI1_MEMBASE:
3219 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3220 ins->inst_basereg == last_ins->inst_destbasereg &&
3221 ins->inst_offset == last_ins->inst_offset) {
3222 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3223 ins->sreg1 = last_ins->sreg1;
3226 case OP_LOADU2_MEMBASE:
3227 case OP_LOADI2_MEMBASE:
3228 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3229 ins->inst_basereg == last_ins->inst_destbasereg &&
3230 ins->inst_offset == last_ins->inst_offset) {
3231 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3232 ins->sreg1 = last_ins->sreg1;
3236 ins->opcode = OP_MOVE;
3240 if (ins->dreg == ins->sreg1) {
3241 MONO_DELETE_INS (bb, ins);
3245 * OP_MOVE sreg, dreg
3246 * OP_MOVE dreg, sreg
3248 if (last_ins && last_ins->opcode == OP_MOVE &&
3249 ins->sreg1 == last_ins->dreg &&
3250 ins->dreg == last_ins->sreg1) {
3251 MONO_DELETE_INS (bb, ins);
3260 * the branch_cc_table should maintain the order of these
3274 branch_cc_table [] = {
3288 #define ADD_NEW_INS(cfg,dest,op) do { \
3289 MONO_INST_NEW ((cfg), (dest), (op)); \
3290 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3294 map_to_reg_reg_op (int op)
3303 case OP_COMPARE_IMM:
3305 case OP_ICOMPARE_IMM:
3319 case OP_LOAD_MEMBASE:
3320 return OP_LOAD_MEMINDEX;
3321 case OP_LOADI4_MEMBASE:
3322 return OP_LOADI4_MEMINDEX;
3323 case OP_LOADU4_MEMBASE:
3324 return OP_LOADU4_MEMINDEX;
3325 case OP_LOADU1_MEMBASE:
3326 return OP_LOADU1_MEMINDEX;
3327 case OP_LOADI2_MEMBASE:
3328 return OP_LOADI2_MEMINDEX;
3329 case OP_LOADU2_MEMBASE:
3330 return OP_LOADU2_MEMINDEX;
3331 case OP_LOADI1_MEMBASE:
3332 return OP_LOADI1_MEMINDEX;
3333 case OP_STOREI1_MEMBASE_REG:
3334 return OP_STOREI1_MEMINDEX;
3335 case OP_STOREI2_MEMBASE_REG:
3336 return OP_STOREI2_MEMINDEX;
3337 case OP_STOREI4_MEMBASE_REG:
3338 return OP_STOREI4_MEMINDEX;
3339 case OP_STORE_MEMBASE_REG:
3340 return OP_STORE_MEMINDEX;
3341 case OP_STORER4_MEMBASE_REG:
3342 return OP_STORER4_MEMINDEX;
3343 case OP_STORER8_MEMBASE_REG:
3344 return OP_STORER8_MEMINDEX;
3345 case OP_STORE_MEMBASE_IMM:
3346 return OP_STORE_MEMBASE_REG;
3347 case OP_STOREI1_MEMBASE_IMM:
3348 return OP_STOREI1_MEMBASE_REG;
3349 case OP_STOREI2_MEMBASE_IMM:
3350 return OP_STOREI2_MEMBASE_REG;
3351 case OP_STOREI4_MEMBASE_IMM:
3352 return OP_STOREI4_MEMBASE_REG;
3354 g_assert_not_reached ();
3358 * Remove from the instruction list the instructions that can't be
3359 * represented with very simple instructions with no register
3363 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3365 MonoInst *ins, *temp, *last_ins = NULL;
3366 int rot_amount, imm8, low_imm;
3368 MONO_BB_FOR_EACH_INS (bb, ins) {
3370 switch (ins->opcode) {
3374 case OP_COMPARE_IMM:
3375 case OP_ICOMPARE_IMM:
3389 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3390 int opcode2 = mono_op_imm_to_op (ins->opcode);
3391 ADD_NEW_INS (cfg, temp, OP_ICONST);
3392 temp->inst_c0 = ins->inst_imm;
3393 temp->dreg = mono_alloc_ireg (cfg);
3394 ins->sreg2 = temp->dreg;
3396 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3397 ins->opcode = opcode2;
3399 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3405 if (ins->inst_imm == 1) {
3406 ins->opcode = OP_MOVE;
3409 if (ins->inst_imm == 0) {
3410 ins->opcode = OP_ICONST;
3414 imm8 = mono_is_power_of_two (ins->inst_imm);
3416 ins->opcode = OP_SHL_IMM;
3417 ins->inst_imm = imm8;
3420 ADD_NEW_INS (cfg, temp, OP_ICONST);
3421 temp->inst_c0 = ins->inst_imm;
3422 temp->dreg = mono_alloc_ireg (cfg);
3423 ins->sreg2 = temp->dreg;
3424 ins->opcode = OP_IMUL;
3430 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3431 /* ARM sets the C flag to 1 if there was _no_ overflow */
3432 ins->next->opcode = OP_COND_EXC_NC;
3435 case OP_IDIV_UN_IMM:
3437 case OP_IREM_UN_IMM: {
3438 int opcode2 = mono_op_imm_to_op (ins->opcode);
3439 ADD_NEW_INS (cfg, temp, OP_ICONST);
3440 temp->inst_c0 = ins->inst_imm;
3441 temp->dreg = mono_alloc_ireg (cfg);
3442 ins->sreg2 = temp->dreg;
3444 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3445 ins->opcode = opcode2;
3448 case OP_LOCALLOC_IMM:
3449 ADD_NEW_INS (cfg, temp, OP_ICONST);
3450 temp->inst_c0 = ins->inst_imm;
3451 temp->dreg = mono_alloc_ireg (cfg);
3452 ins->sreg1 = temp->dreg;
3453 ins->opcode = OP_LOCALLOC;
3455 case OP_LOAD_MEMBASE:
3456 case OP_LOADI4_MEMBASE:
3457 case OP_LOADU4_MEMBASE:
3458 case OP_LOADU1_MEMBASE:
3459 /* we can do two things: load the immed in a register
3460 * and use an indexed load, or see if the immed can be
3461 * represented as an ad_imm + a load with a smaller offset
3462 * that fits. We just do the first for now, optimize later.
3464 if (arm_is_imm12 (ins->inst_offset))
3466 ADD_NEW_INS (cfg, temp, OP_ICONST);
3467 temp->inst_c0 = ins->inst_offset;
3468 temp->dreg = mono_alloc_ireg (cfg);
3469 ins->sreg2 = temp->dreg;
3470 ins->opcode = map_to_reg_reg_op (ins->opcode);
3472 case OP_LOADI2_MEMBASE:
3473 case OP_LOADU2_MEMBASE:
3474 case OP_LOADI1_MEMBASE:
3475 if (arm_is_imm8 (ins->inst_offset))
3477 ADD_NEW_INS (cfg, temp, OP_ICONST);
3478 temp->inst_c0 = ins->inst_offset;
3479 temp->dreg = mono_alloc_ireg (cfg);
3480 ins->sreg2 = temp->dreg;
3481 ins->opcode = map_to_reg_reg_op (ins->opcode);
3483 case OP_LOADR4_MEMBASE:
3484 case OP_LOADR8_MEMBASE:
3485 if (arm_is_fpimm8 (ins->inst_offset))
3487 low_imm = ins->inst_offset & 0x1ff;
3488 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3489 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3490 temp->inst_imm = ins->inst_offset & ~0x1ff;
3491 temp->sreg1 = ins->inst_basereg;
3492 temp->dreg = mono_alloc_ireg (cfg);
3493 ins->inst_basereg = temp->dreg;
3494 ins->inst_offset = low_imm;
3498 ADD_NEW_INS (cfg, temp, OP_ICONST);
3499 temp->inst_c0 = ins->inst_offset;
3500 temp->dreg = mono_alloc_ireg (cfg);
3502 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3503 add_ins->sreg1 = ins->inst_basereg;
3504 add_ins->sreg2 = temp->dreg;
3505 add_ins->dreg = mono_alloc_ireg (cfg);
3507 ins->inst_basereg = add_ins->dreg;
3508 ins->inst_offset = 0;
3511 case OP_STORE_MEMBASE_REG:
3512 case OP_STOREI4_MEMBASE_REG:
3513 case OP_STOREI1_MEMBASE_REG:
3514 if (arm_is_imm12 (ins->inst_offset))
3516 ADD_NEW_INS (cfg, temp, OP_ICONST);
3517 temp->inst_c0 = ins->inst_offset;
3518 temp->dreg = mono_alloc_ireg (cfg);
3519 ins->sreg2 = temp->dreg;
3520 ins->opcode = map_to_reg_reg_op (ins->opcode);
3522 case OP_STOREI2_MEMBASE_REG:
3523 if (arm_is_imm8 (ins->inst_offset))
3525 ADD_NEW_INS (cfg, temp, OP_ICONST);
3526 temp->inst_c0 = ins->inst_offset;
3527 temp->dreg = mono_alloc_ireg (cfg);
3528 ins->sreg2 = temp->dreg;
3529 ins->opcode = map_to_reg_reg_op (ins->opcode);
3531 case OP_STORER4_MEMBASE_REG:
3532 case OP_STORER8_MEMBASE_REG:
3533 if (arm_is_fpimm8 (ins->inst_offset))
3535 low_imm = ins->inst_offset & 0x1ff;
3536 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3537 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3538 temp->inst_imm = ins->inst_offset & ~0x1ff;
3539 temp->sreg1 = ins->inst_destbasereg;
3540 temp->dreg = mono_alloc_ireg (cfg);
3541 ins->inst_destbasereg = temp->dreg;
3542 ins->inst_offset = low_imm;
3546 ADD_NEW_INS (cfg, temp, OP_ICONST);
3547 temp->inst_c0 = ins->inst_offset;
3548 temp->dreg = mono_alloc_ireg (cfg);
3550 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3551 add_ins->sreg1 = ins->inst_destbasereg;
3552 add_ins->sreg2 = temp->dreg;
3553 add_ins->dreg = mono_alloc_ireg (cfg);
3555 ins->inst_destbasereg = add_ins->dreg;
3556 ins->inst_offset = 0;
3559 case OP_STORE_MEMBASE_IMM:
3560 case OP_STOREI1_MEMBASE_IMM:
3561 case OP_STOREI2_MEMBASE_IMM:
3562 case OP_STOREI4_MEMBASE_IMM:
3563 ADD_NEW_INS (cfg, temp, OP_ICONST);
3564 temp->inst_c0 = ins->inst_imm;
3565 temp->dreg = mono_alloc_ireg (cfg);
3566 ins->sreg1 = temp->dreg;
3567 ins->opcode = map_to_reg_reg_op (ins->opcode);
3569 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3572 gboolean swap = FALSE;
3576 /* Optimized away */
3581 /* Some fp compares require swapped operands */
3582 switch (ins->next->opcode) {
3584 ins->next->opcode = OP_FBLT;
3588 ins->next->opcode = OP_FBLT_UN;
3592 ins->next->opcode = OP_FBGE;
3596 ins->next->opcode = OP_FBGE_UN;
3604 ins->sreg1 = ins->sreg2;
3613 bb->last_ins = last_ins;
3614 bb->max_vreg = cfg->next_vreg;
3618 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3622 if (long_ins->opcode == OP_LNEG) {
3624 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), 0);
3625 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
3631 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3633 /* sreg is a float, dreg is an integer reg */
3635 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3637 ARM_TOSIZD (code, vfp_scratch1, sreg);
3639 ARM_TOUIZD (code, vfp_scratch1, sreg);
3640 ARM_FMRS (code, dreg, vfp_scratch1);
3641 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3645 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3646 else if (size == 2) {
3647 ARM_SHL_IMM (code, dreg, dreg, 16);
3648 ARM_SHR_IMM (code, dreg, dreg, 16);
3652 ARM_SHL_IMM (code, dreg, dreg, 24);
3653 ARM_SAR_IMM (code, dreg, dreg, 24);
3654 } else if (size == 2) {
3655 ARM_SHL_IMM (code, dreg, dreg, 16);
3656 ARM_SAR_IMM (code, dreg, dreg, 16);
3663 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3665 /* sreg is a float, dreg is an integer reg */
3667 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3669 ARM_TOSIZS (code, vfp_scratch1, sreg);
3671 ARM_TOUIZS (code, vfp_scratch1, sreg);
3672 ARM_FMRS (code, dreg, vfp_scratch1);
3673 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3677 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3678 else if (size == 2) {
3679 ARM_SHL_IMM (code, dreg, dreg, 16);
3680 ARM_SHR_IMM (code, dreg, dreg, 16);
3684 ARM_SHL_IMM (code, dreg, dreg, 24);
3685 ARM_SAR_IMM (code, dreg, dreg, 24);
3686 } else if (size == 2) {
3687 ARM_SHL_IMM (code, dreg, dreg, 16);
3688 ARM_SAR_IMM (code, dreg, dreg, 16);
3694 #endif /* #ifndef DISABLE_JIT */
3696 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3699 emit_thunk (guint8 *code, gconstpointer target)
3703 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3704 if (thumb_supported)
3705 ARM_BX (code, ARMREG_IP);
3707 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3708 *(guint32*)code = (guint32)target;
3710 mono_arch_flush_icache (p, code - p);
3714 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3716 MonoJitInfo *ji = NULL;
3717 MonoThunkJitInfo *info;
3720 guint8 *orig_target;
3721 guint8 *target_thunk;
3724 domain = mono_domain_get ();
3728 * This can be called multiple times during JITting,
3729 * save the current position in cfg->arch to avoid
3730 * doing a O(n^2) search.
3732 if (!cfg->arch.thunks) {
3733 cfg->arch.thunks = cfg->thunks;
3734 cfg->arch.thunks_size = cfg->thunk_area;
3736 thunks = cfg->arch.thunks;
3737 thunks_size = cfg->arch.thunks_size;
3739 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3740 g_assert_not_reached ();
3743 g_assert (*(guint32*)thunks == 0);
3744 emit_thunk (thunks, target);
3745 arm_patch (code, thunks);
3747 cfg->arch.thunks += THUNK_SIZE;
3748 cfg->arch.thunks_size -= THUNK_SIZE;
3750 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3752 info = mono_jit_info_get_thunk_info (ji);
3755 thunks = (guint8*)ji->code_start + info->thunks_offset;
3756 thunks_size = info->thunks_size;
3758 orig_target = mono_arch_get_call_target (code + 4);
3760 mono_mini_arch_lock ();
3762 target_thunk = NULL;
3763 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3764 /* The call already points to a thunk, because of trampolines etc. */
3765 target_thunk = orig_target;
3767 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3768 if (((guint32*)p) [0] == 0) {
3772 } else if (((guint32*)p) [2] == (guint32)target) {
3773 /* Thunk already points to target */
3780 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3782 if (!target_thunk) {
3783 mono_mini_arch_unlock ();
3784 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3785 g_assert_not_reached ();
3788 emit_thunk (target_thunk, target);
3789 arm_patch (code, target_thunk);
3790 mono_arch_flush_icache (code, 4);
3792 mono_mini_arch_unlock ();
3797 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3799 guint32 *code32 = (void*)code;
3800 guint32 ins = *code32;
3801 guint32 prim = (ins >> 25) & 7;
3802 guint32 tval = GPOINTER_TO_UINT (target);
3804 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3805 if (prim == 5) { /* 101b */
3806 /* the diff starts 8 bytes from the branch opcode */
3807 gint diff = target - code - 8;
3809 gint tmask = 0xffffffff;
3810 if (tval & 1) { /* entering thumb mode */
3811 diff = target - 1 - code - 8;
3812 g_assert (thumb_supported);
3813 tbits = 0xf << 28; /* bl->blx bit pattern */
3814 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3815 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3819 tmask = ~(1 << 24); /* clear the link bit */
3820 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3825 if (diff <= 33554431) {
3827 ins = (ins & 0xff000000) | diff;
3829 *code32 = ins | tbits;
3833 /* diff between 0 and -33554432 */
3834 if (diff >= -33554432) {
3836 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3838 *code32 = ins | tbits;
3843 handle_thunk (cfg, domain, code, target);
3848 * The alternative call sequences looks like this:
3850 * ldr ip, [pc] // loads the address constant
3851 * b 1f // jumps around the constant
3852 * address constant embedded in the code
3857 * There are two cases for patching:
3858 * a) at the end of method emission: in this case code points to the start
3859 * of the call sequence
3860 * b) during runtime patching of the call site: in this case code points
3861 * to the mov pc, ip instruction
3863 * We have to handle also the thunk jump code sequence:
3867 * address constant // execution never reaches here
3869 if ((ins & 0x0ffffff0) == 0x12fff10) {
3870 /* Branch and exchange: the address is constructed in a reg
3871 * We can patch BX when the code sequence is the following:
3872 * ldr ip, [pc, #0] ; 0x8
3879 guint8 *emit = (guint8*)ccode;
3880 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3882 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3883 ARM_BX (emit, ARMREG_IP);
3885 /*patching from magic trampoline*/
3886 if (ins == ccode [3]) {
3887 g_assert (code32 [-4] == ccode [0]);
3888 g_assert (code32 [-3] == ccode [1]);
3889 g_assert (code32 [-1] == ccode [2]);
3890 code32 [-2] = (guint32)target;
3893 /*patching from JIT*/
3894 if (ins == ccode [0]) {
3895 g_assert (code32 [1] == ccode [1]);
3896 g_assert (code32 [3] == ccode [2]);
3897 g_assert (code32 [4] == ccode [3]);
3898 code32 [2] = (guint32)target;
3901 g_assert_not_reached ();
3902 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3910 guint8 *emit = (guint8*)ccode;
3911 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3913 ARM_BLX_REG (emit, ARMREG_IP);
3915 g_assert (code32 [-3] == ccode [0]);
3916 g_assert (code32 [-2] == ccode [1]);
3917 g_assert (code32 [0] == ccode [2]);
3919 code32 [-1] = (guint32)target;
3922 guint32 *tmp = ccode;
3923 guint8 *emit = (guint8*)tmp;
3924 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3925 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3926 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3927 ARM_BX (emit, ARMREG_IP);
3928 if (ins == ccode [2]) {
3929 g_assert_not_reached (); // should be -2 ...
3930 code32 [-1] = (guint32)target;
3933 if (ins == ccode [0]) {
3934 /* handles both thunk jump code and the far call sequence */
3935 code32 [2] = (guint32)target;
3938 g_assert_not_reached ();
3940 // g_print ("patched with 0x%08x\n", ins);
3944 arm_patch (guchar *code, const guchar *target)
3946 arm_patch_general (NULL, NULL, code, target);
3950 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3951 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3952 * to be used with the emit macros.
3953 * Return -1 otherwise.
3956 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3959 for (i = 0; i < 31; i+= 2) {
3960 res = (val << (32 - i)) | (val >> i);
3963 *rot_amount = i? 32 - i: 0;
3970 * Emits in code a sequence of instructions that load the value 'val'
3971 * into the dreg register. Uses at most 4 instructions.
3974 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3976 int imm8, rot_amount;
3978 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3979 /* skip the constant pool */
3985 if (mini_get_debug_options()->single_imm_size && v7_supported) {
3986 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3987 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3991 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
3992 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
3993 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
3994 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
3997 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3999 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4003 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4005 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4007 if (val & 0xFF0000) {
4008 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4010 if (val & 0xFF000000) {
4011 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4013 } else if (val & 0xFF00) {
4014 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4015 if (val & 0xFF0000) {
4016 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4018 if (val & 0xFF000000) {
4019 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4021 } else if (val & 0xFF0000) {
4022 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4023 if (val & 0xFF000000) {
4024 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4027 //g_assert_not_reached ();
4033 mono_arm_thumb_supported (void)
4035 return thumb_supported;
4041 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4046 call = (MonoCallInst*)ins;
4047 cinfo = call->call_info;
4049 switch (cinfo->ret.storage) {
4050 case RegTypeStructByVal:
4052 MonoInst *loc = cfg->arch.vret_addr_loc;
4055 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
4056 /* The JIT treats this as a normal call */
4060 /* Load the destination address */
4061 g_assert (loc && loc->opcode == OP_REGOFFSET);
4063 if (arm_is_imm12 (loc->inst_offset)) {
4064 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4066 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4067 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4070 if (cinfo->ret.storage == RegTypeStructByVal) {
4071 int rsize = cinfo->ret.struct_size;
4073 for (i = 0; i < cinfo->ret.nregs; ++i) {
4074 g_assert (rsize >= 0);
4079 ARM_STRB_IMM (code, i, ARMREG_LR, i * 4);
4082 ARM_STRH_IMM (code, i, ARMREG_LR, i * 4);
4085 ARM_STR_IMM (code, i, ARMREG_LR, i * 4);
4091 for (i = 0; i < cinfo->ret.nregs; ++i) {
4092 if (cinfo->ret.esize == 4)
4093 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4095 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4104 switch (ins->opcode) {
4107 case OP_FCALL_MEMBASE:
4109 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4110 if (sig_ret->type == MONO_TYPE_R4) {
4111 if (IS_HARD_FLOAT) {
4112 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4114 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4115 ARM_CVTS (code, ins->dreg, ins->dreg);
4118 if (IS_HARD_FLOAT) {
4119 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4121 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4128 case OP_RCALL_MEMBASE: {
4133 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4134 g_assert (sig_ret->type == MONO_TYPE_R4);
4135 if (IS_HARD_FLOAT) {
4136 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4138 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4139 ARM_CPYS (code, ins->dreg, ins->dreg);
4151 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4156 guint8 *code = cfg->native_code + cfg->code_len;
4157 MonoInst *last_ins = NULL;
4158 guint last_offset = 0;
4160 int imm8, rot_amount;
4162 /* we don't align basic blocks of loops on arm */
4164 if (cfg->verbose_level > 2)
4165 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4167 cpos = bb->max_offset;
4169 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4170 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4171 //g_assert (!mono_compile_aot);
4174 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4175 /* this is not thread save, but good enough */
4176 /* fixme: howto handle overflows? */
4177 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4180 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4181 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4182 (gpointer)"mono_break");
4183 code = emit_call_seq (cfg, code);
4186 MONO_BB_FOR_EACH_INS (bb, ins) {
4187 offset = code - cfg->native_code;
4189 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4191 if (offset > (cfg->code_size - max_len - 16)) {
4192 cfg->code_size *= 2;
4193 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4194 code = cfg->native_code + offset;
4196 // if (ins->cil_code)
4197 // g_print ("cil code\n");
4198 mono_debug_record_line_number (cfg, ins, offset);
4200 switch (ins->opcode) {
4201 case OP_MEMORY_BARRIER:
4203 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4204 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4208 code = emit_tls_get (code, ins->dreg, ins->inst_offset);
4211 code = emit_tls_set (code, ins->sreg1, ins->inst_offset);
4213 case OP_ATOMIC_EXCHANGE_I4:
4214 case OP_ATOMIC_CAS_I4:
4215 case OP_ATOMIC_ADD_I4: {
4219 g_assert (v7_supported);
4222 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4224 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4226 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4230 g_assert (cfg->arch.atomic_tmp_offset != -1);
4231 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4233 switch (ins->opcode) {
4234 case OP_ATOMIC_EXCHANGE_I4:
4236 ARM_DMB (code, ARM_DMB_SY);
4237 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4238 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4239 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4241 ARM_B_COND (code, ARMCOND_NE, 0);
4242 arm_patch (buf [1], buf [0]);
4244 case OP_ATOMIC_CAS_I4:
4245 ARM_DMB (code, ARM_DMB_SY);
4247 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4248 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4250 ARM_B_COND (code, ARMCOND_NE, 0);
4251 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4252 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4254 ARM_B_COND (code, ARMCOND_NE, 0);
4255 arm_patch (buf [2], buf [0]);
4256 arm_patch (buf [1], code);
4258 case OP_ATOMIC_ADD_I4:
4260 ARM_DMB (code, ARM_DMB_SY);
4261 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4262 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4263 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4264 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4266 ARM_B_COND (code, ARMCOND_NE, 0);
4267 arm_patch (buf [1], buf [0]);
4270 g_assert_not_reached ();
4273 ARM_DMB (code, ARM_DMB_SY);
4274 if (tmpreg != ins->dreg)
4275 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4276 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4279 case OP_ATOMIC_LOAD_I1:
4280 case OP_ATOMIC_LOAD_U1:
4281 case OP_ATOMIC_LOAD_I2:
4282 case OP_ATOMIC_LOAD_U2:
4283 case OP_ATOMIC_LOAD_I4:
4284 case OP_ATOMIC_LOAD_U4:
4285 case OP_ATOMIC_LOAD_R4:
4286 case OP_ATOMIC_LOAD_R8: {
4287 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4288 ARM_DMB (code, ARM_DMB_SY);
4290 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4292 switch (ins->opcode) {
4293 case OP_ATOMIC_LOAD_I1:
4294 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4296 case OP_ATOMIC_LOAD_U1:
4297 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4299 case OP_ATOMIC_LOAD_I2:
4300 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4302 case OP_ATOMIC_LOAD_U2:
4303 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4305 case OP_ATOMIC_LOAD_I4:
4306 case OP_ATOMIC_LOAD_U4:
4307 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4309 case OP_ATOMIC_LOAD_R4:
4311 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4312 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4314 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4315 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4316 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4317 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4318 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4321 case OP_ATOMIC_LOAD_R8:
4322 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4323 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4327 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4328 ARM_DMB (code, ARM_DMB_SY);
4331 case OP_ATOMIC_STORE_I1:
4332 case OP_ATOMIC_STORE_U1:
4333 case OP_ATOMIC_STORE_I2:
4334 case OP_ATOMIC_STORE_U2:
4335 case OP_ATOMIC_STORE_I4:
4336 case OP_ATOMIC_STORE_U4:
4337 case OP_ATOMIC_STORE_R4:
4338 case OP_ATOMIC_STORE_R8: {
4339 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4340 ARM_DMB (code, ARM_DMB_SY);
4342 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4344 switch (ins->opcode) {
4345 case OP_ATOMIC_STORE_I1:
4346 case OP_ATOMIC_STORE_U1:
4347 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4349 case OP_ATOMIC_STORE_I2:
4350 case OP_ATOMIC_STORE_U2:
4351 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4353 case OP_ATOMIC_STORE_I4:
4354 case OP_ATOMIC_STORE_U4:
4355 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4357 case OP_ATOMIC_STORE_R4:
4359 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4360 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4362 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4363 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4364 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4365 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4366 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4369 case OP_ATOMIC_STORE_R8:
4370 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4371 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4375 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4376 ARM_DMB (code, ARM_DMB_SY);
4380 ARM_SMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4383 ARM_UMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4385 case OP_STOREI1_MEMBASE_IMM:
4386 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4387 g_assert (arm_is_imm12 (ins->inst_offset));
4388 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4390 case OP_STOREI2_MEMBASE_IMM:
4391 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4392 g_assert (arm_is_imm8 (ins->inst_offset));
4393 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4395 case OP_STORE_MEMBASE_IMM:
4396 case OP_STOREI4_MEMBASE_IMM:
4397 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4398 g_assert (arm_is_imm12 (ins->inst_offset));
4399 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4401 case OP_STOREI1_MEMBASE_REG:
4402 g_assert (arm_is_imm12 (ins->inst_offset));
4403 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4405 case OP_STOREI2_MEMBASE_REG:
4406 g_assert (arm_is_imm8 (ins->inst_offset));
4407 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4409 case OP_STORE_MEMBASE_REG:
4410 case OP_STOREI4_MEMBASE_REG:
4411 /* this case is special, since it happens for spill code after lowering has been called */
4412 if (arm_is_imm12 (ins->inst_offset)) {
4413 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4415 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4416 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4419 case OP_STOREI1_MEMINDEX:
4420 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4422 case OP_STOREI2_MEMINDEX:
4423 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4425 case OP_STORE_MEMINDEX:
4426 case OP_STOREI4_MEMINDEX:
4427 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4430 g_assert_not_reached ();
4432 case OP_LOAD_MEMINDEX:
4433 case OP_LOADI4_MEMINDEX:
4434 case OP_LOADU4_MEMINDEX:
4435 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4437 case OP_LOADI1_MEMINDEX:
4438 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4440 case OP_LOADU1_MEMINDEX:
4441 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4443 case OP_LOADI2_MEMINDEX:
4444 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4446 case OP_LOADU2_MEMINDEX:
4447 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4449 case OP_LOAD_MEMBASE:
4450 case OP_LOADI4_MEMBASE:
4451 case OP_LOADU4_MEMBASE:
4452 /* this case is special, since it happens for spill code after lowering has been called */
4453 if (arm_is_imm12 (ins->inst_offset)) {
4454 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4456 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4457 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4460 case OP_LOADI1_MEMBASE:
4461 g_assert (arm_is_imm8 (ins->inst_offset));
4462 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4464 case OP_LOADU1_MEMBASE:
4465 g_assert (arm_is_imm12 (ins->inst_offset));
4466 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4468 case OP_LOADU2_MEMBASE:
4469 g_assert (arm_is_imm8 (ins->inst_offset));
4470 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4472 case OP_LOADI2_MEMBASE:
4473 g_assert (arm_is_imm8 (ins->inst_offset));
4474 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4476 case OP_ICONV_TO_I1:
4477 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4478 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4480 case OP_ICONV_TO_I2:
4481 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4482 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4484 case OP_ICONV_TO_U1:
4485 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4487 case OP_ICONV_TO_U2:
4488 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4489 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4493 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4495 case OP_COMPARE_IMM:
4496 case OP_ICOMPARE_IMM:
4497 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4498 g_assert (imm8 >= 0);
4499 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4503 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4504 * So instead of emitting a trap, we emit a call a C function and place a
4507 //*(int*)code = 0xef9f0001;
4510 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4511 (gpointer)"mono_break");
4512 code = emit_call_seq (cfg, code);
4514 case OP_RELAXED_NOP:
4519 case OP_DUMMY_STORE:
4520 case OP_DUMMY_ICONST:
4521 case OP_DUMMY_R8CONST:
4522 case OP_NOT_REACHED:
4525 case OP_IL_SEQ_POINT:
4526 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4528 case OP_SEQ_POINT: {
4530 MonoInst *info_var = cfg->arch.seq_point_info_var;
4531 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4532 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4533 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4535 int dreg = ARMREG_LR;
4538 if (cfg->soft_breakpoints) {
4539 g_assert (!cfg->compile_aot);
4544 * For AOT, we use one got slot per method, which will point to a
4545 * SeqPointInfo structure, containing all the information required
4546 * by the code below.
4548 if (cfg->compile_aot) {
4549 g_assert (info_var);
4550 g_assert (info_var->opcode == OP_REGOFFSET);
4551 g_assert (arm_is_imm12 (info_var->inst_offset));
4554 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4556 * Read from the single stepping trigger page. This will cause a
4557 * SIGSEGV when single stepping is enabled.
4558 * We do this _before_ the breakpoint, so single stepping after
4559 * a breakpoint is hit will step to the next IL offset.
4561 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4564 /* Single step check */
4565 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4566 if (cfg->soft_breakpoints) {
4567 /* Load the address of the sequence point method variable. */
4568 var = ss_method_var;
4570 g_assert (var->opcode == OP_REGOFFSET);
4571 g_assert (arm_is_imm12 (var->inst_offset));
4572 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4574 /* Read the value and check whether it is non-zero. */
4575 ARM_LDR_IMM (code, dreg, dreg, 0);
4576 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4577 /* Call it conditionally. */
4578 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4580 if (cfg->compile_aot) {
4581 /* Load the trigger page addr from the variable initialized in the prolog */
4582 var = ss_trigger_page_var;
4584 g_assert (var->opcode == OP_REGOFFSET);
4585 g_assert (arm_is_imm12 (var->inst_offset));
4586 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4588 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4590 *(int*)code = (int)ss_trigger_page;
4593 ARM_LDR_IMM (code, dreg, dreg, 0);
4597 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4599 /* Breakpoint check */
4600 if (cfg->compile_aot) {
4601 guint32 offset = code - cfg->native_code;
4604 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4605 /* Add the offset */
4606 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4607 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4608 if (arm_is_imm12 ((int)val)) {
4609 ARM_LDR_IMM (code, dreg, dreg, val);
4611 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4613 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4615 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4616 g_assert (!(val & 0xFF000000));
4618 ARM_LDR_IMM (code, dreg, dreg, 0);
4620 /* What is faster, a branch or a load ? */
4621 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4622 /* The breakpoint instruction */
4623 if (cfg->soft_breakpoints)
4624 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4626 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4627 } else if (cfg->soft_breakpoints) {
4628 /* Load the address of the breakpoint method into ip. */
4629 var = bp_method_var;
4631 g_assert (var->opcode == OP_REGOFFSET);
4632 g_assert (arm_is_imm12 (var->inst_offset));
4633 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4636 * A placeholder for a possible breakpoint inserted by
4637 * mono_arch_set_breakpoint ().
4642 * A placeholder for a possible breakpoint inserted by
4643 * mono_arch_set_breakpoint ().
4645 for (i = 0; i < 4; ++i)
4650 * Add an additional nop so skipping the bp doesn't cause the ip to point
4651 * to another IL offset.
4659 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4662 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4666 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4669 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4670 g_assert (imm8 >= 0);
4671 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4675 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4676 g_assert (imm8 >= 0);
4677 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4681 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4682 g_assert (imm8 >= 0);
4683 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4686 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4687 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4689 case OP_IADD_OVF_UN:
4690 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4691 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4694 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4695 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4697 case OP_ISUB_OVF_UN:
4698 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4699 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4701 case OP_ADD_OVF_CARRY:
4702 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4703 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4705 case OP_ADD_OVF_UN_CARRY:
4706 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4707 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4709 case OP_SUB_OVF_CARRY:
4710 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4711 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4713 case OP_SUB_OVF_UN_CARRY:
4714 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4715 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4719 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4722 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4723 g_assert (imm8 >= 0);
4724 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4727 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4731 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4735 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4736 g_assert (imm8 >= 0);
4737 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4741 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4742 g_assert (imm8 >= 0);
4743 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4745 case OP_ARM_RSBS_IMM:
4746 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4747 g_assert (imm8 >= 0);
4748 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4750 case OP_ARM_RSC_IMM:
4751 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4752 g_assert (imm8 >= 0);
4753 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4756 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4760 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4761 g_assert (imm8 >= 0);
4762 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4765 g_assert (v7s_supported || v7k_supported);
4766 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4769 g_assert (v7s_supported || v7k_supported);
4770 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4773 g_assert (v7s_supported || v7k_supported);
4774 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4775 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4778 g_assert (v7s_supported || v7k_supported);
4779 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4780 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4784 g_assert_not_reached ();
4786 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4790 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4791 g_assert (imm8 >= 0);
4792 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4795 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4799 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4800 g_assert (imm8 >= 0);
4801 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4804 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4809 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4810 else if (ins->dreg != ins->sreg1)
4811 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4814 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4819 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4820 else if (ins->dreg != ins->sreg1)
4821 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4824 case OP_ISHR_UN_IMM:
4826 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4827 else if (ins->dreg != ins->sreg1)
4828 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4831 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4834 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4837 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4840 if (ins->dreg == ins->sreg2)
4841 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4843 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4846 g_assert_not_reached ();
4849 /* FIXME: handle ovf/ sreg2 != dreg */
4850 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4851 /* FIXME: MUL doesn't set the C/O flags on ARM */
4853 case OP_IMUL_OVF_UN:
4854 /* FIXME: handle ovf/ sreg2 != dreg */
4855 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4856 /* FIXME: MUL doesn't set the C/O flags on ARM */
4859 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4862 /* Load the GOT offset */
4863 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4864 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4866 *(gpointer*)code = NULL;
4868 /* Load the value from the GOT */
4869 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4871 case OP_OBJC_GET_SELECTOR:
4872 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4873 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4875 *(gpointer*)code = NULL;
4877 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4879 case OP_ICONV_TO_I4:
4880 case OP_ICONV_TO_U4:
4882 if (ins->dreg != ins->sreg1)
4883 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4886 int saved = ins->sreg2;
4887 if (ins->sreg2 == ARM_LSW_REG) {
4888 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4891 if (ins->sreg1 != ARM_LSW_REG)
4892 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4893 if (saved != ARM_MSW_REG)
4894 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4898 if (IS_VFP && ins->dreg != ins->sreg1)
4899 ARM_CPYD (code, ins->dreg, ins->sreg1);
4902 if (IS_VFP && ins->dreg != ins->sreg1)
4903 ARM_CPYS (code, ins->dreg, ins->sreg1);
4905 case OP_MOVE_F_TO_I4:
4907 ARM_FMRS (code, ins->dreg, ins->sreg1);
4909 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4910 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4911 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4912 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4915 case OP_MOVE_I4_TO_F:
4917 ARM_FMSR (code, ins->dreg, ins->sreg1);
4919 ARM_FMSR (code, ins->dreg, ins->sreg1);
4920 ARM_CVTS (code, ins->dreg, ins->dreg);
4923 case OP_FCONV_TO_R4:
4926 ARM_CVTD (code, ins->dreg, ins->sreg1);
4928 ARM_CVTD (code, ins->dreg, ins->sreg1);
4929 ARM_CVTS (code, ins->dreg, ins->dreg);
4934 MonoCallInst *call = (MonoCallInst*)ins;
4937 * The stack looks like the following:
4938 * <caller argument area>
4941 * <callee argument area>
4942 * Need to copy the arguments from the callee argument area to
4943 * the caller argument area, and pop the frame.
4945 if (call->stack_usage) {
4946 int i, prev_sp_offset = 0;
4948 /* Compute size of saved registers restored below */
4950 prev_sp_offset = 2 * 4;
4952 prev_sp_offset = 1 * 4;
4953 for (i = 0; i < 16; ++i) {
4954 if (cfg->used_int_regs & (1 << i))
4955 prev_sp_offset += 4;
4958 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
4960 /* Copy arguments on the stack to our argument area */
4961 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
4962 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
4963 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
4968 * Keep in sync with mono_arch_emit_epilog
4970 g_assert (!cfg->method->save_lmf);
4972 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4974 if (cfg->used_int_regs)
4975 ARM_POP (code, cfg->used_int_regs);
4976 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4978 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4981 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4982 if (cfg->compile_aot) {
4983 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
4985 *(gpointer*)code = NULL;
4987 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
4989 code = mono_arm_patchable_b (code, ARMCOND_AL);
4990 cfg->thunk_area += THUNK_SIZE;
4995 /* ensure ins->sreg1 is not NULL */
4996 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
4999 g_assert (cfg->sig_cookie < 128);
5000 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5001 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5011 call = (MonoCallInst*)ins;
5014 code = emit_float_args (cfg, call, code, &max_len, &offset);
5016 if (ins->flags & MONO_INST_HAS_METHOD)
5017 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5019 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5020 code = emit_call_seq (cfg, code);
5021 ins->flags |= MONO_INST_GC_CALLSITE;
5022 ins->backend.pc_offset = code - cfg->native_code;
5023 code = emit_move_return_value (cfg, ins, code);
5030 case OP_VOIDCALL_REG:
5033 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5035 code = emit_call_reg (code, ins->sreg1);
5036 ins->flags |= MONO_INST_GC_CALLSITE;
5037 ins->backend.pc_offset = code - cfg->native_code;
5038 code = emit_move_return_value (cfg, ins, code);
5040 case OP_FCALL_MEMBASE:
5041 case OP_RCALL_MEMBASE:
5042 case OP_LCALL_MEMBASE:
5043 case OP_VCALL_MEMBASE:
5044 case OP_VCALL2_MEMBASE:
5045 case OP_VOIDCALL_MEMBASE:
5046 case OP_CALL_MEMBASE: {
5047 g_assert (ins->sreg1 != ARMREG_LR);
5048 call = (MonoCallInst*)ins;
5051 code = emit_float_args (cfg, call, code, &max_len, &offset);
5052 if (!arm_is_imm12 (ins->inst_offset)) {
5053 /* sreg1 might be IP */
5054 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5055 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5056 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_LR);
5057 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5058 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, 0);
5060 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5061 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5063 ins->flags |= MONO_INST_GC_CALLSITE;
5064 ins->backend.pc_offset = code - cfg->native_code;
5065 code = emit_move_return_value (cfg, ins, code);
5068 case OP_GENERIC_CLASS_INIT: {
5072 byte_offset = MONO_STRUCT_OFFSET (MonoVTable, initialized);
5074 g_assert (arm_is_imm8 (byte_offset));
5075 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5076 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5078 ARM_B_COND (code, ARMCOND_NE, 0);
5080 /* Uninitialized case */
5081 g_assert (ins->sreg1 == ARMREG_R0);
5083 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5084 (gpointer)"mono_generic_class_init");
5085 code = emit_call_seq (cfg, code);
5087 /* Initialized case */
5088 arm_patch (jump, code);
5092 /* round the size to 8 bytes */
5093 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5094 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5095 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5096 /* memzero the area: dreg holds the size, sp is the pointer */
5097 if (ins->flags & MONO_INST_INIT) {
5098 guint8 *start_loop, *branch_to_cond;
5099 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5100 branch_to_cond = code;
5103 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5104 arm_patch (branch_to_cond, code);
5105 /* decrement by 4 and set flags */
5106 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5107 ARM_B_COND (code, ARMCOND_GE, 0);
5108 arm_patch (code - 4, start_loop);
5110 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5111 if (cfg->param_area)
5112 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5117 MonoInst *var = cfg->dyn_call_var;
5120 g_assert (var->opcode == OP_REGOFFSET);
5121 g_assert (arm_is_imm12 (var->inst_offset));
5123 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5124 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5126 ARM_MOV_REG_REG (code, ARMREG_IP, ins->sreg2);
5128 /* Save args buffer */
5129 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5131 /* Set stack slots using R0 as scratch reg */
5132 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5133 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5134 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5135 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5138 /* Set fp argument registers */
5139 if (IS_HARD_FLOAT) {
5140 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, has_fpregs));
5141 ARM_CMP_REG_IMM (code, ARMREG_R0, 0, 0);
5143 ARM_B_COND (code, ARMCOND_EQ, 0);
5144 for (i = 0; i < FP_PARAM_REGS; ++i) {
5145 int offset = MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * sizeof (double));
5146 g_assert (arm_is_fpimm8 (offset));
5147 ARM_FLDD (code, i * 2, ARMREG_LR, offset);
5149 arm_patch (buf [0], code);
5152 /* Set argument registers */
5153 for (i = 0; i < PARAM_REGS; ++i)
5154 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5157 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5158 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5161 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5162 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5163 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5165 ARM_FSTD (code, ARM_VFP_D0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, fpregs));
5169 if (ins->sreg1 != ARMREG_R0)
5170 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5171 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5172 (gpointer)"mono_arch_throw_exception");
5173 code = emit_call_seq (cfg, code);
5177 if (ins->sreg1 != ARMREG_R0)
5178 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5179 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5180 (gpointer)"mono_arch_rethrow_exception");
5181 code = emit_call_seq (cfg, code);
5184 case OP_START_HANDLER: {
5185 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5186 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5189 /* Reserve a param area, see filter-stack.exe */
5191 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5192 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5194 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5195 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5199 if (arm_is_imm12 (spvar->inst_offset)) {
5200 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5202 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5203 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5207 case OP_ENDFILTER: {
5208 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5209 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5212 /* Free the param area */
5214 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5215 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5217 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5218 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5222 if (ins->sreg1 != ARMREG_R0)
5223 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5224 if (arm_is_imm12 (spvar->inst_offset)) {
5225 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5227 g_assert (ARMREG_IP != spvar->inst_basereg);
5228 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5229 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5231 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5234 case OP_ENDFINALLY: {
5235 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5236 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5239 /* Free the param area */
5241 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5242 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5244 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5245 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5249 if (arm_is_imm12 (spvar->inst_offset)) {
5250 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5252 g_assert (ARMREG_IP != spvar->inst_basereg);
5253 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5254 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5256 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5259 case OP_CALL_HANDLER:
5260 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5261 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5262 cfg->thunk_area += THUNK_SIZE;
5263 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5266 if (ins->dreg != ARMREG_R0)
5267 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5271 ins->inst_c0 = code - cfg->native_code;
5274 /*if (ins->inst_target_bb->native_offset) {
5276 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5278 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5279 code = mono_arm_patchable_b (code, ARMCOND_AL);
5283 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5287 * In the normal case we have:
5288 * ldr pc, [pc, ins->sreg1 << 2]
5291 * ldr lr, [pc, ins->sreg1 << 2]
5293 * After follows the data.
5294 * FIXME: add aot support.
5296 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5297 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5298 if (offset + max_len > (cfg->code_size - 16)) {
5299 cfg->code_size += max_len;
5300 cfg->code_size *= 2;
5301 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5302 code = cfg->native_code + offset;
5304 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5306 code += 4 * GPOINTER_TO_INT (ins->klass);
5310 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5311 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5315 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5316 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5320 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5321 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5325 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5326 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5330 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5331 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5334 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5335 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5338 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5339 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5342 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5343 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5346 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5347 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5350 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5351 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5353 case OP_COND_EXC_EQ:
5354 case OP_COND_EXC_NE_UN:
5355 case OP_COND_EXC_LT:
5356 case OP_COND_EXC_LT_UN:
5357 case OP_COND_EXC_GT:
5358 case OP_COND_EXC_GT_UN:
5359 case OP_COND_EXC_GE:
5360 case OP_COND_EXC_GE_UN:
5361 case OP_COND_EXC_LE:
5362 case OP_COND_EXC_LE_UN:
5363 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5365 case OP_COND_EXC_IEQ:
5366 case OP_COND_EXC_INE_UN:
5367 case OP_COND_EXC_ILT:
5368 case OP_COND_EXC_ILT_UN:
5369 case OP_COND_EXC_IGT:
5370 case OP_COND_EXC_IGT_UN:
5371 case OP_COND_EXC_IGE:
5372 case OP_COND_EXC_IGE_UN:
5373 case OP_COND_EXC_ILE:
5374 case OP_COND_EXC_ILE_UN:
5375 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5378 case OP_COND_EXC_IC:
5379 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5381 case OP_COND_EXC_OV:
5382 case OP_COND_EXC_IOV:
5383 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5385 case OP_COND_EXC_NC:
5386 case OP_COND_EXC_INC:
5387 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5389 case OP_COND_EXC_NO:
5390 case OP_COND_EXC_INO:
5391 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5403 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5406 /* floating point opcodes */
5408 if (cfg->compile_aot) {
5409 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5411 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5413 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5416 /* FIXME: we can optimize the imm load by dealing with part of
5417 * the displacement in LDFD (aligning to 512).
5419 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5420 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5424 if (cfg->compile_aot) {
5425 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5427 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5430 ARM_CVTS (code, ins->dreg, ins->dreg);
5432 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5433 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5435 ARM_CVTS (code, ins->dreg, ins->dreg);
5438 case OP_STORER8_MEMBASE_REG:
5439 /* This is generated by the local regalloc pass which runs after the lowering pass */
5440 if (!arm_is_fpimm8 (ins->inst_offset)) {
5441 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5442 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5443 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5445 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5448 case OP_LOADR8_MEMBASE:
5449 /* This is generated by the local regalloc pass which runs after the lowering pass */
5450 if (!arm_is_fpimm8 (ins->inst_offset)) {
5451 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5452 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5453 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5455 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5458 case OP_STORER4_MEMBASE_REG:
5459 g_assert (arm_is_fpimm8 (ins->inst_offset));
5461 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5463 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5464 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5465 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5466 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5469 case OP_LOADR4_MEMBASE:
5471 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5473 g_assert (arm_is_fpimm8 (ins->inst_offset));
5474 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5475 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5476 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5477 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5480 case OP_ICONV_TO_R_UN: {
5481 g_assert_not_reached ();
5484 case OP_ICONV_TO_R4:
5486 ARM_FMSR (code, ins->dreg, ins->sreg1);
5487 ARM_FSITOS (code, ins->dreg, ins->dreg);
5489 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5490 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5491 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5492 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5493 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5496 case OP_ICONV_TO_R8:
5497 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5498 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5499 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5500 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5504 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5505 if (sig_ret->type == MONO_TYPE_R4) {
5507 if (IS_HARD_FLOAT) {
5508 if (ins->sreg1 != ARM_VFP_D0)
5509 ARM_CPYS (code, ARM_VFP_D0, ins->sreg1);
5511 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5514 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5517 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5521 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5523 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5527 case OP_FCONV_TO_I1:
5528 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5530 case OP_FCONV_TO_U1:
5531 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5533 case OP_FCONV_TO_I2:
5534 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5536 case OP_FCONV_TO_U2:
5537 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5539 case OP_FCONV_TO_I4:
5541 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5543 case OP_FCONV_TO_U4:
5545 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5547 case OP_FCONV_TO_I8:
5548 case OP_FCONV_TO_U8:
5549 g_assert_not_reached ();
5550 /* Implemented as helper calls */
5552 case OP_LCONV_TO_R_UN:
5553 g_assert_not_reached ();
5554 /* Implemented as helper calls */
5556 case OP_LCONV_TO_OVF_I4_2: {
5557 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5559 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5562 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5563 high_bit_not_set = code;
5564 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5566 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5567 valid_negative = code;
5568 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5569 invalid_negative = code;
5570 ARM_B_COND (code, ARMCOND_AL, 0);
5572 arm_patch (high_bit_not_set, code);
5574 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5575 valid_positive = code;
5576 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5578 arm_patch (invalid_negative, code);
5579 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5581 arm_patch (valid_negative, code);
5582 arm_patch (valid_positive, code);
5584 if (ins->dreg != ins->sreg1)
5585 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5589 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5592 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5595 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5598 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5601 ARM_NEGD (code, ins->dreg, ins->sreg1);
5605 g_assert_not_reached ();
5609 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5615 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5620 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5623 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5624 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5628 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5631 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5632 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5636 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5639 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5640 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5641 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5645 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5648 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5649 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5653 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5656 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5657 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5658 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5662 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5665 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5666 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5670 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5673 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5674 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5678 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5681 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5682 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5685 /* ARM FPA flags table:
5686 * N Less than ARMCOND_MI
5687 * Z Equal ARMCOND_EQ
5688 * C Greater Than or Equal ARMCOND_CS
5689 * V Unordered ARMCOND_VS
5692 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5695 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5698 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5701 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5702 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5708 g_assert_not_reached ();
5712 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5714 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5715 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5716 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5720 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5721 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5726 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5727 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5729 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5730 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5732 *(guint32*)code = 0xffffffff;
5734 *(guint32*)code = 0x7fefffff;
5736 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5738 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "OverflowException");
5739 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5741 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "OverflowException");
5742 ARM_CPYD (code, ins->dreg, ins->sreg1);
5744 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5745 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5750 case OP_RCONV_TO_I1:
5751 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5753 case OP_RCONV_TO_U1:
5754 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5756 case OP_RCONV_TO_I2:
5757 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5759 case OP_RCONV_TO_U2:
5760 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5762 case OP_RCONV_TO_I4:
5763 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5765 case OP_RCONV_TO_U4:
5766 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5768 case OP_RCONV_TO_R4:
5770 if (ins->dreg != ins->sreg1)
5771 ARM_CPYS (code, ins->dreg, ins->sreg1);
5773 case OP_RCONV_TO_R8:
5775 ARM_CVTS (code, ins->dreg, ins->sreg1);
5778 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5781 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5784 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5787 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5790 ARM_NEGS (code, ins->dreg, ins->sreg1);
5794 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5797 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5798 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5802 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5805 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5806 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5810 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5813 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5814 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5815 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5819 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5822 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5823 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5827 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5830 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5831 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5832 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5836 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5839 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5840 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5844 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5847 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5848 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5852 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5855 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5856 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5859 case OP_GC_LIVENESS_DEF:
5860 case OP_GC_LIVENESS_USE:
5861 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5862 ins->backend.pc_offset = code - cfg->native_code;
5864 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5865 ins->backend.pc_offset = code - cfg->native_code;
5866 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5868 case OP_GC_SAFE_POINT: {
5871 g_assert (mono_threads_is_coop_enabled ());
5873 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5874 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5876 ARM_B_COND (code, ARMCOND_EQ, 0);
5877 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
5878 code = emit_call_seq (cfg, code);
5879 arm_patch (buf [0], code);
5884 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5885 g_assert_not_reached ();
5888 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5889 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5890 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5891 g_assert_not_reached ();
5897 last_offset = offset;
5900 cfg->code_len = code - cfg->native_code;
5903 #endif /* DISABLE_JIT */
5906 mono_arch_register_lowlevel_calls (void)
5908 /* The signature doesn't matter */
5909 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5910 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5911 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
5914 #define patch_lis_ori(ip,val) do {\
5915 guint16 *__lis_ori = (guint16*)(ip); \
5916 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
5917 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
5921 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5923 unsigned char *ip = ji->ip.i + code;
5925 if (ji->type == MONO_PATCH_INFO_SWITCH) {
5929 case MONO_PATCH_INFO_SWITCH: {
5930 gpointer *jt = (gpointer*)(ip + 8);
5932 /* jt is the inlined jump table, 2 instructions after ip
5933 * In the normal case we store the absolute addresses,
5934 * otherwise the displacements.
5936 for (i = 0; i < ji->data.table->table_size; i++)
5937 jt [i] = code + (int)ji->data.table->table [i];
5940 case MONO_PATCH_INFO_IP:
5941 g_assert_not_reached ();
5942 patch_lis_ori (ip, ip);
5944 case MONO_PATCH_INFO_METHOD_REL:
5945 g_assert_not_reached ();
5946 *((gpointer *)(ip)) = target;
5948 case MONO_PATCH_INFO_METHODCONST:
5949 case MONO_PATCH_INFO_CLASS:
5950 case MONO_PATCH_INFO_IMAGE:
5951 case MONO_PATCH_INFO_FIELD:
5952 case MONO_PATCH_INFO_VTABLE:
5953 case MONO_PATCH_INFO_IID:
5954 case MONO_PATCH_INFO_SFLDA:
5955 case MONO_PATCH_INFO_LDSTR:
5956 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
5957 case MONO_PATCH_INFO_LDTOKEN:
5958 g_assert_not_reached ();
5959 /* from OP_AOTCONST : lis + ori */
5960 patch_lis_ori (ip, target);
5962 case MONO_PATCH_INFO_R4:
5963 case MONO_PATCH_INFO_R8:
5964 g_assert_not_reached ();
5965 *((gconstpointer *)(ip + 2)) = target;
5967 case MONO_PATCH_INFO_EXC_NAME:
5968 g_assert_not_reached ();
5969 *((gconstpointer *)(ip + 1)) = target;
5971 case MONO_PATCH_INFO_NONE:
5972 case MONO_PATCH_INFO_BB_OVF:
5973 case MONO_PATCH_INFO_EXC_OVF:
5974 /* everything is dealt with at epilog output time */
5977 arm_patch_general (cfg, domain, ip, target);
5983 mono_arm_unaligned_stack (MonoMethod *method)
5985 g_assert_not_reached ();
5991 * Stack frame layout:
5993 * ------------------- fp
5994 * MonoLMF structure or saved registers
5995 * -------------------
5997 * -------------------
5999 * -------------------
6000 * optional 8 bytes for tracing
6001 * -------------------
6002 * param area size is cfg->param_area
6003 * ------------------- sp
6006 mono_arch_emit_prolog (MonoCompile *cfg)
6008 MonoMethod *method = cfg->method;
6010 MonoMethodSignature *sig;
6012 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6017 int prev_sp_offset, reg_offset;
6019 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6022 sig = mono_method_signature (method);
6023 cfg->code_size = 256 + sig->param_count * 64;
6024 code = cfg->native_code = g_malloc (cfg->code_size);
6026 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6028 alloc_size = cfg->stack_offset;
6034 * The iphone uses R7 as the frame pointer, and it points at the saved
6039 * We can't use r7 as a frame pointer since it points into the middle of
6040 * the frame, so we keep using our own frame pointer.
6041 * FIXME: Optimize this.
6043 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6044 prev_sp_offset += 8; /* r7 and lr */
6045 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6046 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6047 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6050 if (!method->save_lmf) {
6052 /* No need to push LR again */
6053 if (cfg->used_int_regs)
6054 ARM_PUSH (code, cfg->used_int_regs);
6056 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6057 prev_sp_offset += 4;
6059 for (i = 0; i < 16; ++i) {
6060 if (cfg->used_int_regs & (1 << i))
6061 prev_sp_offset += 4;
6063 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6065 for (i = 0; i < 16; ++i) {
6066 if ((cfg->used_int_regs & (1 << i))) {
6067 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6068 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6072 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6073 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6075 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6076 ARM_PUSH (code, 0x5ff0);
6077 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6078 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6080 for (i = 0; i < 16; ++i) {
6081 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6082 /* The original r7 is saved at the start */
6083 if (!(iphone_abi && i == ARMREG_R7))
6084 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6088 g_assert (reg_offset == 4 * 10);
6089 pos += sizeof (MonoLMF) - (4 * 10);
6093 orig_alloc_size = alloc_size;
6094 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6095 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6096 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6097 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6100 /* the stack used in the pushed regs */
6101 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6102 cfg->stack_usage = alloc_size;
6104 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6105 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6107 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6108 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6110 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6112 if (cfg->frame_reg != ARMREG_SP) {
6113 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6114 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6116 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6117 prev_sp_offset += alloc_size;
6119 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6120 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6122 /* compute max_offset in order to use short forward jumps
6123 * we could skip do it on arm because the immediate displacement
6124 * for jumps is large enough, it may be useful later for constant pools
6127 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6128 MonoInst *ins = bb->code;
6129 bb->max_offset = max_offset;
6131 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6134 MONO_BB_FOR_EACH_INS (bb, ins)
6135 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6138 /* stack alignment check */
6142 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6143 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6144 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6145 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6147 ARM_B_COND (code, ARMCOND_EQ, 0);
6148 if (cfg->compile_aot)
6149 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6151 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6152 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6153 code = emit_call_seq (cfg, code);
6154 arm_patch (buf [0], code);
6158 /* store runtime generic context */
6159 if (cfg->rgctx_var) {
6160 MonoInst *ins = cfg->rgctx_var;
6162 g_assert (ins->opcode == OP_REGOFFSET);
6164 if (arm_is_imm12 (ins->inst_offset)) {
6165 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6167 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6168 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6172 /* load arguments allocated to register from the stack */
6175 cinfo = get_call_info (NULL, sig);
6177 if (cinfo->ret.storage == RegTypeStructByAddr) {
6178 ArgInfo *ainfo = &cinfo->ret;
6179 inst = cfg->vret_addr;
6180 g_assert (arm_is_imm12 (inst->inst_offset));
6181 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6184 if (sig->call_convention == MONO_CALL_VARARG) {
6185 ArgInfo *cookie = &cinfo->sig_cookie;
6187 /* Save the sig cookie address */
6188 g_assert (cookie->storage == RegTypeBase);
6190 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6191 g_assert (arm_is_imm12 (cfg->sig_cookie));
6192 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6193 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6196 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6197 ArgInfo *ainfo = cinfo->args + i;
6198 inst = cfg->args [pos];
6200 if (cfg->verbose_level > 2)
6201 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6203 if (inst->opcode == OP_REGVAR) {
6204 if (ainfo->storage == RegTypeGeneral)
6205 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6206 else if (ainfo->storage == RegTypeFP) {
6207 g_assert_not_reached ();
6208 } else if (ainfo->storage == RegTypeBase) {
6209 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6210 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6212 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6213 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6216 g_assert_not_reached ();
6218 if (cfg->verbose_level > 2)
6219 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6221 switch (ainfo->storage) {
6223 for (part = 0; part < ainfo->nregs; part ++) {
6224 if (ainfo->esize == 4)
6225 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6227 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6230 case RegTypeGeneral:
6231 case RegTypeIRegPair:
6232 case RegTypeGSharedVtInReg:
6233 case RegTypeStructByAddr:
6234 switch (ainfo->size) {
6236 if (arm_is_imm12 (inst->inst_offset))
6237 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6239 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6240 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6244 if (arm_is_imm8 (inst->inst_offset)) {
6245 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6247 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6248 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6252 if (arm_is_imm12 (inst->inst_offset)) {
6253 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6255 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6256 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6258 if (arm_is_imm12 (inst->inst_offset + 4)) {
6259 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6261 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6262 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6266 if (arm_is_imm12 (inst->inst_offset)) {
6267 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6269 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6270 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6275 case RegTypeBaseGen:
6276 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6277 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6279 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6280 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6282 if (arm_is_imm12 (inst->inst_offset + 4)) {
6283 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6284 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6286 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6287 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6288 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6289 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6293 case RegTypeGSharedVtOnStack:
6294 case RegTypeStructByAddrOnStack:
6295 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6296 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6298 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6299 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6302 switch (ainfo->size) {
6304 if (arm_is_imm8 (inst->inst_offset)) {
6305 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6307 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6308 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6312 if (arm_is_imm8 (inst->inst_offset)) {
6313 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6315 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6316 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6320 if (arm_is_imm12 (inst->inst_offset)) {
6321 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6323 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6324 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6326 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6327 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6329 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6330 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6332 if (arm_is_imm12 (inst->inst_offset + 4)) {
6333 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6335 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6336 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6340 if (arm_is_imm12 (inst->inst_offset)) {
6341 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6343 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6344 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6350 int imm8, rot_amount;
6352 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6353 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6354 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6356 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6358 if (ainfo->size == 8)
6359 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6361 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6364 case RegTypeStructByVal: {
6365 int doffset = inst->inst_offset;
6369 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6370 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6371 if (arm_is_imm12 (doffset)) {
6372 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6374 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6375 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6377 soffset += sizeof (gpointer);
6378 doffset += sizeof (gpointer);
6380 if (ainfo->vtsize) {
6381 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6382 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6383 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6388 g_assert_not_reached ();
6395 if (method->save_lmf)
6396 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6399 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6401 if (cfg->arch.seq_point_info_var) {
6402 MonoInst *ins = cfg->arch.seq_point_info_var;
6404 /* Initialize the variable from a GOT slot */
6405 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6406 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6408 *(gpointer*)code = NULL;
6410 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6412 g_assert (ins->opcode == OP_REGOFFSET);
6414 if (arm_is_imm12 (ins->inst_offset)) {
6415 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6417 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6418 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6422 /* Initialize ss_trigger_page_var */
6423 if (!cfg->soft_breakpoints) {
6424 MonoInst *info_var = cfg->arch.seq_point_info_var;
6425 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6426 int dreg = ARMREG_LR;
6429 g_assert (info_var->opcode == OP_REGOFFSET);
6430 g_assert (arm_is_imm12 (info_var->inst_offset));
6432 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6433 /* Load the trigger page addr */
6434 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6435 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6439 if (cfg->arch.seq_point_ss_method_var) {
6440 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6441 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6443 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6444 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6446 if (cfg->compile_aot) {
6447 MonoInst *info_var = cfg->arch.seq_point_info_var;
6448 int dreg = ARMREG_LR;
6450 g_assert (info_var->opcode == OP_REGOFFSET);
6451 g_assert (arm_is_imm12 (info_var->inst_offset));
6453 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6454 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr));
6455 ARM_STR_IMM (code, dreg, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6457 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6458 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6460 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6462 *(gpointer*)code = &single_step_tramp;
6464 *(gpointer*)code = breakpoint_tramp;
6467 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6468 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6469 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6470 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6474 cfg->code_len = code - cfg->native_code;
6475 g_assert (cfg->code_len < cfg->code_size);
6482 mono_arch_emit_epilog (MonoCompile *cfg)
6484 MonoMethod *method = cfg->method;
6485 int pos, i, rot_amount;
6486 int max_epilog_size = 16 + 20*4;
6490 if (cfg->method->save_lmf)
6491 max_epilog_size += 128;
6493 if (mono_jit_trace_calls != NULL)
6494 max_epilog_size += 50;
6496 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6497 max_epilog_size += 50;
6499 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6500 cfg->code_size *= 2;
6501 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6502 cfg->stat_code_reallocs++;
6506 * Keep in sync with OP_JMP
6508 code = cfg->native_code + cfg->code_len;
6510 /* Save the uwind state which is needed by the out-of-line code */
6511 mono_emit_unwind_op_remember_state (cfg, code);
6513 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6514 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6518 /* Load returned vtypes into registers if needed */
6519 cinfo = cfg->arch.cinfo;
6520 switch (cinfo->ret.storage) {
6521 case RegTypeStructByVal: {
6522 MonoInst *ins = cfg->ret;
6524 if (cinfo->ret.nregs == 1) {
6525 if (arm_is_imm12 (ins->inst_offset)) {
6526 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6528 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6529 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6532 for (i = 0; i < cinfo->ret.nregs; ++i) {
6533 int offset = ins->inst_offset + (i * 4);
6534 if (arm_is_imm12 (offset)) {
6535 ARM_LDR_IMM (code, i, ins->inst_basereg, offset);
6537 code = mono_arm_emit_load_imm (code, ARMREG_LR, offset);
6538 ARM_LDR_REG_REG (code, i, ins->inst_basereg, ARMREG_LR);
6545 MonoInst *ins = cfg->ret;
6547 for (i = 0; i < cinfo->ret.nregs; ++i) {
6548 if (cinfo->ret.esize == 4)
6549 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6551 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6559 if (method->save_lmf) {
6560 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6561 /* all but r0-r3, sp and pc */
6562 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6565 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6567 /* This points to r4 inside MonoLMF->iregs */
6568 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6570 regmask = 0x9ff0; /* restore lr to pc */
6571 /* Skip caller saved registers not used by the method */
6572 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6573 regmask &= ~(1 << reg);
6578 /* Restored later */
6579 regmask &= ~(1 << ARMREG_PC);
6580 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6581 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6582 for (i = 0; i < 16; i++) {
6583 if (regmask & (1 << i))
6586 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6588 ARM_POP (code, regmask);
6590 for (i = 0; i < 16; i++) {
6591 if (regmask & (1 << i))
6592 mono_emit_unwind_op_same_value (cfg, code, i);
6594 /* Restore saved r7, restore LR to PC */
6595 /* Skip lr from the lmf */
6596 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6597 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6598 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6599 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6602 int i, nused_int_regs = 0;
6604 for (i = 0; i < 16; i++) {
6605 if (cfg->used_int_regs & (1 << i))
6609 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6610 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6612 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6613 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6616 if (cfg->frame_reg != ARMREG_SP) {
6617 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6621 /* Restore saved gregs */
6622 if (cfg->used_int_regs) {
6623 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6624 ARM_POP (code, cfg->used_int_regs);
6625 for (i = 0; i < 16; i++) {
6626 if (cfg->used_int_regs & (1 << i))
6627 mono_emit_unwind_op_same_value (cfg, code, i);
6630 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6631 /* Restore saved r7, restore LR to PC */
6632 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6634 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6635 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6639 /* Restore the unwind state to be the same as before the epilog */
6640 mono_emit_unwind_op_restore_state (cfg, code);
6642 cfg->code_len = code - cfg->native_code;
6644 g_assert (cfg->code_len < cfg->code_size);
6649 mono_arch_emit_exceptions (MonoCompile *cfg)
6651 MonoJumpInfo *patch_info;
6654 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6655 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6656 int max_epilog_size = 50;
6658 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6659 exc_throw_pos [i] = NULL;
6660 exc_throw_found [i] = 0;
6663 /* count the number of exception infos */
6666 * make sure we have enough space for exceptions
6668 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6669 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6670 i = mini_exception_id_by_name (patch_info->data.target);
6671 if (!exc_throw_found [i]) {
6672 max_epilog_size += 32;
6673 exc_throw_found [i] = TRUE;
6678 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6679 cfg->code_size *= 2;
6680 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6681 cfg->stat_code_reallocs++;
6684 code = cfg->native_code + cfg->code_len;
6686 /* add code to raise exceptions */
6687 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6688 switch (patch_info->type) {
6689 case MONO_PATCH_INFO_EXC: {
6690 MonoClass *exc_class;
6691 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6693 i = mini_exception_id_by_name (patch_info->data.target);
6694 if (exc_throw_pos [i]) {
6695 arm_patch (ip, exc_throw_pos [i]);
6696 patch_info->type = MONO_PATCH_INFO_NONE;
6699 exc_throw_pos [i] = code;
6701 arm_patch (ip, code);
6703 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6705 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6706 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6707 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6708 patch_info->data.name = "mono_arch_throw_corlib_exception";
6709 patch_info->ip.i = code - cfg->native_code;
6711 cfg->thunk_area += THUNK_SIZE;
6712 *(guint32*)(gpointer)code = exc_class->type_token - MONO_TOKEN_TYPE_DEF;
6722 cfg->code_len = code - cfg->native_code;
6724 g_assert (cfg->code_len < cfg->code_size);
6728 #endif /* #ifndef DISABLE_JIT */
6731 mono_arch_finish_init (void)
6736 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6741 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6748 mono_arch_print_tree (MonoInst *tree, int arity)
6758 mono_arch_get_patch_offset (guint8 *code)
6765 mono_arch_flush_register_windows (void)
6770 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6772 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6776 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6778 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6782 mono_arch_get_cie_program (void)
6786 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6791 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6792 #define BASE_SIZE (6 * 4)
6793 #define BSEARCH_ENTRY_SIZE (4 * 4)
6794 #define CMP_SIZE (3 * 4)
6795 #define BRANCH_SIZE (1 * 4)
6796 #define CALL_SIZE (2 * 4)
6797 #define WMC_SIZE (8 * 4)
6798 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6801 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6803 guint32 delta = DISTANCE (target, code);
6805 g_assert (delta >= 0 && delta <= 0xFFF);
6806 *target = *target | delta;
6811 #ifdef ENABLE_WRONG_METHOD_CHECK
6813 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6815 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6821 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6822 gpointer fail_tramp)
6825 arminstr_t *code, *start;
6826 gboolean large_offsets = FALSE;
6827 guint32 **constant_pool_starts;
6828 arminstr_t *vtable_target = NULL;
6829 int extra_space = 0;
6830 #ifdef ENABLE_WRONG_METHOD_CHECK
6836 constant_pool_starts = g_new0 (guint32*, count);
6838 for (i = 0; i < count; ++i) {
6839 MonoIMTCheckItem *item = imt_entries [i];
6840 if (item->is_equals) {
6841 gboolean fail_case = !item->check_target_idx && fail_tramp;
6843 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6844 item->chunk_size += 32;
6845 large_offsets = TRUE;
6848 if (item->check_target_idx || fail_case) {
6849 if (!item->compare_done || fail_case)
6850 item->chunk_size += CMP_SIZE;
6851 item->chunk_size += BRANCH_SIZE;
6853 #ifdef ENABLE_WRONG_METHOD_CHECK
6854 item->chunk_size += WMC_SIZE;
6858 item->chunk_size += 16;
6859 large_offsets = TRUE;
6861 item->chunk_size += CALL_SIZE;
6863 item->chunk_size += BSEARCH_ENTRY_SIZE;
6864 imt_entries [item->check_target_idx]->compare_done = TRUE;
6866 size += item->chunk_size;
6870 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6873 code = mono_method_alloc_generic_virtual_trampoline (domain, size);
6875 code = mono_domain_code_reserve (domain, size);
6878 unwind_ops = mono_arch_get_cie_program ();
6881 g_print ("Building IMT trampoline for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6882 for (i = 0; i < count; ++i) {
6883 MonoIMTCheckItem *item = imt_entries [i];
6884 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
6888 if (large_offsets) {
6889 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6890 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
6892 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
6893 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6895 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
6896 vtable_target = code;
6897 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
6898 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
6900 for (i = 0; i < count; ++i) {
6901 MonoIMTCheckItem *item = imt_entries [i];
6902 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
6903 gint32 vtable_offset;
6905 item->code_target = (guint8*)code;
6907 if (item->is_equals) {
6908 gboolean fail_case = !item->check_target_idx && fail_tramp;
6910 if (item->check_target_idx || fail_case) {
6911 if (!item->compare_done || fail_case) {
6913 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6914 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6916 item->jmp_code = (guint8*)code;
6917 ARM_B_COND (code, ARMCOND_NE, 0);
6919 /*Enable the commented code to assert on wrong method*/
6920 #ifdef ENABLE_WRONG_METHOD_CHECK
6922 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6923 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6925 ARM_B_COND (code, ARMCOND_EQ, 0);
6927 /* Define this if your system is so bad that gdb is failing. */
6928 #ifdef BROKEN_DEV_ENV
6929 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
6931 arm_patch (code - 1, mini_dump_bad_imt);
6935 arm_patch (cond, code);
6939 if (item->has_target_code) {
6940 /* Load target address */
6941 target_code_ins = code;
6942 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6943 /* Save it to the fourth slot */
6944 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6945 /* Restore registers and branch */
6946 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6948 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
6950 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
6951 if (!arm_is_imm12 (vtable_offset)) {
6953 * We need to branch to a computed address but we don't have
6954 * a free register to store it, since IP must contain the
6955 * vtable address. So we push the two values to the stack, and
6956 * load them both using LDM.
6958 /* Compute target address */
6959 vtable_offset_ins = code;
6960 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6961 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
6962 /* Save it to the fourth slot */
6963 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6964 /* Restore registers and branch */
6965 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6967 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
6969 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
6970 if (large_offsets) {
6971 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6972 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
6974 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
6975 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
6980 arm_patch (item->jmp_code, (guchar*)code);
6982 target_code_ins = code;
6983 /* Load target address */
6984 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6985 /* Save it to the fourth slot */
6986 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6987 /* Restore registers and branch */
6988 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6990 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
6991 item->jmp_code = NULL;
6995 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
6997 /*must emit after unconditional branch*/
6998 if (vtable_target) {
6999 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7000 item->chunk_size += 4;
7001 vtable_target = NULL;
7004 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7005 constant_pool_starts [i] = code;
7007 code += extra_space;
7011 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7012 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7014 item->jmp_code = (guint8*)code;
7015 ARM_B_COND (code, ARMCOND_HS, 0);
7020 for (i = 0; i < count; ++i) {
7021 MonoIMTCheckItem *item = imt_entries [i];
7022 if (item->jmp_code) {
7023 if (item->check_target_idx)
7024 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7026 if (i > 0 && item->is_equals) {
7028 arminstr_t *space_start = constant_pool_starts [i];
7029 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7030 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7037 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7038 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7043 g_free (constant_pool_starts);
7045 mono_arch_flush_icache ((guint8*)start, size);
7046 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7047 mono_stats.imt_trampolines_size += code - start;
7049 g_assert (DISTANCE (start, code) <= size);
7051 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7057 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7059 return ctx->regs [reg];
7063 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7065 ctx->regs [reg] = val;
7069 * mono_arch_get_trampolines:
7071 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7075 mono_arch_get_trampolines (gboolean aot)
7077 return mono_arm_get_exception_trampolines (aot);
7081 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7088 bp = MONO_CONTEXT_GET_BP (ctx);
7089 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7091 old_value = *lr_loc;
7092 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7095 *lr_loc = new_value;
7100 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7102 * mono_arch_set_breakpoint:
7104 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7105 * The location should contain code emitted by OP_SEQ_POINT.
7108 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7111 guint32 native_offset = ip - (guint8*)ji->code_start;
7112 MonoDebugOptions *opt = mini_get_debug_options ();
7115 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7117 if (!breakpoint_tramp)
7118 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7120 g_assert (native_offset % 4 == 0);
7121 g_assert (info->bp_addrs [native_offset / 4] == 0);
7122 info->bp_addrs [native_offset / 4] = opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page;
7123 } else if (opt->soft_breakpoints) {
7125 ARM_BLX_REG (code, ARMREG_LR);
7126 mono_arch_flush_icache (code - 4, 4);
7128 int dreg = ARMREG_LR;
7130 /* Read from another trigger page */
7131 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7133 *(int*)code = (int)bp_trigger_page;
7135 ARM_LDR_IMM (code, dreg, dreg, 0);
7137 mono_arch_flush_icache (code - 16, 16);
7140 /* This is currently implemented by emitting an SWI instruction, which
7141 * qemu/linux seems to convert to a SIGILL.
7143 *(int*)code = (0xef << 24) | 8;
7145 mono_arch_flush_icache (code - 4, 4);
7151 * mono_arch_clear_breakpoint:
7153 * Clear the breakpoint at IP.
7156 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7158 MonoDebugOptions *opt = mini_get_debug_options ();
7163 guint32 native_offset = ip - (guint8*)ji->code_start;
7164 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7166 if (!breakpoint_tramp)
7167 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7169 g_assert (native_offset % 4 == 0);
7170 g_assert (info->bp_addrs [native_offset / 4] == (opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page));
7171 info->bp_addrs [native_offset / 4] = 0;
7172 } else if (opt->soft_breakpoints) {
7175 mono_arch_flush_icache (code - 4, 4);
7177 for (i = 0; i < 4; ++i)
7180 mono_arch_flush_icache (ip, code - ip);
7185 * mono_arch_start_single_stepping:
7187 * Start single stepping.
7190 mono_arch_start_single_stepping (void)
7192 if (ss_trigger_page)
7193 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7195 single_step_tramp = mini_get_single_step_trampoline ();
7199 * mono_arch_stop_single_stepping:
7201 * Stop single stepping.
7204 mono_arch_stop_single_stepping (void)
7206 if (ss_trigger_page)
7207 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7209 single_step_tramp = NULL;
7213 #define DBG_SIGNAL SIGBUS
7215 #define DBG_SIGNAL SIGSEGV
7219 * mono_arch_is_single_step_event:
7221 * Return whenever the machine state in SIGCTX corresponds to a single
7225 mono_arch_is_single_step_event (void *info, void *sigctx)
7227 siginfo_t *sinfo = info;
7229 if (!ss_trigger_page)
7232 /* Sometimes the address is off by 4 */
7233 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7240 * mono_arch_is_breakpoint_event:
7242 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7245 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7247 siginfo_t *sinfo = info;
7249 if (!ss_trigger_page)
7252 if (sinfo->si_signo == DBG_SIGNAL) {
7253 /* Sometimes the address is off by 4 */
7254 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7264 * mono_arch_skip_breakpoint:
7266 * See mini-amd64.c for docs.
7269 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7271 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7275 * mono_arch_skip_single_step:
7277 * See mini-amd64.c for docs.
7280 mono_arch_skip_single_step (MonoContext *ctx)
7282 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7285 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7288 * mono_arch_get_seq_point_info:
7290 * See mini-amd64.c for docs.
7293 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7298 // FIXME: Add a free function
7300 mono_domain_lock (domain);
7301 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7303 mono_domain_unlock (domain);
7306 ji = mono_jit_info_table_find (domain, (char*)code);
7309 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7311 info->ss_trigger_page = ss_trigger_page;
7312 info->bp_trigger_page = bp_trigger_page;
7313 info->ss_tramp_addr = &single_step_tramp;
7315 mono_domain_lock (domain);
7316 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7318 mono_domain_unlock (domain);
7325 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7327 ext->lmf.previous_lmf = prev_lmf;
7328 /* Mark that this is a MonoLMFExt */
7329 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7330 ext->lmf.sp = (gssize)ext;
7334 * mono_arch_set_target:
7336 * Set the target architecture the JIT backend should generate code for, in the form
7337 * of a GNU target triplet. Only used in AOT mode.
7340 mono_arch_set_target (char *mtriple)
7342 /* The GNU target triple format is not very well documented */
7343 if (strstr (mtriple, "armv7")) {
7344 v5_supported = TRUE;
7345 v6_supported = TRUE;
7346 v7_supported = TRUE;
7348 if (strstr (mtriple, "armv6")) {
7349 v5_supported = TRUE;
7350 v6_supported = TRUE;
7352 if (strstr (mtriple, "armv7s")) {
7353 v7s_supported = TRUE;
7355 if (strstr (mtriple, "armv7k")) {
7356 v7k_supported = TRUE;
7358 if (strstr (mtriple, "thumbv7s")) {
7359 v5_supported = TRUE;
7360 v6_supported = TRUE;
7361 v7_supported = TRUE;
7362 v7s_supported = TRUE;
7363 thumb_supported = TRUE;
7364 thumb2_supported = TRUE;
7366 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7367 v5_supported = TRUE;
7368 v6_supported = TRUE;
7369 thumb_supported = TRUE;
7372 if (strstr (mtriple, "gnueabi"))
7373 eabi_supported = TRUE;
7377 mono_arch_opcode_supported (int opcode)
7380 case OP_ATOMIC_ADD_I4:
7381 case OP_ATOMIC_EXCHANGE_I4:
7382 case OP_ATOMIC_CAS_I4:
7383 case OP_ATOMIC_LOAD_I1:
7384 case OP_ATOMIC_LOAD_I2:
7385 case OP_ATOMIC_LOAD_I4:
7386 case OP_ATOMIC_LOAD_U1:
7387 case OP_ATOMIC_LOAD_U2:
7388 case OP_ATOMIC_LOAD_U4:
7389 case OP_ATOMIC_STORE_I1:
7390 case OP_ATOMIC_STORE_I2:
7391 case OP_ATOMIC_STORE_I4:
7392 case OP_ATOMIC_STORE_U1:
7393 case OP_ATOMIC_STORE_U2:
7394 case OP_ATOMIC_STORE_U4:
7395 return v7_supported;
7396 case OP_ATOMIC_LOAD_R4:
7397 case OP_ATOMIC_LOAD_R8:
7398 case OP_ATOMIC_STORE_R4:
7399 case OP_ATOMIC_STORE_R8:
7400 return v7_supported && IS_VFP;
7407 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
7409 return get_call_info (mp, sig);
7413 mono_arch_get_get_tls_tramp (void)
7419 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data)
7422 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
7423 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7425 *(gpointer*)code = NULL;
7427 /* Load the value from the GOT */
7428 ARM_LDR_REG_REG (code, dreg, ARMREG_PC, dreg);
7433 mono_arm_emit_aotconst (gpointer ji_list, guint8 *code, guint8 *buf, int dreg, int patch_type, gconstpointer data)
7435 MonoJumpInfo **ji = (MonoJumpInfo**)ji_list;
7437 *ji = mono_patch_info_list_prepend (*ji, code - buf, patch_type, data);
7438 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7440 *(gpointer*)code = NULL;
7442 ARM_LDR_REG_REG (code, dreg, ARMREG_PC, dreg);